CN112652661A - Transistor and preparation method thereof - Google Patents

Transistor and preparation method thereof Download PDF

Info

Publication number
CN112652661A
CN112652661A CN201910959540.5A CN201910959540A CN112652661A CN 112652661 A CN112652661 A CN 112652661A CN 201910959540 A CN201910959540 A CN 201910959540A CN 112652661 A CN112652661 A CN 112652661A
Authority
CN
China
Prior art keywords
epitaxial
epitaxial layer
metal
layer
front surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910959540.5A
Other languages
Chinese (zh)
Inventor
刘勇强
曾丹
敖利波
薛勇
张祎龙
陈道坤
史波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gree Electric Appliances Inc of Zhuhai
Original Assignee
Gree Electric Appliances Inc of Zhuhai
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gree Electric Appliances Inc of Zhuhai filed Critical Gree Electric Appliances Inc of Zhuhai
Priority to CN201910959540.5A priority Critical patent/CN112652661A/en
Publication of CN112652661A publication Critical patent/CN112652661A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to a transistor and a preparation method thereof, wherein the transistor comprises a metal drain electrode, a substrate, an epitaxial layer and a front structure embedded in the epitaxial layer, wherein the metal drain electrode, the substrate and the epitaxial layer are sequentially attached and connected; a metal interlayer is arranged in the epitaxial layer, and the front structure extends inwards from the front surface of the epitaxial layer to penetrate through the metal interlayer. Through set up the metal intermediate layer in the epitaxial layer, the metal intermediate layer is in the epitaxial layer as impurity atom doping, and the front structure inlays and establishes and pass the metal intermediate layer in the epitaxial layer in addition after, therefore impurity atom can form the recombination center, and the recombination center makes the compound process of the nonequilibrium carrier in the transistor change from traditional direct recombination into indirect recombination, has reduced the recombination time of carrier like this, and then has reduced the reverse recovery time of transistor.

Description

Transistor and preparation method thereof
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a transistor and a preparation method thereof.
Background
A power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a special MOSFET for handling high power levels and is widely applied to switching devices in the Field of voltages less than 600V. The super-junction MOSFET is developed on the power MOSFET, and the breakdown voltage of the MOSFET is greatly improved and the on-resistance of the MOSFET is reduced by adopting a super-junction method. The super-junction MOSFET is generally manufactured by adopting a method of multiple epitaxy and implantation or a process of deep trench digging, but the reverse recovery time of the diode of the existing super-junction MOSFET is too long.
Therefore, it is desirable to provide a transistor and a method for fabricating the same to solve the disadvantages of the prior art.
Disclosure of Invention
The invention provides a transistor and a preparation method thereof, aiming at solving the problem that the reverse recovery time of the transistor in the prior art is too long.
The invention provides a transistor, which comprises a metal drain electrode, a substrate, an epitaxial layer and a front structure, wherein the metal drain electrode, the substrate and the epitaxial layer are sequentially attached and connected, and the front structure is embedded in the epitaxial layer;
a metal interlayer is arranged in the epitaxial layer, and the front structure extends inwards from the front surface of the epitaxial layer to penetrate through the metal interlayer.
Furthermore, the epitaxial layer comprises a plurality of epitaxial layers, the metal interlayers are arranged between every two adjacent epitaxial layers, and the front structure sequentially penetrates through all the metal interlayers; the doping type and the doping concentration of the epitaxial layers are the same.
Furthermore, the epitaxial layer comprises two epitaxial sub-layers, and one metal interlayer is arranged between the two epitaxial sub-layers.
Further, the front structure comprises a plurality of conductive pillars, a plurality of gates and a plurality of sources; the plurality of conducting columns are embedded in the epitaxial layer respectively, the front surface of each conducting column is embedded with one source electrode, the front surface of each conducting column and the front surface of the epitaxial layer are flush, and the front surface of each source electrode, the front surface of each conducting column and the front surface of the epitaxial layer form a first plane; the grid electrodes are respectively arranged on the first plane, and each grid electrode is connected with two source electrodes;
the conduction type of the conduction pillar is different from the doping type of the epitaxial layer.
Furthermore, the plurality of conductive columns are uniformly distributed in the epitaxial layer.
Furthermore, the front structure further comprises a plurality of conduction wells, the conduction wells are arranged around the conduction pillars in a one-to-one correspondence manner, the front surfaces of the conduction wells are flush with the first plane, and the depth of embedding the conduction wells into the epitaxial layer is smaller than the depth of embedding the conduction pillars into the epitaxial layer.
Based on the same inventive concept, the invention provides a transistor preparation method, which comprises the following steps:
preparing a metal interlayer: growing an epitaxial layer on the front surface of the substrate or the front surface of the epitaxial layer, diffusing metal from the front surface of the epitaxial layer to form a metal interlayer embedded in the epitaxial layer, and filling the conductive sub-column from the front surface of the epitaxial layer;
if the number of the metal interlayers meets the preset requirement, performing the following steps of epitaxial layered preparation, otherwise, repeating the steps of preparing the metal interlayers one or more times until the number of the metal interlayers meets the preset requirement, and performing the following steps of epitaxial layered preparation, wherein the steps of epitaxial layered preparation are as follows:
and growing a new epitaxial layer on the front surface of the epitaxial layer, and filling the conductive sub-column from the front surface of the new epitaxial layer.
Further, the diffusing metal from the front side of the epitaxial layer to form a metal interlayer embedded in the epitaxial layer includes:
growing a metal layer on the front surface of the epitaxial lamination by a magnetron sputtering process;
cleaning the metal layer by an acid etching process;
and diffusing the residual metal on the epitaxial lamination into the front surface of the epitaxial lamination through a high-temperature diffusion process to form the metal interlayer.
Further, the packed conductive column includes: etching one or more transmission grooves on the front surface of the epitaxial layering, and filling semiconductor materials into the transmission grooves respectively to form transmission sub-columns;
the conducting grooves etched on the epitaxial layering connected with the substrate penetrate through the metal interlayer, the depth of the conducting grooves is smaller than the thickness of the epitaxial layering, and the conducting grooves etched on other epitaxial layering penetrate through the epitaxial layering;
the arrangement positions of the conduction sub-columns on the multiple epitaxial layers are consistent with each other, the conduction sub-columns at the same position on the multiple epitaxial layers form one conduction column, and the multiple epitaxial layers form an epitaxial layer.
Further, after the step of preparing the epitaxial layers, the method further comprises:
injecting and pushing semiconductor material around each conductive pillar to form a conductive well;
preparing a source electrode and a grid electrode on a first plane formed by the surfaces of the conduction trap, the conduction pillar and the epitaxial layer;
and thinning the back surface of the substrate until the thickness requirement is met, and preparing a metal drain on the back surface of the substrate.
Compared with the closest prior art, the technical scheme of the invention has the following advantages:
according to the transistor provided by the technical scheme, the metal interlayer is arranged in the epitaxial layer, the metal interlayer is doped in the epitaxial layer as an impurity atom, and the front structure is embedded in the epitaxial layer and then penetrates through the metal interlayer, so that the impurity atom can form a recombination center, and the recombination process of an unbalanced carrier in the transistor is changed from traditional direct recombination into indirect recombination by the recombination center, so that the recombination time of the carrier is reduced, and further the reverse recovery time of the transistor is reduced.
Drawings
Fig. 1-10 are state diagrams of steps in a method for fabricating a transistor according to an embodiment of the present invention.
Wherein, 1-a substrate; 2-epitaxial layering; 3-a metal interlayer; 4-a conveying guide groove; 5-a conductive sub-column; 6-conductive well; a 7-source electrode; 8-a grid; 9-metal drain.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In this application, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation.
Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meaning of these terms in this application will be understood by those of ordinary skill in the art as appropriate.
Furthermore, the terms "disposed," "connected," and "secured" are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail with reference to the accompanying examples and figures 1-10. Fig. 1-10 are state diagrams of steps in a method of fabricating a transistor according to the present invention, the transistor in the method of fabricating a transistor shown in fig. 1-10 comprising a metal interlayer; fig. 10 is a state diagram of a completed transistor, that is, a structure diagram of the transistor.
As shown in fig. 10, the present invention provides a Transistor, which may be a Metal-Oxide-Semiconductor Field-Effect Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor), and includes a Metal drain 9, a substrate 1, an epitaxial layer, and a front structure embedded in the epitaxial layer, which are sequentially attached and connected; a metal interlayer 3 is arranged in the epitaxial layer, and the front structure extends inwards from the front surface of the epitaxial layer to penetrate through the metal interlayer 3.
The invention sets a metal interlayer 3 in an epitaxial layer, the metal interlayer 3 is doped in the epitaxial layer as an impurity atom, and the front structure is embedded in the epitaxial layer and then passes through the metal interlayer 3, so that the impurity atom can form a recombination center, the recombination process of the unbalanced carriers in the transistor is changed from the traditional direct recombination to the indirect recombination, thereby reducing the recombination time of the carriers and further reducing the reverse recovery time of the transistor, when the transistor provided by the invention is specifically a super junction MOSFET, the reverse recovery time of the diode of the transistor is greatly shortened; the metal interlayer is preferably a platinum layer and the platinum layer is doped in the epitaxial layer by diffusion and thermal drive.
In some embodiments of the present invention, the epitaxial layer includes a plurality of epitaxial sublayers 2, a metal interlayer 3 is disposed between two adjacent epitaxial sublayers 2, and the front structure sequentially passes through all the metal interlayers 3; the doping type and the doping concentration of the plurality of epitaxial layers 2 are all the same. One or more metal interlayers 3 are arranged in the epitaxial layer, when one metal interlayer 3 is arranged, the epitaxial layer is cut into two epitaxial sublayers 2 by the metal interlayer 3, when a plurality of metal interlayers 3 are arranged, the epitaxial layer is cut into at least three epitaxial sublayers 2 by the plurality of metal interlayers 3, when the plurality of metal interlayers 3 are arranged, the front structure is embedded to a depth which is enough to sequentially penetrate through each metal interlayer 3, the plurality of epitaxial sublayers 2 and the metal interlayers 3 between the epitaxial sublayers 2 grow layer by layer during growth, the plurality of metal interlayers 3 are made of the same metal (for example, platinum), the thickness and the concentration of the plurality of metal interlayers 3 are the same, the doping types of the plurality of epitaxial sublayers 2 are the same (for example, the doping types are both N-type, and the substrate 1 is also an N-type substrate 1), and the doping concentrations are the same.
In some embodiments of the invention, the epitaxial layer comprises two epitaxial sublayers between which a metal interlayer 3 is disposed. The arrangement of the metal interlayer 3 can form a recombination center, reduce the recombination time of carriers, reduce the reverse recovery time of the transistor, avoid excessively increasing the thickness of the transistor, increase the preparation workload compared with the traditional epitaxial layer, and basically achieve the effect of reducing the reverse recovery time of the transistor on the basis of the original cost and efficiency.
In some embodiments of the present invention, the front side structure comprises a plurality of conductive pillars, a plurality of gates 8 and a plurality of sources 7; the plurality of conducting columns are embedded in the epitaxial layer respectively, a source electrode 7 is embedded in the front surface of each conducting column, the front surfaces of the source electrodes 7 and the conducting columns are flush with the front surface of the epitaxial layer, and the front surfaces of the source electrodes 7, the conducting columns and the epitaxial layer form a first plane; a plurality of grid electrodes 8 are respectively arranged on the first plane, and each grid electrode 8 is connected with two source electrodes 7; the conduction type of the conduction pillars is different from the doping type of the epitaxial layer. The conductive pillars are semiconductor material with a certain conductivity type filled in the trenches of the epitaxial layer, and the conductivity type of the conductive pillars is different from that of the epitaxial layer, for example, when the epitaxial layer is semiconductor material with an N-type conductivity type, the conductive pillars are semiconductor material with a P-type conductivity type filled, the structure and arrangement position of the conductive pillars, the structure and arrangement position of the source 7, the structure and arrangement position of the gate 8, and the connection relationship among these mechanisms can all refer to transistors in the prior art, and the above technical contents are known to those skilled in the art, and will not be described herein in detail.
In some embodiments of the present invention, the plurality of conductive pillars are uniformly distributed within the epitaxial layer. The conduction columns are uniformly arranged, so that the on-resistance of the conduction columns can be further reduced, and the breakdown voltage of the conduction columns is improved.
In some embodiments of the present invention, the front structure further includes a plurality of conductive wells 6, the conductive wells 6 are disposed around the conductive pillars in a one-to-one correspondence, a front surface of the conductive well 6 is flush with the first plane, and a depth of embedding the conductive well 6 into the epitaxial layer is smaller than a depth of embedding the conductive pillars into the epitaxial layer. The conductive well 6 is a semiconductor material implanted and driven from the epitaxial layer, which is arranged around the conductive pillar, whose driven well has a depth smaller than that of the conductive pillar, does not contact the metal interlayer 3, and is formed of the same conductive type as the semiconductor material of the conductive pillar.
The transistor according to the above embodiments may further include other necessary components or structures, and the corresponding arrangement positions and connection relationships may refer to the transistors in the prior art, and the connection relationships, operation and operation principles of the structures that are not described in detail are known to those skilled in the art and will not be described in detail herein.
Based on the same inventive concept, the invention provides a transistor preparation method, which comprises the following steps:
s1, as shown in FIGS. 1 to 4, the preparation of the metal interlayer 3 comprises the following steps: growing an epitaxial layer 2 on the front surface of the substrate 1 or the front surface of the epitaxial layer 2 (as shown in fig. 1), diffusing metal from the front surface of the epitaxial layer 2 to form a metal interlayer 3 embedded in the epitaxial layer 2 (as shown in fig. 2), and filling a conductive pillar 5 from the front surface of the epitaxial layer 2 (as shown in fig. 3 and 4);
before the step is carried out, an N + substrate 1 is required to be prepared, the doping concentration of the N + substrate is more than 1e15, the thickness of the N + substrate is more than 500um, and phosphorus is doped in the N + substrate; the epitaxial layer 2 generated in the step grows by a chemical vapor epitaxy process;
in this step, diffusing metal from the front surface of the epitaxial layer 2 to form the metal interlayer 3 embedded in the epitaxial layer 2 specifically includes:
firstly, growing a metal layer with the thickness of 100-200 angstroms on the front surface of the epitaxial layering 2 by a magnetron sputtering process;
then, the metal layer is cleaned by aqua regia and an acid etching process, the metal arranged on the epitaxial layer is removed after cleaning, but some metal (5% -20%) is remained in the epitaxial layer or on the surface, and the remained metal is used as a metal source for subsequent diffusion;
finally, the residual metal on the epitaxial layered layer 2 is diffused into the front surface of the epitaxial layered layer 2 by a high-temperature diffusion process, and since the diffusion speed of the metal (particularly platinum) in silicon (the main component of the epitaxial layer is monocrystalline silicon) is very high, the metal (such as platinum) needs to be removed first and then a metal diffusion process is carried out; at the moment, the diffusion temperature is controlled to be 800-; after the platinum diffusion is completed, the metal interlayer 3 formed in the epitaxial layered layer 2 will introduce a deep recombination center in the epitaxial layered layer 2;
in this step, the packed conductive column 5 specifically includes: etching one or more conductive trenches 4 (shown in fig. 3) in the front surface of the epitaxial layer 2, and filling the conductive trenches 4 with semiconductor material to form conductive pillars 5 (shown in fig. 4); wherein, the conduction groove 4 etched on the epitaxial layered layer 2 connected with the substrate 1 penetrates through the metal interlayer 3 and the depth is less than the thickness of the epitaxial layered layer 2, and the conduction grooves 4 etched on other epitaxial layered layers 2 penetrate through the epitaxial layered layer 2; the arrangement positions of the conduction sub-columns 5 on the multiple epitaxial sub-layers 2 are consistent with each other, the conduction sub-columns 5 at the same positions on the multiple epitaxial sub-layers 2 form a conduction column, and the multiple epitaxial sub-layers 2 form an epitaxial layer; wherein, the operation of etching the conduction groove 4 adopts a dry etching process, and the conduction groove 4 is a preset groove for filling the semiconductor material; the step of filling the semiconductor material to form the conductive sub-column 5 may be specifically to form a P-type conductive sub-column (or simply referred to as P-sub-column) by filling a P-type semiconductor material in the conductive trench 4, and the P-type conductive sub-column and the epitaxial sub-layer are spaced to form a super junction structure.
S2, if the number of the metal interlayers 3 meets the preset requirement, performing the step of preparing the epitaxial delamination 2 as shown in fig. 5 to 7 (which is the case with the preparation method shown in fig. 1 to 10), otherwise, repeating the step of preparing the metal interlayers 3 one or more times until the number of the metal interlayers 3 meets the preset requirement, and performing the step of preparing the epitaxial delamination 2 as shown in fig. 5 to 7, wherein the step of preparing the epitaxial delamination 2 is: a new epitaxial layer 2 is grown on the front side of the epitaxial layer 2 (as shown in fig. 5), and the conductive pillars 5 are filled from the front side of the new epitaxial layer 2 (as shown in fig. 6 and 7).
As shown in fig. 8 to 10, after the step of preparing the epitaxial layer 2, the method further includes: injecting and pushing semiconductor material around each conductive pillar to form a conductive well 6 (as shown in fig. 8); preparing a source electrode 7 and a grid electrode 8 on a first plane composed of the surfaces of the conductive well 6, the conductive pillar and the epitaxial layer (as shown in fig. 9); thinning treatment is carried out from the back of the substrate 1 until the thickness requirement is met, and a metal drain 9 is prepared on the back of the substrate 1 (as shown in fig. 10).
The chemical vapor epitaxy process, the magnetron sputtering process, the acid etching process, the high-temperature diffusion process, the semiconductor material filling process, the semiconductor material injection and drive-in process, and the process for preparing the source electrode 7, the gate electrode 8, and the metal drain electrode 9 mentioned in the method for preparing the transistor according to the above embodiment are all well-established processes commonly used in the art, and can be implemented by those skilled in the art with reference to the prior art, and will not be described in detail herein.
The method for manufacturing a transistor according to the above embodiment may further include other necessary steps, and the implementation manner and sequence of the corresponding steps can be found in the prior art and will not be described in detail herein.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. A transistor is characterized by comprising a metal drain electrode (9), a substrate (1), an epitaxial layer and a front structure embedded in the epitaxial layer, wherein the metal drain electrode, the substrate and the epitaxial layer are sequentially attached and connected;
a metal interlayer (3) is arranged in the epitaxial layer, and the front structure extends inwards from the front surface of the epitaxial layer to penetrate through the metal interlayer (3).
2. The transistor according to claim 1, characterized in that the epitaxial layer comprises a plurality of epitaxial sublayers (2), the metal interlayer (3) is arranged between two adjacent epitaxial sublayers (2), and the front structure sequentially passes through all the metal interlayers (3); the doping type and the doping concentration of the epitaxial layers (2) are the same.
3. Transistor according to claim 2, characterized in that said epitaxial layer comprises two said epitaxial sublayers, between which one said metallic interlayer (3) is provided.
4. Transistor according to claim 1, characterized in that the front side structure comprises a plurality of conductive pillars, a plurality of gates (8) and a plurality of sources (7); the plurality of the conduction columns are embedded in the epitaxial layer respectively, the front surface of each conduction column is embedded with one source electrode (7), the front surfaces of the source electrodes (7), the front surfaces of the conduction columns and the front surface of the epitaxial layer are flush, and the front surfaces of the source electrodes (7), the front surfaces of the conduction columns and the front surface of the epitaxial layer form a first plane; the grid electrodes (8) are respectively arranged on the first plane, and each grid electrode (8) is connected with two source electrodes (7);
the conduction type of the conduction pillar is different from the doping type of the epitaxial layer.
5. The transistor of claim 4, wherein a plurality of said conductive pillars are uniformly distributed within said epitaxial layer.
6. The transistor of claim 4, wherein the front structure further comprises a plurality of conductive wells (6), the plurality of conductive wells (6) are disposed around the conductive pillars in a one-to-one correspondence, a front surface of the conductive wells (6) is flush with the first plane, and a depth of embedding of the conductive wells (6) into the epitaxial layer is smaller than a depth of embedding of the conductive pillars into the epitaxial layer.
7. A transistor preparation method is characterized by comprising the following steps:
preparation of the metal interlayer (3): growing an epitaxial layer (2) on the front surface of the substrate (1) or the front surface of the epitaxial layer (2), diffusing metal from the front surface of the epitaxial layer (2) to form a metal interlayer (3) embedded in the epitaxial layer (2), and filling a conductive pillar (5) from the front surface of the epitaxial layer (2);
if the number of the metal interlayers (3) meets the preset requirement, performing the following step of epitaxial layering (2) preparation, otherwise, repeating the step of metal interlayer (3) preparation one or more times until the number of the metal interlayers (3) meets the preset requirement, and performing the step of epitaxial layering (2) preparation, wherein the step of epitaxial layering (2) preparation is as follows:
growing a new epitaxial layer (2) on the front surface of the epitaxial layer (2), and filling the conductive sub-column (5) from the front surface of the new epitaxial layer (2).
8. Method for preparing a transistor according to claim 7, characterized in that said diffusing metal from the front side of the epitaxial layer (2) to form a metallic interlayer (3) embedded within the epitaxial layer (2) comprises:
growing a metal layer on the front surface of the epitaxial lamination (2) by a magnetron sputtering process;
cleaning the metal layer by an acid etching process;
and diffusing the residual metal on the epitaxial layered layer (2) into the front surface of the epitaxial layered layer (2) by a high-temperature diffusion process to form a metal interlayer (3).
9. The transistor fabrication method according to claim 7, wherein the filling of the conductive pillars (5) comprises: etching one or more transmission grooves (4) on the front surface of the epitaxial layering (2), and filling semiconductor materials into the transmission grooves (4) respectively to form transmission sub-columns (5);
wherein, the transmission guide groove (4) etched on the epitaxial layered layer (2) connected with the substrate (1) penetrates through the metal interlayer (3) and has a depth smaller than the thickness of the epitaxial layered layer (2), and the transmission guide groove (4) etched on other epitaxial layered layers (2) penetrates through the epitaxial layered layer (2);
the arrangement positions of the conduction sub-columns (5) on the epitaxial sub-layers (2) are consistent with each other, the conduction sub-columns (5) at the same position on the epitaxial sub-layers (2) form a conduction column, and the epitaxial sub-layers (2) form an epitaxial layer.
10. Method for the preparation of a transistor according to claim 9, characterized in that said step of preparation of an epitaxial layer (2) is followed by the further step of:
injecting and pushing semiconductor material around each conductive pillar to form a conductive well (6);
preparing a source electrode (7) and a grid electrode (8) on a first plane formed by the surfaces of the conduction trap (6), the conduction pillar and the epitaxial layer;
and thinning the back surface of the substrate (1) to meet the thickness requirement, and preparing a metal drain electrode (9) on the back surface of the substrate (1).
CN201910959540.5A 2019-10-10 2019-10-10 Transistor and preparation method thereof Pending CN112652661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910959540.5A CN112652661A (en) 2019-10-10 2019-10-10 Transistor and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910959540.5A CN112652661A (en) 2019-10-10 2019-10-10 Transistor and preparation method thereof

Publications (1)

Publication Number Publication Date
CN112652661A true CN112652661A (en) 2021-04-13

Family

ID=75343431

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910959540.5A Pending CN112652661A (en) 2019-10-10 2019-10-10 Transistor and preparation method thereof

Country Status (1)

Country Link
CN (1) CN112652661A (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090283799A1 (en) * 2008-05-13 2009-11-19 Infineon Technologies Ag Reduced Free-Charge Carrier Lifetime Device
CN103035676A (en) * 2011-09-28 2013-04-10 丰田自动车株式会社 Semiconductor device and method for manufacturing the same
CN104934465A (en) * 2015-05-12 2015-09-23 电子科技大学 Super junction composition preparation method
CN105122458A (en) * 2013-09-18 2015-12-02 富士电机株式会社 Semiconductor device and manufacturing method therefor
CN106062966A (en) * 2014-09-04 2016-10-26 富士电机株式会社 Semiconductor device and semiconductor device manufacturing method
CN107408576A (en) * 2015-09-16 2017-11-28 富士电机株式会社 The manufacture method of semiconductor device and semiconductor device
US20190074352A1 (en) * 2007-08-02 2019-03-07 Infineon Technologies Austria Ag Method for Producing a Semiconductor Body Having a Recombination Zone, Semiconductor Component Having a Recombination Zone, and Method for Producing such a Semiconductor Component
CN109994383A (en) * 2017-12-18 2019-07-09 英飞凌科技股份有限公司 Semiconductor devices and the method for being used to form semiconductor devices

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190074352A1 (en) * 2007-08-02 2019-03-07 Infineon Technologies Austria Ag Method for Producing a Semiconductor Body Having a Recombination Zone, Semiconductor Component Having a Recombination Zone, and Method for Producing such a Semiconductor Component
US20090283799A1 (en) * 2008-05-13 2009-11-19 Infineon Technologies Ag Reduced Free-Charge Carrier Lifetime Device
CN103035676A (en) * 2011-09-28 2013-04-10 丰田自动车株式会社 Semiconductor device and method for manufacturing the same
CN105122458A (en) * 2013-09-18 2015-12-02 富士电机株式会社 Semiconductor device and manufacturing method therefor
CN106062966A (en) * 2014-09-04 2016-10-26 富士电机株式会社 Semiconductor device and semiconductor device manufacturing method
CN104934465A (en) * 2015-05-12 2015-09-23 电子科技大学 Super junction composition preparation method
CN107408576A (en) * 2015-09-16 2017-11-28 富士电机株式会社 The manufacture method of semiconductor device and semiconductor device
CN109994383A (en) * 2017-12-18 2019-07-09 英飞凌科技股份有限公司 Semiconductor devices and the method for being used to form semiconductor devices

Similar Documents

Publication Publication Date Title
CN102804386B (en) Semiconductor device
US8129783B2 (en) Lateral power MOSFET with high breakdown voltage and low on-resistance
US9455345B2 (en) Method and apparatus for power device with depletion structure
TWI588990B (en) Semiconductor device including superjunction structure formed suing angled implant process
CN102947928B (en) Semiconductor device and method for manufacturing same
US20060006458A1 (en) Semiconductor device and method for manufacturing the same
JP6864288B2 (en) Semiconductor devices and methods for manufacturing semiconductor devices
CN107316899B (en) Semi-super junction device and manufacturing method thereof
CN102479805A (en) Super junction semiconductor element and manufacture method thereof
WO2011033550A1 (en) Semiconductor device
CN105185825A (en) Injection Control In Semiconductor Power Devices
CN104637821B (en) The manufacturing method of super-junction device
JP2008053397A (en) Semiconductor device, and its manufacturing method
CN109755322B (en) Silicon carbide MOSFET device and preparation method thereof
CN102354685A (en) Integrated circuit including power diode
CN105914231B (en) Charge storage type IGBT and its manufacturing method
CN108074963B (en) Super junction device and manufacturing method thereof
CN109713029A (en) A kind of multiple extension superjunction devices production method improving reverse recovery characteristic
JP6766522B2 (en) Semiconductor devices and methods for manufacturing semiconductor devices
CN110212026A (en) Superjunction MOS device structure and preparation method thereof
CN112652661A (en) Transistor and preparation method thereof
CN102214561A (en) Super-junction semiconductor device and manufacturing method thereof
CN210607276U (en) Groove type power device based on Schottky structure
CN104979214B (en) A kind of preparation method of super-junction structure
JP6092680B2 (en) Semiconductor device and manufacturing method of semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20210413

RJ01 Rejection of invention patent application after publication