CN112636700A - Signal processing equipment and interference reduction charge amplifier thereof - Google Patents

Signal processing equipment and interference reduction charge amplifier thereof Download PDF

Info

Publication number
CN112636700A
CN112636700A CN202110013731.XA CN202110013731A CN112636700A CN 112636700 A CN112636700 A CN 112636700A CN 202110013731 A CN202110013731 A CN 202110013731A CN 112636700 A CN112636700 A CN 112636700A
Authority
CN
China
Prior art keywords
resistor
capacitor
circuit
input
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110013731.XA
Other languages
Chinese (zh)
Inventor
唐德尧
曾娅娟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tangzhi Science & Technology Hunan Development Co ltd
Original Assignee
Tangzhi Science & Technology Hunan Development Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tangzhi Science & Technology Hunan Development Co ltd filed Critical Tangzhi Science & Technology Hunan Development Co ltd
Priority to CN202110013731.XA priority Critical patent/CN112636700A/en
Publication of CN112636700A publication Critical patent/CN112636700A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/70—Charge amplifiers

Abstract

The application discloses reduce charge amplifier of interference includes: the first input end of the positive charge converter is connected with the preceding stage circuit and the first end of the second resistor, and the second input end of the positive charge converter is used as a reference end and is connected with the second input end of the negative charge converter; the first input end of the negative charge converter is connected with the preceding stage circuit and the second end of the first resistor; the differential superposition circuit is connected with the positive and negative charge converters and the reference end; the first end of the third resistor is connected with the output end of the positive charge converter, and the second end of the third resistor is connected with the first end of the fourth resistor; the second end of the fourth resistor is connected with the output end of the negative charge converter; the first end of the first resistor is connected with the second end of the second resistor; a second resistor; the connecting ends of the first resistor and the second resistor are connected with the connecting ends of the third resistor and the fourth resistor. By applying the scheme of the application, the common-mode interference can be effectively reduced, and the method is simple and easy to implement. The application also provides a signal processing device with corresponding effect.

Description

Signal processing equipment and interference reduction charge amplifier thereof
Technical Field
The present invention relates to the field of circuit technologies, and in particular, to a signal processing device and a charge amplifier for reducing interference.
Background
The charge amplifier is subject to interference during use. Especially for piezoelectric sensitive devices such as piezoelectric ceramics, when the piezoelectric sensitive devices are independently arranged at the far end of a charge amplifier, common mode interference in the environment is extremely easy to enter the charge amplifier at the later stage through distributed capacitances CZ1 and CZ2 between a cable connecting the piezoelectric sensitive devices and an interference electric field. The interference signal may directly make the charge amplifier output amplitude limiting, and when the piezoelectric sensitive device outputs the charge signal, the superposed interference signal is more likely to make the charge amplifier amplitude limiting.
The existing common solution is to reduce the electric field interference entering the input end of the transmission cable of the piezoelectric sensing device by shielding grounding, improving the insulation resistance of the input end of the piezoelectric sensing device to the interference source, and the like, but because the electric field interference is mainly through the coupling of distributed capacitance, the distributed capacitance cannot be eliminated, the electric field interference in the environment still inevitably enters the charge amplifier through the distributed capacitance of the interference source to the piezoelectric sensing device, and the classical methods of shielding grounding, filtering, and the like cannot reduce the common-mode interference entering the circuit, thereby causing the output amplitude limit of the charge amplifier, and causing the circuit to be interfered and unable to be normally used in severe cases. There are also solutions where high precision electronic components are used, but such costs are too high.
In summary, how to effectively reduce the common mode interference, and the method is simple and easy to implement, is a technical problem that needs to be solved urgently by those skilled in the art.
Disclosure of Invention
The invention aims to provide a signal processing device and an interference reduction charge amplifier thereof, so as to effectively reduce common-mode interference and be simple and easy to implement.
In order to solve the technical problems, the invention provides the following technical scheme:
a glitch reducing charge amplifier, comprising:
the first input end is respectively connected with the preceding stage circuit and the first end of the second resistor, the second input end is used as a reference end and is connected with the second input end of the negative charge converter, and the positive charge converter is used for converting an input charge signal into a voltage signal and amplifying and outputting the voltage signal;
the first input end is respectively connected with the preceding stage circuit and the second end of the first resistor, and the negative charge converter is used for converting the input charge signal into a voltage signal and amplifying and outputting the voltage signal;
the first input end is connected with the output end of the positive charge converter, the second input end is connected with the output end of the negative charge converter, and the third input end is connected with the reference end, so that the differential superposition circuit is used for summing differential voltages;
a third resistor having a first terminal connected to the output terminal of the positive charge converter and a second terminal connected to the first terminal of the fourth resistor; the fourth resistor with a second end connected with the output end of the negative charge converter; the first resistor is connected with the second end of the second resistor at a first end; the second resistor; and a connection end of the first resistor and the second resistor is used as a first target end, a connection end of the third resistor and the fourth resistor is used as a second target end, and the first target end is connected with the second target end.
Preferably, the method further comprises the following steps:
a proportional amplifying circuit disposed between the first target terminal and the second target terminal.
Preferably, the scale amplifying circuit includes:
the same-direction input end is connected with the second target end, the reverse-phase input end is respectively connected with the first end of a fifth resistor and the first end of a sixth resistor, and the output end is respectively connected with the second end of the sixth resistor and the first target end;
the fifth resistor with a second end connected with the reference end;
the sixth resistor.
Preferably, the positive charge converter includes:
the non-inverting input end is used as a second input end of the positive charge converter, the inverting input end is used as a first input end of the positive charge converter and is simultaneously connected with the preceding-stage circuit, a first end of the second resistor, a first end of the fourth capacitor and a first end of the eighth resistor, and the output end is used as a second operational amplifier of the output end of the positive charge converter;
the second end of the fourth capacitor is connected with the output end of the second operational amplifier and the second end of the ninth resistor respectively;
the second end of the eighth resistor is connected with the first end of the ninth resistor;
the ninth resistor;
the negative charge converter includes:
the non-inverting input end is used as a second input end of the negative charge converter, the inverting input end is used as a first input end of the negative charge converter and is simultaneously connected with the preceding-stage circuit, a second end of the first resistor, a first end of the sixth capacitor and a first end of the eleventh resistor, and the output end is used as a third operational amplifier of the output end of the negative charge converter;
the sixth capacitor with a second end connected with the output end of the third operational amplifier and the second end of the twelfth resistor respectively;
an eleventh resistor having a second end connected to the first end of the twelfth resistor;
the twelfth resistor.
Preferably, the method further comprises the following steps:
a second RC circuit disposed between the preceding stage circuit and the first input terminal of the positive charge converter;
a third RC circuit disposed between the pre-stage circuit and the first input terminal of the negative charge converter;
and, the second RC circuit includes a third capacitor and a seventh resistor, the third RC circuit includes a fifth capacitor and a tenth resistor:
a first end of the third capacitor is used as a first end of the second RC circuit and is connected with the preceding stage circuit and a first end of the second resistor, a second end of the third capacitor is connected with a first end of the seventh resistor, and a second end of the seventh resistor is used as a second end of the second RC circuit and is connected with a first input end of the positive charge converter;
a first end of the fifth capacitor is used as a first end of the third RC circuit and is connected with the preceding stage circuit and a second end of the first resistor, a second end of the fifth capacitor is connected with a first end of the tenth resistor, and a second end of the tenth resistor is used as a second end of the third RC circuit and is connected with a first input end of the negative charge converter.
Preferably, the method further comprises the following steps: a first capacitor and a second capacitor;
the second end of the second capacitor is respectively connected with the first end of the first capacitor and the first target end;
when the first end of the second capacitor is connected with the first end of the second resistor, the second end of the first capacitor is connected with the second end of the first resistor;
when the first end of the second capacitor is connected with the second end of the third capacitor, the second end of the first capacitor is connected with the second end of the fifth capacitor;
when the first end of the second capacitor is connected with the second end of the seventh resistor, the second end of the first capacitor is connected with the second end of the tenth resistor.
Preferably, the resistance value selection range of the first resistor and the resistance value selection range of the second resistor are both output according to a common mode output voltage UCDetermining a resistance value selection range according to a rule smaller than a preset threshold value;
wherein the content of the first and second substances,
Figure BDA0002885955460000041
Uiinterference voltage, R, for an external ambient electric fieldC，Rf1And RCZAre all intermediate parameters, and RC＝R1＝R2，Rf1＝R3＝R4，RCZ＝RCZ1＝RCZ2，R1，R2，R3，R4Sequentially expressing the resistance value of the first resistor, the resistance value of the second resistor, the resistance value of the third resistor and the resistance value of the fourth resistor; rCZ1And RCZ2Respectively representing the coupling capacitance of Ui to the positive charge input end of the charge signal source of the charge amplifier and the coupling capacitance of Ui to the negative charge input end of the charge signal source of the charge amplifier; rC3Representing the impedance generated by the third capacitor，R7Representing the resistance of the seventh resistor.
Preferably, the method further comprises the following steps:
a first RC circuit connected to both the positive charge converter and the negative charge converter;
and, the first RC circuit includes:
the first end of the thirteenth resistor is connected with the second end of the eighth resistor, and the second end of the thirteenth resistor is connected with the first end of the seventh capacitor;
the seventh capacitor with a second end connected with the second end of the eleventh resistor;
and the resistance value of the thirteenth resistor is according to
Figure BDA0002885955460000042
Determining the resistance value;
wherein the intermediate parameter
Figure BDA0002885955460000043
fLRepresenting the target cut-off frequency, C3Representing the capacitance value, R, of the third capacitor8And C7Respectively representing the resistance value of the eighth resistor, the capacitance value of the seventh capacitor and an intermediate parameter Cf＝C3＝C4，C3And C4Respectively representing the capacitance value of the third capacitor and the capacitance value of the fourth capacitor, and an intermediate parameter.
Preferably, the differential superimposing circuit includes:
the first end of the fourth resistor is used as the first input end of the differential superposition circuit, and the second end of the fourth resistor is connected with the second end of the fifth resistor and the non-inverting input end of the fourth operational amplifier;
the fifteenth resistor with a first end serving as a third input end of the differential superposition circuit;
the first end of the differential superposition circuit is used as a second input end of the differential superposition circuit, and the second end of the differential superposition circuit is respectively connected with the first end of a seventeenth resistor and the inverted input end of the fourth operational amplifier;
the output end of the fourth operational amplifier is used as the output end of the differential superposition circuit and is connected with the second end of the seventeenth resistor;
the seventeenth resistor.
A signal processing apparatus comprising the interference reducing charge amplifier of any one of the above.
By applying the technical scheme provided by the embodiment of the invention, considering that the common-mode input range of the charge amplifier is limited, although the circuit with the differential amplification function formed by the positive charge converter, the negative charge converter and the differential superposition circuit can eliminate common-mode interference, when the common-mode interference entering the charge amplifier exceeds the common-mode input range of the positive charge converter and the negative charge converter, harmful differential-mode signals can be generated at the differential output end, namely the output end of the differential superposition circuit. Therefore, the purpose of the present application is to reduce the interference of the common mode input, and the specific scheme can be realized by a negative feedback circuit formed by the first resistor, the second resistor, the third resistor and the fourth resistor. This application scheme has increased the common mode negative feedback resistance of charge amplifier output to input, has specifically set up respectively with the third resistance and the fourth resistance that positive charge converter output and negative charge converter output are connected promptly, the first end of second resistance then with the first input end of positive charge converter be connected, the second end of second resistance is connected with the first end of first resistance, the second end of first resistance then is connected with the first input of negative charge converter. And the common end of the third resistor and the fourth resistor is connected with the common end of the first resistor and the second resistor, thereby forming a negative feedback circuit. The common-mode input voltage can not exceed the common-mode input range of the positive charge converter and the negative charge converter, the common-mode voltage output by the positive charge converter and the negative charge converter is reduced, the differential superposition circuit can effectively eliminate common-mode interference through differential output, and the scheme of the application can effectively reduce the finally output common-mode interference signal. In addition, the negative feedback circuit formed by the first resistor, the second resistor, the third resistor and the fourth resistor can be used for realizing the negative feedback circuit, the structure is simple, the cost is low, and the implementation is easy. In summary, the scheme of the application can effectively reduce common-mode interference, and is simple and easy to implement.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of an interference reducing charge amplifier according to the present invention;
FIG. 2 is a schematic diagram of a first configuration of a glitch reduction charge amplifier in accordance with one embodiment of the present invention;
FIG. 3 is a second schematic diagram of a glitch reduction charge amplifier in accordance with one embodiment of the present invention;
FIG. 4 is a schematic diagram of a third configuration of a glitch reduction charge amplifier in accordance with an embodiment of the present invention;
FIG. 5 is a schematic diagram of the frequency response of the three schemes of FIGS. 2, 3 and 4 in one embodiment;
FIG. 6a is a schematic diagram showing signal waveforms at various detection positions of a conventional negative feedback circuit without the present application when the charge input terminal leaks to ground;
FIG. 6b is a schematic diagram of signal waveforms at various detection positions of the embodiment of FIG. 2 according to the present application when the charge input terminal leaks electricity to ground;
FIG. 6c is a schematic diagram of signal waveforms at various detection positions of the embodiment of FIG. 4 according to the present application when the charge input terminal leaks electricity to ground;
FIG. 7a is a waveform diagram illustrating various detection positions of a conventional charge amplifier when common mode interference exists;
FIG. 7b is a schematic diagram showing waveforms of various detection positions to which the present solution is applied when common mode interference exists;
FIG. 8a is a diagram illustrating a fourth configuration of a disturbance reduction charge amplifier according to an embodiment of the present invention;
fig. 8b is a schematic diagram of a fifth configuration of a disturbance reduction charge amplifier according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide a charge amplifier with reduced interference, which can effectively reduce the common-mode interference of output.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic diagram of a structure of a disturbance reduction charge amplifier according to the present invention, the disturbance reduction charge amplifier may include:
a positive charge converter 10 having a first input terminal connected to the previous stage circuit and a first terminal of the second resistor R2, and a second input terminal serving as a reference terminal and connected to a second input terminal of the negative charge converter 20, for converting an input charge signal into a voltage signal and amplifying the voltage signal;
a negative charge converter 20 having a first input terminal connected to the previous stage circuit and a second terminal of the first resistor R1, for converting an input charge signal into a voltage signal and amplifying the voltage signal;
a differential superposition circuit 30, a first input end of which is connected with the output end of the positive charge converter 10, a second input end of which is connected with the output end of the negative charge converter 20, and a third input end of which is connected with a reference end, for carrying out differential voltage summation;
a third resistor R3 having a first terminal connected to the output terminal of the positive charge converter 10 and a second terminal connected to a first terminal of a fourth resistor R4; a fourth resistor R4 having a second terminal connected to the output terminal of the negative charge converter 20; a first resistor R1 having a first end connected to a second end of the second resistor R2; and a second resistor R2.
The connection end of the first resistor R1 and the second resistor R2 serves as a first target end, the connection end of the third resistor R3 and the fourth resistor R4 serves as a second target end, and the first target end and the second target end are connected.
Specifically, the front stage circuit is usually a piezoelectric sensitive device, such as a piezoelectric sensitive device like piezoelectric ceramics, and the specific circuit structure can be selected according to actual needs.
The output of differential voltage can be realized through the positive charge converter 10 and the negative charge converter 20, then the differential voltage summation is carried out through the differential superposition circuit 30, the specific circuit structures of the positive charge converter 10, the negative charge converter 20 and the differential superposition circuit 30 can also be set and adjusted according to actual needs, and the functions of the application can be realized.
For example, in one embodiment of the present invention, referring to fig. 2, positive charge transformer 10 includes:
a second operational amplifier OP2, wherein the non-inverting input terminal is used as a second input terminal of the positive charge converter 10, the inverting input terminal is used as a first input terminal of the positive charge converter 10 and is connected with a first terminal of a simultaneous preceding stage circuit, a first terminal of a second resistor R2, a first terminal of a fourth capacitor C4 and a first terminal of an eighth resistor R8, and the output terminal is used as an output terminal of the positive charge converter 10;
a fourth capacitor C4 having a second terminal connected to the output terminal of the second OP2 and the second terminal of the ninth resistor R9, respectively;
an eighth resistor R8 having a second end connected to the first end of the ninth resistor R9;
a ninth resistor R9.
In the embodiment of fig. 2, the positive charge converter 10 is composed of a second OP2, a fourth capacitor C4, an eighth resistor R8, and a ninth resistor R9.
The structure of the negative charge transformer 20 is generally the same as the positive charge transformer 10, for example in the embodiment of fig. 2, the negative charge transformer 20 may include:
a non-inverting input terminal as a second input terminal of the negative charge converter 20, an inverting input terminal as a first input terminal of the negative charge converter 20 and connected to a preceding stage circuit, a second terminal of the first resistor R1, a first terminal of the sixth capacitor C6 and a first terminal of the eleventh resistor R11, and an output terminal as a third operational amplifier OP3 of the output terminal of the negative charge converter 20;
a sixth capacitor C6 having a second terminal connected to the output terminal of the third OP3 and the second terminal of the twelfth resistor R12, respectively;
an eleventh resistor R11 having a second end connected to the first end of the twelfth resistor R12;
a twelfth resistor R12.
In the embodiment of fig. 2, the negative charge converter 20 is composed of a sixth capacitor C6, a second operational amplifier OP2, an eleventh resistor R11 and a twelfth resistor R12, and has a structure identical to that of the positive charge converter 10. In the embodiment of fig. 2, the positive charge converter 10 and the negative charge converter 20 have a simpler structure, which facilitates implementation of the scheme.
Further, in practical applications, the method generally further includes:
a second RC circuit provided between the preceding stage circuit and the first input terminal of the positive charge converter 10;
and a third RC circuit disposed between the preceding stage circuit and the first input terminal of the negative charge converter 20.
For example, in an embodiment of the present invention, referring to fig. 2, the second RC circuit includes a third capacitor C3 and a seventh resistor R7, the third RC circuit includes a fifth capacitor C5 and a tenth resistor R10:
a first end of a third capacitor C3 is used as a first end of the second RC circuit and is connected with a previous stage circuit and a first end of a second resistor R2, a second end of a third capacitor C3 is connected with a first end of a seventh resistor R7, and a second end of the seventh resistor R7 is used as a second end of the second RC circuit and is connected with a first input end of the positive charge converter 10;
a first terminal of the fifth capacitor C5 serves as a first terminal of the third RC circuit and is connected to the previous stage circuit and the second terminal of the first resistor R1, a second terminal of the fifth capacitor C5 is connected to a first terminal of the tenth resistor R10, and a second terminal of the tenth resistor R10 serves as a second terminal of the third RC circuit and is connected to the first input terminal of the negative charge converter 20.
In the embodiment shown in fig. 2, the second RC circuit and the third RC circuit are implemented by the third capacitor C3, the seventh resistor R7, the fifth capacitor C5 and the tenth resistor R10, which is simple and convenient.
In fig. 2, Z + denotes the positive charge input of the inventive interference-reducing charge amplifier, and Z-denotes the negative charge input of the inventive interference-reducing charge amplifier. In addition, the positive and negative charge transducers are generally symmetrical in parameters, except that they are structurally identical. In particular, there is C3＝C5，R7＝R10，R8＝R9＝R11＝R12，C4＝C6。
The non-inverting input terminals of the second operational amplifier OP2 and the third operational amplifier OP3 are both connected to a reference terminal, Vref is used in the drawings of the application to represent the reference terminal, and the specific voltage value of the reference terminal can be set according to actual needs.
In the embodiment of fig. 2, the positive charge converter 10 and the negative charge converter 20 have a simpler structure, which facilitates implementation of the scheme.
The differential superposition circuit 30 is used for summing differential voltages, and the specific circuit structure is various, for example, in the embodiment of fig. 2, the differential superposition circuit 30 includes:
a fourteenth resistor R14 having a first end serving as a first input end of the differential superposition circuit 30 and a second end connected to the second end of the fifteenth resistor R15 and a non-inverting input end of the fourth OP4, respectively;
a fifteenth resistor R15 having a first terminal serving as a third input terminal of the differential superimposing circuit 30;
a sixteenth resistor R16 having a first end serving as a second input end of the differential superposition circuit 30 and a second end connected to the first end of the seventeenth resistor R17 and the inverting input end of the fourth operational amplifier OP4, respectively;
a fourth OP4 having an output terminal serving as an output terminal of the differential superposition circuit 30 and connected to a second terminal of the seventeenth resistor R17;
a seventeenth resistor R17.
The differential superposition circuit 30 in this embodiment is composed of four resistors and one operational amplifier, the circuit structure is convenient to implement, and the output end of the fourth operational amplifier OP4 is used as the output end of the differential superposition circuit 30, namely, the differential charge conversion signal is output through the output end of the fourth operational amplifier OP 4. In addition, R is usually set to14＝R16，R15＝R17。
In an embodiment of the present invention, the method may further include:
a first RC circuit connected to both the positive charge transformer 10 and the negative charge transformer 20.
The first RC circuit, which may also be referred to as a differential bypass branch, is connected to both positive charge converter 10 and negative charge converter 20 to improve the bandwidth of the frequency response. In the embodiment of fig. 2, the thirteenth resistor R13 and the seventh capacitor C7 form a first RC circuit, which is simple and easy to implement. Namely, the first RC circuit in fig. 2 includes: a thirteenth resistor R13 having a first terminal connected to the second terminal of the eighth resistor R8 and a second terminal connected to the first terminal of the seventh capacitor C7; and a seventh capacitor C7 having a second terminal connected to a second terminal of the eleventh resistor R11.
The bandwidth of the enhanced frequency response is illustrated as follows: for example, set R8＝R9＝R11＝R12And R is8+R9＝R11+R12＝Rf，C4＝C6＝Cf. Then if the first RC circuit is not provided, the low frequency breakover frequency f is the low frequency breakover frequency for a single ended charge amplifier0＝1/(2πRfCf) For a single-ended charge amplifier, there is a low frequency transition frequency for the first RC circuit
Figure BDA0002885955460000101
It can be seen that f0' lower than f0It is explained that the first RC circuit can improve the low frequency characteristic. For the differential charge amplifier of the present application, the resistance of the thirteenth resistor R13 in the first RC circuit is increased based on the aboveTo 2 times, the capacitance of the seventh capacitor C7 is reduced by half, i.e. the low frequency transition frequency
Figure BDA0002885955460000102
I.e. 2 times the effect.
In the embodiment shown in fig. 1 and 2 of the present application, the negative feedback circuit required by the present application can be formed by the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4, so as to reduce interference entering the charge amplifier.
Specifically, a first terminal of the third resistor R3 is connected to the output terminal of the positive charge converter 10, and in the specific circuit configuration of fig. 2, the first terminal is connected to the output terminal of the second operational amplifier OP2, and correspondingly, a second terminal of the fourth resistor R4 is connected to the output terminal of the negative charge converter 20, and in the specific circuit configuration of fig. 2, the second terminal is connected to the output terminal of the third operational amplifier OP3, and the second terminal of the third resistor R3 is connected to the first terminal of the fourth resistor R4, for convenience of description, the connection terminal of the third resistor R3 and the fourth resistor R4 is referred to as a second target terminal.
A first terminal of the second resistor R2 is connected to the positive charge input, i.e. can be connected to the first input of the positive charge transformer 10, and a second terminal of the first resistor R1 is connected to the negative charge input, i.e. can be connected to the first input of the negative charge transformer 20. Furthermore, as described above, a second RC circuit is usually disposed between the previous stage circuit and the first input terminal of the positive charge converter 10, and a third RC circuit is disposed between the previous stage circuit and the first input terminal of the negative charge converter 20. Therefore, in the circuit structure of this specific example in fig. 2, the first terminal of the second resistor R2 is connected to the first terminal of the third capacitor C3. Correspondingly, the second terminal of the first resistor R1 is connected to the first terminal of the fifth capacitor C5. The first terminal of the first resistor R1 is connected to the second terminal of the second resistor R2, which is referred to herein as the first target terminal.
In general, R may be set3＝R4，R1＝R2By connecting the first target terminal and the second target terminal, a negative feedback path for positive and negative charge conversion can be formed, and the embodiment is applied to the original charge amplifier pairThe transmission coefficient of the normal piezoelectric signal is not affected. In both fig. 1 and 2, the first target is shown as being connected to the second target by two J1.
The common mode interference voltage of the output of the charge amplifier refers to the voltage of the output of the positive charge transformer 10 and the voltage of the output of the negative charge transformer 20 relative to the reference terminal Vref, i.e., the voltage of the reference terminal relative to the position marked by 4 in fig. 2.
When the interference voltage Ui of the external environment electric field has C to the coupling capacitance of the input end Z + and Z-of the charge signal source of the charge amplifierZ1、CZ2And C isZ1＝CZ2When, for example, CZ1And CZ2Are all represented as CZI.e. CZ＝CZ1＝CZ2If the negative feedback circuit for suppressing common mode interference of the present application is not provided, the common mode interference voltage U output from the charge amplifierC0Specifically, it can be expressed as:
UC0＝Ui×Cf/(RCZ+RC3+R7)
wherein R isC3Impedance, R, generated for the third capacitor C3CZIs a coupling capacitor CZ1、CZ2The resulting impedance, f, is the frequency of the common mode interference signal. CfAs described above, the capacitance values of the fourth capacitor C4 and the sixth capacitor C6, i.e., Cf＝C4＝C6。
In the scheme of fig. 2 of the present application, the common-mode interference voltage U output by the charge amplifierCSpecifically, it can be expressed as:
Figure BDA0002885955460000111
wherein R isf1The values of the third resistor R3 and the fourth resistor R4, namely R3＝R4＝Rf1，RCThe values of the first resistor R1 and the second resistor R2 are shown, R1＝R2＝RC。
It should be noted that the above formula is directed to the specific embodiment of fig. 2, and in other embodiments, the purpose of reducing common mode interference can still be achieved by applying the negative feedback circuit formed by the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 of the present application, but the structures of the positive charge converter 10 and the negative charge converter 20 are different, and the common mode output voltage U is differentCNaturally, the expression formula of (1) is different because the positive charge transformer 10 and the negative charge transformer 20 have different specific structures.
Further, in an embodiment of the present invention, referring to fig. 3, the method may further include:
and the proportional amplifying circuit is arranged between the first target end and the second target end.
By arranging the proportional amplifying circuit between the first target end and the second target end, negative feedback can be amplified, common mode interference can be further reduced, and meanwhile, the low-frequency rejection frequency band is widened.
The specific circuit configuration of the scaling circuit may also be selected according to actual needs, for example, in the embodiment of fig. 3, the scaling circuit includes:
the first operational amplifier OP1 is characterized in that the equidirectional input end is connected with the second target end, the inverted input end is respectively connected with the first end of the fifth resistor R5 and the first end of the sixth resistor R6, and the output end is respectively connected with the second end of the sixth resistor R6 and the first target end;
a fifth resistor R5 having a second terminal connected to the reference terminal;
a sixth resistor R6.
In fig. 3, the proportional amplifier circuit is composed of the first operational amplifier OP1, the fifth resistor R5 and the sixth resistor R6, and compared with fig. 2, the negative feedback of the voltage is increased, which is beneficial to further reducing the common mode interference and widening the low-frequency rejection band. The circuit configuration of the proportional amplifier circuit in fig. 3 is also simple and highly reliable.
Further, in an embodiment of the present invention, the method may further include: a first capacitor C1 and a second capacitor C2;
a second end of the second capacitor C2 is connected to a first end of the first capacitor C1 and a first target end, respectively;
when the first end of the second capacitor C2 is connected with the first end of the second resistor R2, the second end of the first capacitor C1 is connected with the second end of the first resistor R1;
when the first terminal of the second capacitor C2 is connected with the second terminal of the third capacitor C3, the second terminal of the first capacitor C1 is connected with the second terminal of the fifth capacitor C5;
when the first terminal of the second capacitor C2 is connected to the second terminal of the seventh resistor R7, the second terminal of the first capacitor C1 is connected to the second terminal of the tenth resistor R10.
In this embodiment, the embodiments of fig. 2 and 3 are considered, and the common mode interference suppression capability for the low frequency band is strong, and on this basis, the common mode interference of the high frequency band is further reduced by adding the negative feedback of the capacitor. Furthermore, the capacitance value of the first capacitor C1 needs to be generally equal to the capacitance value of the second capacitor C2.
In this embodiment, referring to fig. 4 and fig. 8a and 8b, respectively, since the connection modes are consistent in principle, the present application will be described with reference to the embodiment of fig. 4, that is, the first terminal of the second capacitor C2 is connected to the first terminal of the second resistor R2, and the second terminal of the first capacitor C1 is connected to the second terminal of the first resistor R1.
The frequency response of the three schemes of fig. 2, 3 and 4 can be seen in fig. 5, which reflects the ability of the three schemes to suppress common mode interference, wherein curve 1 in fig. 5 inputs common mode, and shows the frequency response without the negative feedback circuit. The resistive degeneration of curve 2 outputs the common mode, representing the frequency response of the scheme of figure 2. The double resistance degeneration of curve 3 outputs the common mode, representing the frequency response of the scheme of figure 3. The resistor + capacitor degeneration of curve 4 outputs the common mode, representing the frequency response of the scheme of figure 4. It can be seen that the arrangement of figure 4 has an effect in the high frequency band which is better than that of figures 2 and 3.
It should be noted that the common mode interference is generated by distributed capacitive coupling, but the present application also has a suppression effect when the charge input terminal or the capacitive device leaks to cause dc common mode interference.
Specifically, referring to fig. 6a, fig. 6b, fig. 6c, and fig. 6a are schematic signal waveforms of each detection position of the conventional negative feedback circuit without the present application when the charge input terminal leaks electricity to the ground, and curves in each coordinate axis from top to bottom sequentially show: 1-output voltage of the positive charge converter. 2-the output voltage of the negative charge converter. 3-differential output voltage, i.e. the voltage of the output of the differential superposition circuit with respect to the reference terminal. 4-output common mode voltage. 5-input common mode voltage. 6-interference source. 7-signal source.
Fig. 6b is a schematic diagram of signal waveforms of each detection position in the embodiment of fig. 2 when the charge input terminal leaks electricity to the ground, and curves of each coordinate axis from top to bottom sequentially show: the output voltage of the 1-positive charge converter, i.e. the voltage at position 1 marked in fig. 2 with respect to the reference terminal. The output voltage of the 2-negative charge converter, i.e. the voltage at position 2 marked in fig. 2 with respect to the reference terminal. 3-differential output voltage, i.e. the voltage at position 3 marked in fig. 2 with respect to the reference terminal. 4-output common mode voltage, i.e. the voltage at position 4 marked in fig. 2 with respect to the reference terminal. 5-input common mode voltage, i.e. the voltage at position 5 marked in fig. 2 with respect to the reference terminal. 6-interference source. 7-signal source.
Fig. 6c is a schematic diagram of signal waveforms of each detection position in the embodiment of fig. 4 when the charge input terminal leaks to the ground, and curves of each coordinate axis from top to bottom sequentially show: the output voltage of the 1-positive charge converter, i.e. the voltage at position 1 marked in fig. 4 with respect to the reference terminal. The output voltage of the 2-negative charge converter, i.e. the voltage at position 2 marked in fig. 4 with respect to the reference terminal. 3-differential output voltage, i.e. the voltage at position 3 marked in fig. 4 with respect to the reference terminal. 4-output common mode voltage, i.e. the voltage at position 4 marked in fig. 4 with respect to the reference terminal. 5-input common mode voltage, i.e. the voltage at position 5 marked in fig. 4 with respect to the reference terminal. 6-interference source. 7-signal source.
It can be seen that the present application also has a suppression effect due to dc common mode interference caused by the leakage condition.
Furthermore, it should be noted that, for the schemes of fig. 2 to 4, the common-mode output voltage can be expressed as:
Figure BDA0002885955460000141
it can be understood that UCThe smaller the size, the better the suppression of common mode interference, and in practical applications, the U is usually limitedCIs smaller than the set threshold. Therefore, the present application sets the resistance values of the first resistor R1 and the second resistor R2, i.e., for Rf1Is set so that U is not requiredCThis definition can be satisfied.
That is, the selection range of the resistance of the first resistor R1 and the selection range of the resistance of the second resistor R2 can be both according to the common mode output voltage UCAnd determining the resistance value selection range according to the rule that the resistance value is less than or equal to the preset threshold value. Certainly, after the resistance value selection range of the first resistor R1 and the resistance value selection range of the second resistor R2 are determined, in practical applications, the resistance value of the first resistor R1 is selected in the resistance value selection range of the first resistor R1, and the resistance value of the second resistor R2 is selected in the resistance value selection range of the second resistor R2 according to practical requirements.
For example, in one embodiment of the present invention,
Figure BDA0002885955460000142
then, the specific values of the first resistor R1 and the second resistor R2 can be selected accordingly.
UiInterference voltage, R, for an external ambient electric fieldC，Rf1And RCZAre all intermediate parameters, and RC＝R1＝R2，Rf1＝R3＝R4，RCZ＝RCZ1＝RCZ2，R1，R2，R3，R4Sequentially expressing the resistance value of the first resistor, the resistance value of the second resistor, the resistance value of the third resistor and the resistance value of the fourth resistor; rCZ1And RCZ2Representing Ui separately for charge signal source of charge amplifierThe coupling capacitor of the positive charge input end, Ui is to the coupling capacitor of the negative charge input end of the charge signal source of the charge amplifier; rC3Representing the impedance, R, produced by the third capacitance7Representing the resistance of the seventh resistor.
As can be seen from the foregoing description, RCZIs a coupling capacitor CZ1、CZ2The generated impedance when setting Rf1＝10kΩ，f＝50Hz，CZ1＝CZ2When not greater than 0.1nF, RCZ31.83M Ω, and is for example in UCR is less than the set thresholdCWhen values are 200k omega, 500k omega, 1M omega and 5M omega in sequence, the comparison of theoretical calculation and simulation results can be seen in the following table I.
Table one:
Figure BDA0002885955460000151
it can be seen that the errors of the theoretical calculation and the simulation result are both within an acceptable range, and it can also be seen from table one that the voltage of the common mode output is reduced to be very low by the application, and the effect is very good.
The effect of suppressing common mode interference according to the present application can also be described with reference to fig. 7a and 7 b. Fig. 7a is a schematic waveform diagram of each detection position of a conventional charge amplifier without a negative feedback circuit according to the present application when common mode interference exists, where curves in each coordinate axis from top to bottom sequentially show: 1-differential output voltage, 2-output common mode voltage. 3-input common mode voltage. 4 voltage/interference source.
Fig. 7b is a schematic waveform diagram of each detection position of the charge amplifier based on the negative feedback circuit to which the present invention is applied when there is common mode interference, and curves in each coordinate axis from top to bottom sequentially show: the output voltage of the 1-positive charge converter, i.e. the voltage at position 1 marked in fig. 2, 3, 4 with respect to the reference terminal. The output voltage of the 2-negative charge converter, i.e. the voltage at position 2 marked in fig. 2, 3, 4 with respect to the reference terminal. 3-differential output voltage, i.e. the voltage at position 3 marked in fig. 2, 3, 4 with respect to the reference terminal. 4-output common mode voltage, i.e. the voltage at position 4 marked in fig. 2, 3, 4 with respect to the reference terminal. 5-input common mode voltage, i.e. the voltage at position 5 relative to the reference terminal, marked in figures 2, 3, 4. 6-voltage/interference source.
It should be noted that, with respect to the scheme of fig. 4, the first capacitor C1, the second capacitor C2, the first resistor R1, and the second resistor R2 affect the transfer coefficient of the first RC circuit formed by the seventh capacitor C7 and the thirteenth resistor R13, and therefore, after values of the first resistor R1 and the second resistor R2 are determined, values of the seventh capacitor C7 and the thirteenth resistor R13 need to be adjusted.
The cut-off frequency of the differential charge amplifier of the present application can be expressed as:
Figure BDA0002885955460000161
on the other hand, in order to ensure stable low-frequency response of the charge amplifier, the differential charge amplifier including the RC, the pyroelectric suppression, and the common mode rejection negative feedback circuit is required to be monotonically attenuated in the low-frequency cutoff frequency range, and therefore, after the common mode rejection negative feedback circuit provided in fig. 4 changes the resistance values of the first resistor R1 and the second resistor R2, the thirteenth resistor R13 and the seventh capacitor C7 in the first RC circuit are calculated as follows:
setting up
Figure BDA0002885955460000162
At other parameters, i.e. Cf、R8、C7In the known case, R can be obtained13The value of (a), i.e. solve:
Figure BDA0002885955460000163
this quadratic equation of unity yields R13The values of (d) are expressed as:
Figure BDA0002885955460000164
that is, the thirteenth resistor R13 in this embodiment has a resistance value according to
Figure BDA0002885955460000165
Determining the resistance value;
wherein the intermediate parameter
Figure BDA0002885955460000166
fLRepresenting the target cut-off frequency, C3Representing the capacitance value, R, of the third capacitor8And C7Respectively representing the resistance value of the eighth resistor, the capacitance value of the seventh capacitor and an intermediate parameter Cf＝C3＝C4，C3And C4Respectively representing the capacitance value of the third capacitor and the capacitance value of the fourth capacitor, and an intermediate parameter.
And setting the high-pass cut-off frequency to be 3.62Hz and R through simulation checking calculationC＝R2＝R1＝200kΩ，C3220nF, target cutoff frequency is 3Hz, and C is setf＝0.2nF、R8＝10MΩ、C7220nF from R above13Can be found by the calculation formula of (1)13168.635k Ω. The circuit simulation was carried in and the results were consistent with expectations.
By applying the technical scheme provided by the embodiment of the invention, considering that the common-mode input range of the charge amplifier is limited, although the circuit with the differential amplification function formed by the positive charge converter, the negative charge converter and the differential superposition circuit can eliminate common-mode interference, when the common-mode interference entering the charge amplifier exceeds the common-mode input range of the positive charge converter and the negative charge converter, harmful differential-mode signals can be generated at the differential output end, namely the output end of the differential superposition circuit. Therefore, the purpose of the present application is to reduce the interference of the common mode input, and the specific scheme can be realized by a negative feedback circuit formed by the first resistor, the second resistor, the third resistor and the fourth resistor. This application scheme has increased the common mode negative feedback resistance of charge amplifier output to input, has specifically set up respectively with the third resistance and the fourth resistance that positive charge converter output and negative charge converter output are connected promptly, the first end of second resistance then with the first input end of positive charge converter be connected, the second end of second resistance is connected with the first end of first resistance, the second end of first resistance then is connected with the first input of negative charge converter. And the common end of the third resistor and the fourth resistor is connected with the common end of the first resistor and the second resistor, thereby forming a negative feedback circuit. The common-mode input voltage can not exceed the common-mode input range of the positive charge converter and the negative charge converter, the common-mode voltage output by the positive charge converter and the negative charge converter is reduced, the differential superposition circuit can effectively eliminate common-mode interference through differential output, and the scheme of the application can effectively reduce the finally output common-mode interference signal. In addition, the negative feedback circuit formed by the first resistor, the second resistor, the third resistor and the fourth resistor can be used for realizing the negative feedback circuit, the structure is simple, the cost is low, and the implementation is easy. In summary, the scheme of the application can effectively reduce common-mode interference, and is simple and easy to implement.
Corresponding to the above embodiments of the disturbance-reducing charge amplifier, the embodiments of the present invention further provide a signal processing device, which may include the disturbance-reducing charge amplifier in any of the above embodiments, and a description thereof is not repeated here.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, article, or apparatus that comprises the element.
The principle and the implementation of the present invention are explained in the present application by using specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

Claims (10)

1. A reduced glitch charge amplifier, comprising:
the first input end is respectively connected with the preceding stage circuit and the first end of the second resistor, the second input end is used as a reference end and is connected with the second input end of the negative charge converter, and the positive charge converter is used for converting an input charge signal into a voltage signal and amplifying and outputting the voltage signal;
the first input end is respectively connected with the preceding stage circuit and the second end of the first resistor, and the negative charge converter is used for converting the input charge signal into a voltage signal and amplifying and outputting the voltage signal;
the first input end is connected with the output end of the positive charge converter, the second input end is connected with the output end of the negative charge converter, and the third input end is connected with the reference end, so that the differential superposition circuit is used for summing differential voltages;
a third resistor having a first terminal connected to the output terminal of the positive charge converter and a second terminal connected to the first terminal of the fourth resistor; the fourth resistor with a second end connected with the output end of the negative charge converter; the first resistor is connected with the second end of the second resistor at a first end; the second resistor; and a connection end of the first resistor and the second resistor is used as a first target end, a connection end of the third resistor and the fourth resistor is used as a second target end, and the first target end is connected with the second target end.
2. The jammer reduction charge amplifier of claim 1, further comprising:
a proportional amplifying circuit disposed between the first target terminal and the second target terminal.
3. The jammer reduction charge amplifier of claim 2, wherein the scaling circuit comprises:
the same-direction input end is connected with the second target end, the reverse-phase input end is respectively connected with the first end of a fifth resistor and the first end of a sixth resistor, and the output end is respectively connected with the second end of the sixth resistor and the first target end;
the fifth resistor with a second end connected with the reference end;
the sixth resistor.
4. The interference reducing charge amplifier of claim 1, wherein the positive charge converter comprises:
the non-inverting input end is used as a second input end of the positive charge converter, the inverting input end is used as a first input end of the positive charge converter and is simultaneously connected with the preceding-stage circuit, a first end of the second resistor, a first end of the fourth capacitor and a first end of the eighth resistor, and the output end is used as a second operational amplifier of the output end of the positive charge converter;
the second end of the fourth capacitor is connected with the output end of the second operational amplifier and the second end of the ninth resistor respectively;
the second end of the eighth resistor is connected with the first end of the ninth resistor;
the ninth resistor;
the negative charge converter includes:
the non-inverting input end is used as a second input end of the negative charge converter, the inverting input end is used as a first input end of the negative charge converter and is simultaneously connected with the preceding-stage circuit, a second end of the first resistor, a first end of the sixth capacitor and a first end of the eleventh resistor, and the output end is used as a third operational amplifier of the output end of the negative charge converter;
the sixth capacitor with a second end connected with the output end of the third operational amplifier and the second end of the twelfth resistor respectively;
an eleventh resistor having a second end connected to the first end of the twelfth resistor;
the twelfth resistor.
5. The jammer reduction charge amplifier of claim 4, further comprising:
a second RC circuit disposed between the preceding stage circuit and the first input terminal of the positive charge converter;
a third RC circuit disposed between the pre-stage circuit and the first input terminal of the negative charge converter;
and, the second RC circuit includes a third capacitor and a seventh resistor, the third RC circuit includes a fifth capacitor and a tenth resistor:
a first end of the third capacitor is used as a first end of the second RC circuit and is connected with the preceding stage circuit and a first end of the second resistor, a second end of the third capacitor is connected with a first end of the seventh resistor, and a second end of the seventh resistor is used as a second end of the second RC circuit and is connected with a first input end of the positive charge converter;
a first end of the fifth capacitor is used as a first end of the third RC circuit and is connected with the preceding stage circuit and a second end of the first resistor, a second end of the fifth capacitor is connected with a first end of the tenth resistor, and a second end of the tenth resistor is used as a second end of the third RC circuit and is connected with a first input end of the negative charge converter.
6. The jammer reduction charge amplifier of claim 5, further comprising: a first capacitor and a second capacitor;
the second end of the second capacitor is respectively connected with the first end of the first capacitor and the first target end;
when the first end of the second capacitor is connected with the first end of the second resistor, the second end of the first capacitor is connected with the second end of the first resistor;
when the first end of the second capacitor is connected with the second end of the third capacitor, the second end of the first capacitor is connected with the second end of the fifth capacitor;
when the first end of the second capacitor is connected with the second end of the seventh resistor, the second end of the first capacitor is connected with the second end of the tenth resistor.
7. The interference-reducing charge amplifier of claim 6, wherein the selected range of resistance values of the first resistor and the selected range of resistance values of the second resistor are both based on a common-mode output voltage UCDetermining a resistance value selection range according to a rule smaller than a preset threshold value;
wherein the content of the first and second substances,
Figure FDA0002885955450000031
Uiinterference voltage, R, for an external ambient electric fieldC，Rf1And RCZAre all intermediate parameters, and RC＝R1＝R2，Rf1＝R3＝R4，RCZ＝RCZ1＝RCZ2，R1，R2，R3，R4Sequentially expressing the resistance value of the first resistor, the resistance value of the second resistor, the resistance value of the third resistor and the resistance value of the fourth resistor; rCZ1And RCZ2Respectively representing the coupling capacitance of Ui to the positive charge input end of the charge signal source of the charge amplifier and the coupling capacitance of Ui to the negative charge input end of the charge signal source of the charge amplifier; rC3Representing the impedance, R, produced by the third capacitance7Representing the resistance of the seventh resistor.
8. The jammer reduction charge amplifier of claim 7, further comprising:
a first RC circuit connected to both the positive charge converter and the negative charge converter;
and, the first RC circuit includes:
the first end of the thirteenth resistor is connected with the second end of the eighth resistor, and the second end of the thirteenth resistor is connected with the first end of the seventh capacitor;
the seventh capacitor with a second end connected with the second end of the eleventh resistor;
and the resistance value of the thirteenth resistor is according to
Figure FDA0002885955450000041
Determining the resistance value;
wherein the intermediate parameter
Figure FDA0002885955450000042
fLRepresenting the target cut-off frequency, C3Representing the capacitance value, R, of the third capacitor8And C7Respectively representing the resistance value of the eighth resistor, the capacitance value of the seventh capacitor and an intermediate parameter Cf＝C3＝C4，C3And C4Respectively representing the capacitance value of the third capacitor and the capacitance value of the fourth capacitor, and an intermediate parameter.
9. The jammer reduction charge amplifier of claim 4, wherein the differential superposition circuit comprises:
the first end of the fourth resistor is used as the first input end of the differential superposition circuit, and the second end of the fourth resistor is connected with the second end of the fifth resistor and the non-inverting input end of the fourth operational amplifier;
the fifteenth resistor with a first end serving as a third input end of the differential superposition circuit;
the first end of the differential superposition circuit is used as a second input end of the differential superposition circuit, and the second end of the differential superposition circuit is respectively connected with the first end of a seventeenth resistor and the inverted input end of the fourth operational amplifier;
the output end of the fourth operational amplifier is used as the output end of the differential superposition circuit and is connected with the second end of the seventeenth resistor;
the seventeenth resistor.
10. A signal processing apparatus comprising a disturbance reduction charge amplifier as claimed in any one of claims 1 to 9.
CN202110013731.XA 2021-01-06 2021-01-06 Signal processing equipment and interference reduction charge amplifier thereof Pending CN112636700A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110013731.XA CN112636700A (en) 2021-01-06 2021-01-06 Signal processing equipment and interference reduction charge amplifier thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110013731.XA CN112636700A (en) 2021-01-06 2021-01-06 Signal processing equipment and interference reduction charge amplifier thereof

Publications (1)

Publication Number Publication Date
CN112636700A true CN112636700A (en) 2021-04-09

Family

ID=75291599

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110013731.XA Pending CN112636700A (en) 2021-01-06 2021-01-06 Signal processing equipment and interference reduction charge amplifier thereof

Country Status (1)

Country Link
CN (1) CN112636700A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115296631A (en) * 2022-07-15 2022-11-04 广州致远仪器有限公司 Differential circuit, circuit board and electronic equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115296631A (en) * 2022-07-15 2022-11-04 广州致远仪器有限公司 Differential circuit, circuit board and electronic equipment

Similar Documents

Publication Publication Date Title
CN107294501B (en) Chopper amplification circuit device and implementation method thereof
CN205562653U (en) Current inducer
CN110988430B (en) Fluxgate heavy current sensor based on digital second harmonic detection and ripple compensation
JP5253687B1 (en) Voltage detector
KR20170110103A (en) Electronic integrator for Rogowski coil sensor
CN112636700A (en) Signal processing equipment and interference reduction charge amplifier thereof
CN105897248A (en) Weak signal reading circuit
CN213937842U (en) Signal processing equipment and interference reduction charge amplifier thereof
CN217363029U (en) Signal processing equipment and interference reduction charge amplifier thereof
CN210514514U (en) Small signal acquisition circuit applied to power distribution terminal
CN114915269A (en) Signal processing equipment and interference reduction charge amplifier thereof
CN204360189U (en) The analog input Acquisition Circuit of electromagnetic interference (EMI) is suppressed in industrial control system
JP3999303B2 (en) Current detector
CN212622770U (en) Isolation transformer applied to KTV audio acquisition and detection
US4245202A (en) Floating gyrator having a current cancellation circuit
CN207067305U (en) A kind of bandwidth-limited circuit for being used to measure leakage current of an arrester triple-frequency harmonics
CN114660349A (en) Feeder automation terminal FTU and signal conditioning method
CN220271426U (en) Sampling connecting device for current transformer
Wang et al. Frequency response analysis of a Rogowski coil transducer for railgun pulse current measurement
CN217032618U (en) Floating differential amplification system for sensor signals
JP2666860B2 (en) Negative impedance circuit
CN109302163A (en) A kind of modified Anti-aliasing Filter Circuits
CN207753691U (en) A kind of modified Anti-aliasing Filter Circuits
JPS6173497A (en) Input circuit of equalizer amplifier
CN209432883U (en) A kind of high frequency sound Hall integrated circuit with enlarging function

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination