CN217363029U - Signal processing equipment and interference reduction charge amplifier thereof - Google Patents
Signal processing equipment and interference reduction charge amplifier thereof Download PDFInfo
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- CN217363029U CN217363029U CN202220658169.6U CN202220658169U CN217363029U CN 217363029 U CN217363029 U CN 217363029U CN 202220658169 U CN202220658169 U CN 202220658169U CN 217363029 U CN217363029 U CN 217363029U
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Abstract
The application discloses reduce charge amplifier of interference includes: a first operational amplifier and a first capacitor which form a positive charge converter; a second operational amplifier and a second capacitor which form a negative charge converter; the differential superposition circuit is respectively connected with the output end of the first operational amplifier, the output end of the second operational amplifier and the reference end and is used for carrying out differential voltage summation; the input end of the differential superposition circuit is connected with the output end of the differential superposition circuit, the output end of the differential superposition circuit is connected with the inverting input end of the first operational amplifier, and the differential mode negative feedback circuit is used for inhibiting differential mode interference through negative feedback; and the common mode negative feedback circuit is respectively connected with the output end of the first operational amplifier, the output end of the second operational amplifier, the inverting input end of the first operational amplifier and the inverting input end of the second operational amplifier and is used for reducing the common mode input current through the output negative feedback current. By applying the scheme of the application, common mode interference and differential mode interference can be effectively reduced, the structure is simple, and the application also discloses signal processing equipment which has corresponding technical effects.
Description
Technical Field
The utility model relates to the technical field of circuits, especially, relate to a signal processing equipment and fall charge amplifier of interference thereof.
Background
The classic differential charge amplifier can cause the operating point to drift greatly due to the asymmetric parameters, thermal imbalance and the like of the positive charge amplifier and the negative charge amplifier, and when the piezoelectric sensitive device is independently arranged at the far end of the charge amplifier, common mode interference in the environment easily enters the charge amplifier at the later stage through the distributed capacitors CZ1 and CZ2 between a cable connected with the piezoelectric sensitive device and an interference electric field, and interference signals can directly enable the output amplitude of the charge amplifier to be limited. And, when the distribution capacitance of the cable transmitting the piezoelectric sensitive device is not symmetrical to that of the external interference source, differential mode interference is also generated.
At present, low-frequency differential mode interference is reduced by improving device precision, adding a filter and the like, but the cost is high, and the method cannot be widely applied to engineering processes. In addition, the filter increases the low frequency response frequency, i.e., reduces the bandwidth, when suppressing low frequency differential mode interference.
In summary, how to effectively reduce the common mode interference and the differential mode interference is a technical problem that needs to be solved urgently by those skilled in the art.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a signal processing equipment and fall charge amplifier who disturbs thereof to reduce common mode interference and differential mode interference effectively.
In order to solve the technical problem, the utility model provides a following technical scheme:
a disturbance reduction charge amplifier, comprising:
the first operational amplifier is used for enabling the reverse-phase input end to serve as a positive charge input end and to be connected with the preceding stage circuit and the first end of the first capacitor respectively, enabling the non-phase input end to serve as a reference end and to be connected with the non-phase input end of the second operational amplifier, and enabling the output end to be connected with the second end of the first capacitor;
the second operational amplifier is provided with an inverting input end serving as a negative charge input end and connected with the preceding stage circuit and a first end of a second capacitor respectively, and an output end connected with a second end of the second capacitor;
the first capacitor, the second capacitor;
the first input end is connected with the output end of the first operational amplifier, the second input end is connected with the output end of the second operational amplifier, and the third input end is connected with the reference end, and the differential superposition circuit is used for carrying out differential voltage summation;
the input end of the differential superposition circuit is connected with the output end of the differential superposition circuit, the output end of the differential superposition circuit is connected with the inverting input end of the first operational amplifier, and the differential negative feedback circuit is used for inhibiting differential mode interference through negative feedback;
the first input end is connected with the output end of the first operational amplifier, the second input end is connected with the output end of the second operational amplifier, the first output end is connected with the inverting input end of the first operational amplifier, the second output end is connected with the inverting input end of the second operational amplifier, and the common mode negative feedback circuit is used for reducing common mode input current through output negative feedback current.
Preferably, the differential mode negative feedback circuit includes:
and the first end of the fifth resistor is connected with the inverting input end of the first operational amplifier, and the second end of the fifth resistor is connected with the output end of the differential superposition circuit.
Preferably, the differential mode negative feedback circuit further includes:
the first end of the sixth resistor is connected with the second end of the fifth resistor, and the second end of the sixth resistor is connected with the output end of the differential superposition circuit;
and a first end of the first RC circuit is respectively connected with a second end of the fifth resistor and a first end of the sixth resistor, and a second end of the first RC circuit is connected with the reference end.
Preferably, the first RC circuit includes:
the first end of the third capacitor is used as the first end of the first RC circuit, and the second end of the third capacitor is connected with the first end of the seventh resistor;
the second terminal is the seventh resistor of the second terminal of the first RC circuit.
Preferably, the differential superimposing circuit includes:
the first end of the eighth resistor is used as the first input end of the differential superposition circuit, and the second end of the eighth resistor is connected with the non-inverting input end of the third operational amplifier;
a ninth resistor, a first end of which is used as a third input end of the differential superposition circuit, and a second end of which is connected with a non-inverting input end of the third operational amplifier;
a tenth resistor, a first end of which is used as a second input end of the differential superposition circuit, and a second end of which is connected with the inverting input end of the third operational amplifier;
the eleventh resistor with a first end connected with the second end of the tenth resistor;
the output end of the differential superposition circuit is connected with the second end of the eleventh resistor, and the connecting end of the differential superposition circuit is used as the third operational amplifier of the output end of the differential superposition circuit.
Preferably, the common mode negative feedback circuit includes:
the first resistor is connected with the first end of the second resistor, the second end of the third resistor and the first end of the fourth resistor at the first end;
the second resistor is connected with the inverting input end of the second operational amplifier at the second end;
the first end of the third resistor is connected with the output end of the first operational amplifier;
and the second end of the fourth resistor is connected with the output end of the second operational amplifier.
Preferably, the method further comprises the following steps:
the second RC circuit is arranged between the preceding stage circuit and the inverting input end of the first operational amplifier;
and the third RC circuit is arranged between the preceding stage circuit and the inverting input end of the second operational amplifier.
Preferably, the second RC circuit includes a fourth capacitor and a twelfth resistor, and the third RC circuit includes a fifth capacitor and a thirteenth resistor:
a first end of the fourth capacitor is used as a first end of the second RC circuit and is connected to the preceding stage circuit, a second end of the fourth capacitor is connected to a first end of the twelfth resistor, and a second end of the twelfth resistor is used as a second end of the second RC circuit and is connected to an inverting input terminal of the first operational amplifier;
a first end of the fifth capacitor is used as a first end of the third RC circuit and is connected to the preceding stage circuit, a second end of the fifth capacitor is connected to a first end of the thirteenth resistor, and a second end of the thirteenth resistor is used as a second end of the third RC circuit and is connected to an inverting input terminal of the second operational amplifier;
when the first end of the fourth capacitor is connected with the first end of the first resistor, the first end of the fifth capacitor is connected with the second end of the second resistor; when the second end of the fourth capacitor is connected with the first end of the first resistor, the second end of the fifth capacitor is connected with the second end of the second resistor; when the second end of the twelfth resistor is connected with the first end of the first resistor, the second end of the thirteenth resistor is connected with the second end of the second resistor.
Preferably, the method further comprises the following steps: a sixth capacitor and a seventh capacitor;
a second end of the sixth capacitor is connected with a first end of the seventh capacitor, a second end of the first resistor, a first end of the second resistor, a second end of the third resistor and a first end of the fourth resistor respectively;
when the first end of the sixth capacitor is connected with the first end of the fourth capacitor, the second end of the seventh capacitor is connected with the first end of the fifth capacitor;
when the first end of the sixth capacitor is connected with the second end of the fourth capacitor, the second end of the seventh capacitor is connected with the second end of the fifth capacitor;
when the first end of the sixth capacitor is connected with the second end of the twelfth resistor, the second end of the seventh capacitor is connected with the second end of the thirteenth resistor.
A signal processing apparatus comprising a disturbance reduction charge amplifier as claimed in any one of the preceding claims.
Use the embodiment of the utility model provides a technical scheme, the mode of considering difference stack can eliminate common mode interference, but when common mode interference surpassed the common mode input range that fortune was put, will produce harmful differential mode signal at the difference output, difference stack circuit's output promptly. Therefore, the common mode negative feedback circuit is provided in the scheme of the application, specifically, a first input end of the common mode negative feedback circuit is connected with an output end of the first operational amplifier, a second input end of the common mode negative feedback circuit is connected with an output end of the second operational amplifier, a first output end of the common mode negative feedback circuit is connected with an inverted output end of the first operational amplifier, and a second output end of the common mode negative feedback circuit is connected with an inverted output end of the second operational amplifier. The common mode negative feedback circuit can reduce the common mode voltage output by the first operational amplifier and the second operational amplifier, so that the differential superposition circuit can effectively eliminate common mode interference through differential output, namely, the scheme of the application can effectively reduce the finally output common mode interference signal through the design of the common mode negative feedback circuit. Meanwhile, the scheme of the application is provided with the differential mode negative feedback circuit for inhibiting the differential mode interference through negative feedback, and in the scheme of the application, the design of a negative feedback resistor in the charge amplifier is cancelled, so that the low-frequency response is favorably improved. The negative feedback resistor of the original design in the charge amplifier can stabilize a direct current working point, and after the design of the negative feedback resistor is cancelled, because a differential mode negative feedback circuit is designed, the input end of the differential mode negative feedback circuit is connected with the output end of a differential superposition circuit, and the output end of the differential mode negative feedback circuit is connected with the inverting input end of a first operational amplifier, the direct current working point can be stabilized through the differential mode negative feedback circuit. To sum up, the scheme of the application can effectively reduce common mode interference and differential mode interference, and has a simple structure.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of a first structure of a charge amplifier for reducing interference according to the present invention;
fig. 2 is a second structural diagram of the interference-reducing charge amplifier according to the present invention;
fig. 3 is a schematic diagram of a third structure of the disturb reducing charge amplifier of the present invention;
fig. 4 is a fourth structural diagram of the interference-reducing charge amplifier according to the present invention;
fig. 5 is a fifth structural diagram of the interference-reducing charge amplifier of the present invention;
fig. 6 is a sixth structural diagram of the interference-reducing charge amplifier of the present invention;
fig. 7 is a seventh structural diagram of the interference-reducing charge amplifier according to the present invention;
fig. 8a is a waveform diagram illustrating a stable dc operating point and suppression of common mode and differential mode interference of the interference reduction charge amplifier according to the present application under the condition of a dc operating point voltage offset of the charge amplifier;
FIG. 8b is a waveform diagram of a conventional charge amplifier at each detection position under the condition of the DC operating point voltage offset of the charge amplifier;
FIG. 9a is a schematic amplitude-frequency curve of the disturbance reduction charge amplifier of the present application;
fig. 9b is a schematic diagram of the amplitude-frequency curve of the conventional charge amplifier.
FIG. 10 is a schematic diagram of a conventional charge amplifier with increased common mode or differential mode negative feedback;
Detailed Description
The utility model discloses a core is that a charge amplifier who falls the interference is provided, common mode interference and differential mode interference can be reduced effectively to simple structure.
In order to make the technical field better understand the solution of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings and the detailed description. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a disturbance reduction charge amplifier according to the present invention, the disturbance reduction charge amplifier may include:
a first operational amplifier OP1, the inverting input terminal of which is used as a positive charge input terminal and is respectively connected with the preceding stage circuit and the first terminal of the first capacitor C1, the non-inverting input terminal of which is used as a reference terminal and is connected with the non-inverting input terminal of the second operational amplifier OP2, and the output terminal of which is connected with the second terminal of the first capacitor C1;
a second operational amplifier OP2, the inverting input terminal of which is used as a negative charge input terminal and is respectively connected with the preceding stage circuit and the first terminal of the second capacitor C2, and the output terminal of which is connected with the second terminal of the second capacitor C2;
a first capacitor C1, a second capacitor C2;
the first input end is connected with the output end of a first operational amplifier OP1, the second input end is connected with the output end of a second operational amplifier OP2, the third input end is connected with a reference end, and the differential superposition circuit 10 is used for carrying out differential voltage summation;
the differential mode negative feedback circuit 20 is connected with the input end of the differential superposition circuit 10 and the output end of the differential superposition circuit is connected with the inverting input end of the first operational amplifier OP1, and is used for inhibiting differential mode interference through negative feedback;
the first input end is connected with the output end of the first operational amplifier OP1, the second input end is connected with the output end of the second operational amplifier OP2, the first output end is connected with the inverting input end of the first operational amplifier OP1, the second output end is connected with the inverting input end of the second operational amplifier OP2, and the common mode negative feedback circuit 30 is used for reducing the common mode input current through the output negative feedback current.
The output of differential voltage can be realized by a positive charge converter and a negative charge converter, and then the differential voltage summation is performed by the differential superposition circuit 10, the conventional charge converter generally includes an operational amplifier, a feedback capacitor and a feedback resistor, for example, fig. 10 is a structural schematic diagram of a conventional charge amplifier adding common mode or differential mode negative feedback, the resistors R3, R4, R5 and R6 in fig. 10 are all feedback resistors, and the capacitors C1 and C2 are all feedback capacitors.
In the scheme of the present application, the feedback resistor in the charge converter is eliminated, that is, in the scheme of the present application, the positive charge converter includes the first operational amplifier OP1 and the first capacitor C1, and the negative charge converter includes the second operational amplifier OP2 and the second capacitor C2, compared with fig. 10, 2 resistors are reduced in both the positive and negative charge converters in the scheme of the present application.
And, the parameters are typically symmetric, i.e., C1 ═ C2. This is considering that a conventional charge converter includes an operational amplifier, a feedback capacitor Cf and a feedback resistor Rf, and the low-frequency cutoff frequency f0 can be expressed as: f0 is 1/(2 pi RfCf), and in practical engineering, the resistance of the resistor device is difficult to increase due to space limitations, and the like, so that it can be seen that the feedback resistance limits the low frequency response of the charge converter.
In the scheme of the application, a feedback resistor limiting the low-frequency response of the charge converter in the charge converter is eliminated, and as can be known from f0 being 1/(2 pi RfCf), the value of the feedback resistor Rf in the formula is increased, so that the low-frequency cutoff frequency f0 is reduced, and the low-frequency response of the charge converter is favorably improved.
However, the cancellation of the feedback resistor will cause the dc operating point of the output of the charge converter to shift. In contrast, the differential mode negative feedback circuit 20 is provided in the scheme of the present application, the input terminal of the differential mode negative feedback circuit 20 is connected to the output terminal of the differential superposition circuit 10, and the output terminal is connected to the inverting input terminal of the first operational amplifier OP1, so that the dc operating point can be stabilized. Furthermore, the suppression capability of the differential mode DC interference can be enhanced by the differential mode negative feedback circuit 20.
The specific circuit configuration of the differential mode negative feedback circuit 20 can be set and adjusted according to actual conditions, for example, in a specific embodiment of the present invention, referring to fig. 2, the differential mode negative feedback circuit 20 includes:
and a fifth resistor R5, the first end of which is connected to the inverting input terminal of the first OP1, and the second end of which is connected to the output terminal of the differential superposition circuit 10.
In this embodiment, the differential-mode negative feedback circuit 20 is composed of 1 resistor, and has a simple structure, that is, the output terminal of the differential superposition circuit 10 and the inverting input terminal of the first operational amplifier OP1 are connected through a fifth resistor R5, so as to implement differential-mode negative feedback. And because the structure of the implementation mode is simple, compared with the traditional scheme of a charge converter which needs to be provided with a feedback resistor, the design of the implementation mode effectively reduces the required number of devices, and the reliability of the circuit is improved.
Further, in an embodiment of the present invention, the differential mode negative feedback circuit 20 may further include:
a sixth resistor R6 having a first end connected to the second end of the fifth resistor R5 and a second end connected to the output end of the differential superposition circuit 10;
and a first end of the first RC circuit is respectively connected with the second end of the fifth resistor R5 and the first end of the sixth resistor R6, and a second end of the first RC circuit is connected with the reference end.
In this embodiment, a first RC circuit, that is, a low-frequency bootstrap bypass, is further introduced, so that the low-frequency cut-off frequency of the charge converter can be effectively reduced, the bandwidth is extended, and the low-frequency performance is also effectively improved, and the effect of the first RC circuit on extending the bandwidth can be reflected in fig. 9a and 9b later. And because the first RC circuit needs to be introduced, a sixth resistor R6 is also arranged in series with the fifth resistor R5, the sixth resistor R6 and the fifth resistor R5 jointly form a negative feedback resistor, and the first RC circuit is introduced into the connection end of the sixth resistor R6 and the negative feedback resistor.
In a specific embodiment of the present invention, referring to fig. 3, the first RC circuit may specifically include:
a third capacitor C3, the first end of which is used as the first end of the first RC circuit, and the second end of which is connected with the first end of a seventh resistor R7;
the second terminal acts as a seventh resistor R7 for the second terminal of the first RC circuit.
In this embodiment, the first RC circuit is composed of the third capacitor C3 and the seventh resistor R7, and has a simple structure and high reliability.
In addition, the common mode negative feedback circuit 30 and the differential mode negative feedback circuit 20 added in the scheme of the present application have no influence on the transmission coefficient of the piezoelectric signal (normal signal) of the original broadband charge amplifier.
The common mode negative feedback circuit 30 is used for suppressing common mode interference, and the common mode input voltage can not exceed the common mode input range of the first operational amplifier OP1 and the second operational amplifier OP2 through the common mode negative feedback circuit 30, so that the common mode voltage output by the first operational amplifier OP1 and the second operational amplifier OP2 is reduced, the differential superposition circuit 10 is enabled to output through differential output, and the common mode interference can be effectively eliminated.
In an embodiment of the present invention, referring to fig. 2, the common mode negative feedback circuit 30 may include:
a first resistor R1 having a first end connected to the inverting input terminal of the first operational amplifier OP1 and a second end connected to the first end of the second resistor R2, the second end of the third resistor R3 and the first end of the fourth resistor R4, respectively;
a second resistor R2 having a second terminal connected to the inverting input terminal of the second OP 2;
a third resistor R3 with a first end connected with the output end of the first operational amplifier OP 1;
and the second end of the fourth resistor R4 is connected with the output end of the second operational amplifier OP 2.
In fig. 2, Z + represents the positive charge input terminal of the disturbance reduction charge amplifier of the present application, Z-represents the negative charge input terminal of the disturbance reduction charge amplifier of the present application, Vref represents the reference terminal, and the specific voltage value of the reference terminal can be set according to actual needs. In addition, in this embodiment, the connection end between the first resistor R1 and the second resistor R2 is denoted by J1, and the connection end between the third resistor R3 and the fourth resistor R4 is denoted by J1, so as to indicate that these two connection ends are connected to each other.
In general, R1 ═ R2 and R3 ═ R4 may be provided. When common-mode interference enters the charge amplifier through the distributed capacitance of the sensor charge transmission cable, the common-mode output voltage of the charge amplifier is reduced by adding the common-mode negative feedback circuit 30 from the output end to the input end of the charge amplifier, so that the final output common-mode interference signal can be effectively reduced or eliminated by the post-stage differential superposition circuit 10 for eliminating the common-mode interference in a limited way, and the common-mode interference suppression of broadband is realized. The specific circuit configuration of the differential superposition circuit 10 can be set and adjusted as required, for example, in an embodiment of the present invention, referring to fig. 2, the differential superposition circuit 10 may include:
an eighth resistor R8 having a first end serving as a first input end of the differential superposition circuit 10 and a second end connected to a non-inverting input end of the third OP 3;
a ninth resistor R9 having a first end serving as a third input end of the differential superposition circuit 10 and a second end connected to a non-inverting input end of the third OP 3;
a tenth resistor R10 having a first end serving as a second input end of the differential superposition circuit 10 and a second end connected to an inverting input end of the third OP 3;
an eleventh resistor R11 having a first end connected to the second end of the tenth resistor R10;
the output end of the differential superposition circuit 10 is connected with the second end of the eleventh resistor R11, and the connection end is used as the third operational amplifier OP3 of the output end of the differential superposition circuit 10.
The differential superposition circuit 10 in this embodiment is composed of four resistors and one operational amplifier, the circuit structure is convenient to implement, and the output end of the third operational amplifier OP3 is used as the output end of the differential superposition circuit 10, namely, the differential charge conversion signal is output through the output end of the third operational amplifier OP 3. In addition, R8 ═ R10 and R9 ═ R11 are usually set.
In a specific embodiment of the present invention, the present invention further comprises:
a second RC circuit provided between the preceding circuit and the inverting input terminal of the first OP 1;
and a third RC circuit disposed between the previous stage circuit and the inverting input terminal of the second OP 2.
The pyroelectric effect can be improved by the second RC circuit and the third RC circuit, and the specific circuit configuration can be selected according to actual needs, for example, in a specific embodiment of the present invention, referring to fig. 3, the second RC circuit includes a fourth capacitor C4 and a twelfth resistor R12, and the third RC circuit includes a fifth capacitor C5 and a thirteenth resistor R13.
A first end of a fourth capacitor C4 is used as a first end of the second RC circuit and is connected with the previous stage circuit, a second end of a fourth capacitor C4 is connected with a first end of a twelfth resistor R12, and a second end of the twelfth resistor R12 is used as a second end of the second RC circuit and is connected with an inverting input end of the first operational amplifier OP 1;
a first end of a fifth capacitor C5 is used as a first end of the third RC circuit and is connected with the preceding stage circuit, a second end of the fifth capacitor C5 is connected with a first end of a thirteenth resistor R13, and a second end of the thirteenth resistor R13 is used as a second end of the third RC circuit and is connected with an inverting input end of a second operational amplifier OP 2;
when the first terminal of the fourth capacitor C4 is connected with the first terminal of the first resistor R1, the first terminal of the fifth capacitor C5 is connected with the second terminal of the second resistor R2; when the second terminal of the fourth capacitor C4 is connected to the first terminal of the first resistor R1, the second terminal of the fifth capacitor C5 is connected to the second terminal of the second resistor R2; when the second terminal of the twelfth resistor R12 is connected to the first terminal of the first resistor R1, the second terminal of the thirteenth resistor R13 is connected to the second terminal of the second resistor R2.
In the embodiment shown in fig. 3, the second RC circuit and the third RC circuit are implemented by the fourth capacitor C4, the twelfth resistor R12, the fifth capacitor C5 and the thirteenth resistor R13, which is simple and convenient. And will typically be set to C4 ═ C5, and R12 ═ R13. In fig. 3, the connection mode of the second end of the twelfth resistor R12 and the first end of the first resistor R1, the connection mode of the second end of the thirteenth resistor R13 and the second end of the second resistor R2 are shown, and the other two connection modes are indicated by broken lines in fig. 3.
In a specific embodiment of the present invention, the present invention can further include: a sixth capacitance C6 and a seventh capacitance C7;
a second end of the sixth capacitor C6 is connected to a first end of the seventh capacitor C7, a second end of the first resistor R1, a first end of the second resistor R2, a second end of the third resistor R3 and a first end of the fourth resistor R4, respectively;
when the first terminal of the sixth capacitor C6 is connected with the first terminal of the fourth capacitor C4, the second terminal of the seventh capacitor C7 is connected with the first terminal of the fifth capacitor C5;
when the first terminal of the sixth capacitor C6 is connected with the second terminal of the fourth capacitor C4, the second terminal of the seventh capacitor C7 is connected with the second terminal of the fifth capacitor C5;
when the first terminal of the sixth capacitor C6 is connected to the second terminal of the twelfth resistor R12, the second terminal of the seventh capacitor C7 is connected to the second terminal of the thirteenth resistor R13.
In this embodiment, considering the above-described embodiment, the common mode interference suppression capability for the low frequency band is strong, and in addition, the common mode interference for the high frequency band can be further reduced by adding the negative feedback of the capacitance. Further, it is generally necessary to provide C6 ═ C7.
Fig. 4, 5, 6 and 7 show that the placement positions of the sixth capacitor C6 and the seventh capacitor C7 in different embodiments can achieve the same interference suppression effect.
The suppression effect of differential mode and common mode interference according to the present application can be described by the simulation results of fig. 8a and 8 b. Fig. 8a is a waveform diagram illustrating that the interference-reducing charge amplifier stabilizes the dc operating point and suppresses common-mode and differential-mode interference when the dc operating point voltage of the charge amplifier is shifted due to asymmetry of parameters of the charge input terminal to ground insulation resistance, offset voltage of the operational amplifier, and negative feedback capacitance. Fig. 8b is a waveform diagram of the conventional charge amplifier at each detection position when the dc operating point voltage of the charge amplifier is shifted due to the asymmetry of the parameters of the insulation resistance of the charge input terminal to ground, the offset voltage of the operational amplifier, and the negative feedback capacitance. In fig. 8a and 8b, the curves in the respective coordinate axes from top to bottom represent in order: 0-differential output voltage, 1-first OP1 output voltage, 2-second OP2 output voltage, 3-output common mode voltage, i.e. the voltage at position 1, position 2, position 3 relative to the reference terminal, marked in fig. 7. 4-charge analog input voltage.
According to simulation results, the interference reduction charge amplifier can effectively stabilize a direct current working point and inhibit common mode and differential mode interference.
Fig. 9b is an amplitude-frequency curve of the conventional charge amplifier, and fig. 9a is an amplitude-frequency curve of the common-mode and differential-mode negative feedback charge amplifier, which shows that the common-mode and differential-mode negative feedback charge amplifier does not affect signal transmission after increasing the suppression capability to common-mode and differential-mode interference, reduces the low-frequency response cut-off frequency, and expands the signal bandwidth. The traditional charge amplifier is provided with a negative feedback capacitor and a negative feedback resistor, so that the low-frequency response of the charge converter is limited, namely the low-frequency response of the charge converter is difficult to promote.
Corresponding to the above embodiments of the interference-reducing charge amplifier, the embodiments of the present invention further provide a signal processing device, which may include the interference-reducing charge amplifier in any of the above embodiments, and the description is not repeated here.
Use the embodiment of the utility model provides a technical scheme, the mode of considering difference stack can eliminate common mode interference, but when common mode interference surpassed the common mode input range that fortune was put, will produce harmful differential mode signal at the difference output, difference stack circuit 10's output promptly. Therefore, the common mode negative feedback circuit 30 is provided in the solution of the present application, specifically, a first input terminal of the common mode negative feedback circuit 30 is connected to an output terminal of the first operational amplifier OP1, a second input terminal is connected to an output terminal of the second operational amplifier OP2, a first output terminal is connected to an inverting output terminal of the first operational amplifier OP1, and a second output terminal is connected to an inverting output terminal of the second operational amplifier OP 2. The common mode negative feedback circuit 30 can make the common mode voltage that first operational amplifier OP1, second operational amplifier OP2 exported reduce, also make the difference stack circuit 10 through differential output, can reject common mode interference more effectively, and the scheme of this application can reduce the common mode interference signal of final output effectively through common mode negative feedback circuit 30's design promptly. Meanwhile, the scheme of the application is provided with the differential mode negative feedback circuit 20 for inhibiting the differential mode interference through negative feedback, and in the scheme of the application, the design of a negative feedback resistor in the charge amplifier is cancelled, so that the low-frequency response is favorably improved, namely the positive charge amplifier of the application is composed of the first operational amplifier OP1 and the first capacitor C1, and the negative charge amplifier is composed of the second operational amplifier OP2 and the second capacitor C2, so that the structure is simplified, and the low-frequency response is favorably improved. The negative feedback resistance of this design can stabilize direct current operating point in the charge amplifier, after this application cancelled negative feedback resistance's design, owing to designed differential mode negative feedback circuit 20, differential mode negative feedback circuit 20's input is connected with the output of difference stack circuit 10, and the output is connected with the inverting input of first operational amplifier OP1, consequently can stabilize direct current operating point through differential mode negative feedback circuit 20. In summary, the scheme of the application can effectively reduce common mode interference and differential mode interference, and has a simple structure.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, article, or apparatus that comprises the element.
The principle and the implementation of the present invention are explained herein by applying specific examples, and the above descriptions of the embodiments are only used to help understand the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, the present invention can be further modified and modified, and such modifications and modifications also fall within the protection scope of the appended claims.
Claims (10)
1. A reduced glitch charge amplifier, comprising:
the first operational amplifier is used for taking the reverse-phase input end as a positive charge input end and is respectively connected with the preceding stage circuit and the first end of the first capacitor, taking the in-phase input end as a reference end and is connected with the in-phase input end of the second operational amplifier, and taking the output end of the first operational amplifier as the second end of the first capacitor;
the second operational amplifier is provided with an inverting input end serving as a negative charge input end and connected with the preceding stage circuit and a first end of a second capacitor respectively, and an output end connected with a second end of the second capacitor;
the first capacitor, the second capacitor;
the first input end is connected with the output end of the first operational amplifier, the second input end is connected with the output end of the second operational amplifier, and the third input end is connected with the reference end, and the differential superposition circuit is used for carrying out differential voltage summation;
the input end of the differential superposition circuit is connected with the output end of the differential superposition circuit, the output end of the differential superposition circuit is connected with the inverting input end of the first operational amplifier, and the differential negative feedback circuit is used for inhibiting differential mode interference through negative feedback;
the first input end is connected with the output end of the first operational amplifier, the second input end is connected with the output end of the second operational amplifier, the first output end is connected with the inverting input end of the first operational amplifier, the second output end is connected with the inverting input end of the second operational amplifier, and the common mode negative feedback circuit is used for reducing common mode input current through output negative feedback current.
2. The interference-reducing charge amplifier of claim 1, wherein the differential-mode negative feedback circuit comprises:
and the first end of the fifth resistor is connected with the inverting input end of the first operational amplifier, and the second end of the fifth resistor is connected with the output end of the differential superposition circuit.
3. The interference-reducing charge amplifier of claim 2, wherein the differential-mode negative feedback circuit further comprises:
the first end of the sixth resistor is connected with the second end of the fifth resistor, and the second end of the sixth resistor is connected with the output end of the differential superposition circuit;
and a first end of the first RC circuit is respectively connected with the second end of the fifth resistor and the first end of the sixth resistor, and the second end of the first RC circuit is connected with the reference end.
4. The jammer reduction charge amplifier of claim 3, wherein the first RC circuit comprises:
the first end of the third capacitor is used as the first end of the first RC circuit, and the second end of the third capacitor is connected with the first end of the seventh resistor;
the second terminal is the seventh resistor of the second terminal of the first RC circuit.
5. The jammer reduction charge amplifier of claim 1, wherein the differential superposition circuit comprises:
the first end of the eighth resistor is used as the first input end of the differential superposition circuit, and the second end of the eighth resistor is connected with the non-inverting input end of the third operational amplifier;
a ninth resistor, a first end of which is used as a third input end of the differential superposition circuit, and a second end of which is connected with a non-inverting input end of the third operational amplifier;
a tenth resistor, a first end of which is used as a second input end of the differential superposition circuit, and a second end of which is connected with the inverting input end of the third operational amplifier;
an eleventh resistor having a first end connected to the second end of the tenth resistor;
the output end of the differential superposition circuit is connected with the second end of the eleventh resistor, and the connecting end of the differential superposition circuit is used as the third operational amplifier of the output end of the differential superposition circuit.
6. The interference-reducing charge amplifier of claim 1, wherein the common-mode negative feedback circuit comprises:
the first resistor is connected with the first end of the second resistor, the second end of the third resistor and the first end of the fourth resistor at the first end;
the second end of the second resistor is connected with the inverting input end of the second operational amplifier;
the first end of the third resistor is connected with the output end of the first operational amplifier;
and the second end of the fourth resistor is connected with the output end of the second operational amplifier.
7. The jammer reduction charge amplifier of claim 6, further comprising:
the second RC circuit is arranged between the preceding stage circuit and the inverting input end of the first operational amplifier;
and the third RC circuit is arranged between the preceding stage circuit and the inverting input end of the second operational amplifier.
8. The jammer reduction charge amplifier of claim 7, wherein the second RC circuit comprises a fourth capacitor and a twelfth resistor, and wherein the third RC circuit comprises a fifth capacitor and a thirteenth resistor:
a first end of the fourth capacitor is used as a first end of the second RC circuit and is connected to the preceding stage circuit, a second end of the fourth capacitor is connected to a first end of the twelfth resistor, and a second end of the twelfth resistor is used as a second end of the second RC circuit and is connected to an inverting input terminal of the first operational amplifier;
a first end of the fifth capacitor is used as a first end of the third RC circuit and is connected to the preceding stage circuit, a second end of the fifth capacitor is connected to a first end of the thirteenth resistor, and a second end of the thirteenth resistor is used as a second end of the third RC circuit and is connected to an inverting input terminal of the second operational amplifier;
when the first end of the fourth capacitor is connected with the first end of the first resistor, the first end of the fifth capacitor is connected with the second end of the second resistor; when the second end of the fourth capacitor is connected with the first end of the first resistor, the second end of the fifth capacitor is connected with the second end of the second resistor; when the second end of the twelfth resistor is connected with the first end of the first resistor, the second end of the thirteenth resistor is connected with the second end of the second resistor.
9. The jammer reducing charge amplifier of claim 8, further comprising: a sixth capacitor and a seventh capacitor;
a second end of the sixth capacitor is connected with a first end of the seventh capacitor, a second end of the first resistor, a first end of the second resistor, a second end of the third resistor and a first end of the fourth resistor respectively;
when the first end of the sixth capacitor is connected with the first end of the fourth capacitor, the second end of the seventh capacitor is connected with the first end of the fifth capacitor;
when the first end of the sixth capacitor is connected with the second end of the fourth capacitor, the second end of the seventh capacitor is connected with the second end of the fifth capacitor;
when the first end of the sixth capacitor is connected with the second end of the twelfth resistor, the second end of the seventh capacitor is connected with the second end of the thirteenth resistor.
10. A signal processing apparatus comprising a disturbance reduction charge amplifier as claimed in any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220658169.6U CN217363029U (en) | 2022-03-24 | 2022-03-24 | Signal processing equipment and interference reduction charge amplifier thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220658169.6U CN217363029U (en) | 2022-03-24 | 2022-03-24 | Signal processing equipment and interference reduction charge amplifier thereof |
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