CN112636696A

CN112636696A - Intermediate frequency modulation and demodulation method for digital T/R assembly

Info

Publication number: CN112636696A
Application number: CN202011544511.1A
Authority: CN
Inventors: 宋锐; 桂阳
Original assignee: CETC 20 Research Institute
Current assignee: CETC 20 Research Institute
Priority date: 2020-12-24
Filing date: 2020-12-24
Publication date: 2021-04-09
Anticipated expiration: 2040-12-24
Also published as: CN112636696B

Abstract

The invention provides an intermediate frequency modulation and demodulation method of a digital T/R assembly, which adopts a digital processing method of DDS and DDC to transmit N frequency sweep signals with different frequencies and different pulse widths in one radar period and complete configuration when completing modulation and demodulation transmission of digital intermediate frequency signals, improves the configuration speed by shortening the total configuration time through controlling a DDS chip by a digital circuit, generates intermediate frequency signals after down-conversion of the signals when receiving the signals, sends data of the sampled digital signals to an FPGA, orthogonally demodulates the sampled digital signals in the FPGA, performs matched filtering on zero intermediate frequency signals by a low-pass filter and sends the zero intermediate frequency signals to a signal processing subsystem. The invention can make the blind-compensating splicing point smoother, thereby exerting the efficiency of the transmitter to the maximum extent, being beneficial to improving the cost performance of the frequency synthesizer and obtaining high I/Q orthogonal sampling precision and stability.

Description

Intermediate frequency modulation and demodulation method for digital T/R assembly

Technical Field

The invention relates to the field of digital modulation and demodulation, in particular to a method for realizing distance blind compensation by adopting multiple pulse transmission of a three-coordinate radar. The invention adopts the Digital processing mode of direct Digital Frequency synthesis technology DDS (direct Digital Frequency synthesis) and Digital down-conversion DDC (direct Digital controller) to complete the modulation and demodulation of Digital intermediate Frequency signals.

Background

With the development and the demand of the technology, higher requirements are provided for performance indexes such as the acting distance, the resolution and the speed measurement accuracy of the radar at the present stage, the detection capability of the radar to a target is in direct proportion to the average power transmitted by the radar, and under the condition that the peak power is limited by the load of a receiving device, the improvement of the average power is generally realized by increasing the width of a transmitted pulse. In order to meet the detection requirement, the waveform of the transmitted signal must be a long-pulse-width chirp signal, and a pulse compression technology is adopted in signal processing, so that the average power of the transmitted signal can be increased, the radar action distance is enlarged, the distance resolution of a radar system can be maintained, and the radio frequency source interference in an adjacent frequency band is effectively reduced. In order to prevent the burning of the receiving front end, the receiving channel is closed when the signal is transmitted, which can block the receiving of the echo within the long pulse, therefore, the all-solid-state radar has a short-range blind area with a certain distance.

The long-short pulse mode is a method mainly adopted by the traditional blind-complementing, the technology is relatively mature, the implementation is relatively simple, the full-range detection of the radar can be realized, but because the blind-complementing pulse is transmitted before the long pulse, the equivalent detection distance of the radar is reduced, and the efficiency of a solid-state transmitter is not fully exerted. In terms of radar reception, the conventional processing method includes: firstly, N different receivers are used for solving the problem through different frequency conversion frequencies and filters; secondly, after the microwave signals are down-converted to the intermediate frequency, N different frequency signals are separated at the intermediate frequency through a power divider and N different filters. The circuits of the methods are too complex and huge, and great difficulty is brought to the integrated miniaturization design.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a digital T/R component intermediate frequency modulation and demodulation method. The invention provides a method for realizing distance blind compensation by adopting a plurality of pulse emissions, which adopts a DDS and DDC digital processing method to complete the modulation and demodulation of digital intermediate frequency signals.

The technical scheme adopted by the invention for solving the technical problem comprises the following steps:

the method comprises the following steps: during transmission, N kinds of sweep frequency signals with different frequencies and different pulse widths are transmitted in one radar period, and configuration of DDS frequency words, a frequency sweep rate register, a sweep rate timer clock and a sweep frequency stepping word register must be completed in limited time;

step two: the DDS generates continuous wave signals, linear frequency modulation signals and pulse signals required by the system operation through the control of a digital circuit on the DDS chip.

Step three: increasing the configuration speed by shortening the total configuration time, wherein the configuration time is 1/configuration frequency total configuration byte (nibble, bit) number;

step four: during receiving, the microwave echo signal is down-converted to generate an intermediate frequency signal and enters a digital part, an analog signal enters an A/D converter to be subjected to band-pass sampling and converted into a digital signal, and after A/D sampling, the sampling frequency f of the intermediate frequency signal_sWith a period of 2 pi extension, the useful signal is shifted to

In a centered position, f₀The signal center frequency is obtained, the sampled signal does not generate frequency spectrum aliasing, and the analog signal before sampling can be completely recovered; sending the data of the sampled digital signal to the FPGA;

step five: dividing the sampled digital signal into N paths of intermediate frequency signals in an FPGA (field programmable gate array) for orthogonal demodulation, wherein the intermediate frequency signals comprise N sweep frequency signals with different frequencies and different pulse widths, and the signals are divided into N paths of signals after passing through the FPGA

Calculating orthogonal digital local oscillator signals, and multiplying N paths of intermediate frequency signals by N groups of different orthogonal digital local oscillator signals to obtain zero intermediate frequency signals;

step six: by designing the cut-off frequency

The low-pass filter performs matched filtering on the zero intermediate frequency signal, and filters high-frequency components and out-of-band signals introduced by interference and multiplier frequency spectrum shift. Wherein B is_sIs the signal bandwidth. Extracting the signals with different frequencies by a low-pass filter to obtain IQ baseband digital signals, and sending the IQ baseband digital signals to a signal processing subsystemAnd (4) a system.

In the first step, the DDS chip is configured by adopting the interior of the FPGA, and the configuration data is identified by the DDS internal control logic after being updated by the IO _ update signal, so that the configuration data is identified by the control logic in the DDS chip at f_nImmediately after IO _ update signal update of signal, configure f_n+1And the control data of the initial frequency and the initial phase of the signal writes all the control data into a buffer memory of the SPI port before the next IO _ update comes.

In the third step, an 8-line configuration mode is adopted, so that the data line is a control word configured with one byte in one clock cycle, and the speed of the serial clock is improved.

The low-pass filter window function method is used for designing the FIR filter.

The window function is a cassel window.

The invention has the beneficial effects that: the multi-pulse method can effectively overcome the problem of echo intensity difference of the blind-patch splice points in the traditional sense, and can enable the blind-patch splice points to be smoother, thereby exerting the efficiency of a transmitter to the maximum extent and effectively utilizing the repetition frequency.

In the method for modulating and demodulating the digital intermediate frequency signal by adopting the digital processing mode of DDC + DDS + FPGA, the characteristics of high performance, high processing speed and large storage capacity of an FPGA chip are utilized, the data can be timely and effectively stored and processed, and the real-time effect is achieved.

By utilizing the DDS chip, the output relative bandwidth is wider; the frequency resolution is high, and the frequency spectrum is pure; the high-stability dense frequency modulation characteristic is achieved; the phase and frequency adjustment is flexible; the phase noise is low; programmable and fully digital architectures; the volume is small, the price is low, and the cost performance of the frequency synthesizer is improved.

By using DDC, wider baseband signals can be processed, and the slew rate requirements on the a/D converter are also relatively low. High I/Q quadrature sampling precision and stability can be obtained.

Drawings

FIG. 1 is a schematic diagram of a transmission waveform in a radar mode;

FIG. 2 is a diagram of the DDS configuration of the present invention;

FIG. 3 is a graph of the spectrum of a signal after digital down conversion by the FPGA of the present invention; fig. 3(a) is a signal spectrum diagram after a/D sampling, fig. 3(b) is a signal spectrum diagram when an orthogonal digital local oscillator is 0.25 pi, fig. 3(c) is a signal spectrum diagram when an orthogonal digital local oscillator is 0.5 pi, and fig. 3(D) is a signal spectrum diagram when an orthogonal digital local oscillator is 0.75 pi.

Fig. 4 is a three-frequency chirp spectrum.

Fig. 5 is a single frequency point chirp spectrum.

FIG. 6 is an XS1 interface AD sine wave signal output.

FIG. 7 is an XS2 interface AD sine wave signal output.

Fig. 8 is a DDC _ fir _1 DDC sine wave signal output.

Fig. 9 is a DDC _ fir _2 DDC sine wave signal output.

Detailed Description

The invention is further illustrated with reference to the following figures and examples.

In the transmitting state, referring to fig. 1, in a radar period, the DDS transmits 3 signals f with 15MHz interval frequency and waveform of certain interval time₁、f₂、f₃It is required not only to perform frequency modulation but also to perform phase modulation. The initial state of the sweep frequency emission signal is determined by the frequency word, phase word, amplitude word and other control registers, and the sweep state is determined by the frequency sweep rate register, sweep rate timer clock and sweep frequency step word register. Emitting three different frequency, different pulse width sweep signals in one radar cycle means that the configuration of the DDS frequency word, the frequency sweep rate register, the sweep rate timer clock, and the sweep frequency step word register must be completed within a limited time. In order to solve the above difficulties, the DDS is configured by the following scheme, see fig. 2

The method comprises the following steps: the configuration data is updated by the IO _ update signal and then identified by the DDS internal control logic, so that at f_nConfiguration of the signal f immediately after IO _ update signal update_n+1Initial frequency and initial phase, all control data being written before the next IO _ update arrivesTo the cache of the SPI port;

step two: an 8-wire configuration mode is adopted, so that the data wire is a control word configured with one byte in one clock period, the speed of a serial clock is improved, and the total configuration time can be effectively shortened;

in a receiving state, the echo signal contains microwave signals of three different frequencies, and a receiver is required to distinguish the three frequencies and then digitally demodulate the three frequencies.

The method comprises the following steps: will contain three frequencies (f)_RF-15MHz，f_RF，f_RF+15MHz) of microwave signals, the total bandwidth is 40MHz, and after down-conversion through analog reception, the microwave signals are converted into intermediate frequency signals (135MHz, 150MHz, 165MHz) with bandwidths of 40 MHz;

step two: band pass sampling is performed. After calculation according to a band-pass sampling theory, the sampling rate is 120MHz (aliasing signals are mainly considered to have no influence on main signals), after A/D sampling, the intermediate frequency signals carry out periodic continuation with the sampling frequency of 120MHz as 2 pi, useful signals are moved to the position with the center of 2 pi x (150-120)/120 pi as 0.5 pi, and the sampled signals can not generate spectrum aliasing and can completely recover analog signals before sampling;

step three: the signal is divided into three paths of intermediate frequency signals in an FPGA for orthogonal demodulation, and three paths of orthogonal digital local oscillators are respectively 0.25 pi, 0.5 pi and 0.75 pi. The three paths of intermediate frequency signals are multiplied by three sets of orthogonal digital local oscillators respectively to obtain zero intermediate frequency signals, and interference among other signals and high frequency components introduced by frequency spectrum shifting of a multiplier need to be processed. A1 dB bandwidth is 3MHz low pass filter, adopt 128 order complex filter to guarantee that the degree of suppression at 15MHz is above 60dBc, the digital filter is realized in FPGA, this scheme chooses the window function (Cassel window) method to design FIR filter;

step four: the signal spectrum after a/D sampling is shown in fig. 3(a), and the signal spectrum after quadrature demodulation by three sets of quadrature digital local oscillators is shown in fig. 3(b), (c), and (D). Carrying out quadrature demodulation on 3 paths of intermediate frequency signals with an interval of 15MHz through three groups of different quadrature digital local oscillators, respectively carrying out matched filtering through an FIR low-pass filter, simultaneously filtering out high-frequency components brought by frequency mixing to obtain IQ baseband digital signals, and sending the IQ baseband digital signals to a signal processing subsystem through an optical fiber.

The experimental conditions are as follows:

an experiment operation platform: vivado 17.4 hardware development environment

An experimental instrument: a signal source; provided is a frequency spectrograph.

Experimental data: when receiving, data is injected by adopting a signal source; at the time of transmission, transmission data is generated for the DDS.

Content of the experiment

Transmitting part

And the DDS module outputs signals under the corresponding working mode according to the received control instruction. The DDS output is a 2-way signal, and the corresponding hardware outputs are XS3 and XS 4. During testing, only one path of signal is accessed at a time, and the spectrum of the signal is output by the DDS under each working mode through the frequency spectrograph.

See fig. 4 for normal operating mode: the DDS outputs linear frequency modulation signals of three frequency points, the center frequencies are 135M, 150M and 165M respectively, and the bandwidth is 4M.

See fig. 5 transmit calibration mode: the DDS outputs a dot frequency signal of a single frequency point, and the center frequency is 150M.

Emitting a test mode: the DDS outputs a dot frequency signal of a single frequency point, and the center frequency is 150M.

Setting mode of frequency spectrograph:

center frequency: 150M;

starting frequency: 100M;

termination frequency: 200M

BW：680Hz

Receiving part

And the AD signal output test is performed through the output of a select IO module. The AD output is a 2-way signal, and the corresponding hardware outputs are XS1 and XS 2. See FIG. 6 where XS1 represents the lower 14 bits of the AD output data and FIG. 7 where XS2 represents the upper 14 bits of the AD output data. During testing, one path of signal is accessed at a time, 130M, 0dB point frequency signals are injected through a signal source, and accuracy and stability of AD output sine wave signals are observed by establishing ila kernels.

In actual work, linear frequency modulation signals of three frequency points are all output through DDC, and 165M signals are taken for test verification. The DDC signal is output as 2-way signals DDC _ fir _1 and DDC _ fir _2, each way corresponding to 32-bit data, and the program divides the 32-bit signal into 2 16-bit signals dout _165[ 31: 16], dout _165_1[ 15: 0]. 166M, 0dB point frequency signals are injected through a signal source, and accuracy and stability of sine wave signals of 1M output by the DDC are observed by establishing an ila core.

Claims

1. An intermediate frequency modulation and demodulation method of a digital T/R component is characterized by comprising the following steps:

step five: dividing the sampled digital signal into N intermediate frequency signals in FPGA for orthogonal demodulation, wherein the intermediate frequency signals comprise N sweep frequency signals with different frequencies and different pulse widthsThe number is divided into N paths of signals after passing through the FPGA

step six: by designing the cut-off frequency

The low-pass filter performs matched filtering on the zero intermediate frequency signal, and filters high-frequency components and out-of-band signals introduced by interference and multiplier frequency spectrum shift. Wherein B is_sIs the signal bandwidth. The signals with different frequencies are extracted through a low-pass filter to obtain IQ baseband digital signals, and the IQ baseband digital signals are sent to a signal processing subsystem.

2. The digital T/R module if modulation and demodulation method of claim 1, wherein:

3. The digital T/R module if modulation and demodulation method of claim 1, wherein:

4. The digital T/R module if modulation and demodulation method of claim 1, wherein:

5. The digital T/R module if modulation and demodulation method of claim 1, wherein:

the window function is a cassel window.