CN112635546A - 高可靠性nmos阵列结构及其制备方法 - Google Patents

高可靠性nmos阵列结构及其制备方法 Download PDF

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CN112635546A
CN112635546A CN202011517465.6A CN202011517465A CN112635546A CN 112635546 A CN112635546 A CN 112635546A CN 202011517465 A CN202011517465 A CN 202011517465A CN 112635546 A CN112635546 A CN 112635546A
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邓晓军
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Abstract

本发明涉及一种高可靠性NMOS阵列结构及其制备方法，P型衬底上方设有P阱区，P阱区上部间隔设有多个P+注入扩散区，相邻两个P+注入扩散区之间设有多个N+注入扩散区；所述P+注入扩散区的下方设有PB层或ZP层。本发明能够有效提升NMOS功耗耐受力，提高工作可靠性。

Description

高可靠性NMOS阵列结构及其制备方法
技术领域
本发明涉及半导体技术领域,尤其是一种NMOS阵列结构及其制备方法。
背景技术
随着便携式设备及智能电源的发展，低电压MOS器件和低功耗技术也得到了飞速发展。为了满足对于低压MOS器件更低导通电阻、更高工作频率、更低驱动损耗和开关损耗的要求，其特征尺寸也从之前的0.5um逐渐缩小到0.18um，并不断向着更小线宽前进。但是，低压MOS不同于高压MOS,没有漂移区来承受大功耗，因此使用时安全可靠性相对偏低。同时，由于低压MOS器件在尺寸缩小的同时，虽然降低了功率损耗，也带来了可靠性变差的问题。例如，5V工作的D类功放，其输出级NMOS，原先用0.5um工艺设计时，由于器件尺寸还比较大，耐受的功耗较强，可以最高工作在7～8V，安全可靠性较高。而目前采用0.18um工艺设计后，由于器件整体尺寸缩小了，因此安全工作区也相应降低了，最高只能工作在5.5～7V，使用时如果电源有纹波，将使其可靠性承受较大影响。
影响NMOS安全工作区(即可靠性)的主要因素之一是NMOS器件体内寄生的NPN管启动快慢。NMOS体内寄生有NPN管，该NPN管一旦启动，NMOS就会进入大电流状态，瞬间烧坏。即寄生NPN管启动越慢，其器件的可靠性就越高。目前人们一般通过提高P阱浓度，来减缓寄生NPN管的启动。但是，P阱浓度又不能提高很多，否则NMOS的源漏击穿电压会降低。如何能进一步延缓寄生NPN管的启动，提高低压NMOS的可靠性，成了制约低压NMOS进一步发展的瓶颈。
发明内容
本发明的发明目的在于提供一种高可靠性NMOS阵列结构及制备方法，能够有效提升NMOS功耗耐受力，提高工作可靠性。
基于同一发明构思，本发明具有两个独立的技术方案：
1、一种高可靠性NMOS阵列结构，包括P型衬底，所述P型衬底上方设有P阱区，其特征在于：
P阱区上部间隔设有多个P+注入扩散区，相邻两个P+注入扩散区之间设有多个N+注入扩散区，所述N+注入扩散区之间以及N+注入扩散区的下方通过P阱区连通；
所述P+注入扩散区的下方设有PB层和/或ZP层，所述PB层和/或ZP层的两端和其上方的P+注入扩散区两端对齐设置。
进一步地，所述P+注入扩散区的下方设有PB层和ZP层，所述ZP层位于所述PB层的下方。
进一步地，P阱区上部间隔设有3个P+注入扩散区，相邻的两个P+注入扩散区之间设有3个N+注入扩散区；所述3个N+注入扩散区间隔设置，依次为第一至第三N+注入扩散区，第一、第三N+注入扩散区作为NMOS阵列结构的源极，第二N+注入扩散区作为NMOS阵列结构的漏极。
进一步地，对应第一与第二N+注入扩散区之间的上方以及第二与第三N+注入扩散区之间的上方均设有栅氧化层。
进一步地，所述栅氧化层上方设有多晶硅，所述多晶硅作为NMOS阵列结构的栅极。
进一步地，所述P+注入扩散区和N+注入扩散区的上方设有外氧化层，所述外氧化层内设有接触通孔，对应每个P+注入扩散区和N+注入扩散区的上方均设有接触通孔，金属布线穿过接触通孔设置，所述金属布线底端与所述P+注入扩散区或N+注入扩散区相接，所述金属布线顶端作为NMOS阵列结构的引线端。
进一步地，所述外氧化层内，对应每个多晶硅的上方均设有接触通孔，金属布线穿过接触通孔设置，所述金属布线底端与所述多晶硅相接，所述金属布线顶端作为NMOS阵列结构的栅极引线端。
进一步地，P+注入扩散区的引线端作为P型衬底引线端；P+注入扩散区的引线端和与其相邻的N+注入扩散区对应的引线端相连接。
2、一种上述高可靠性NMOS阵列结构的制备方法，在P型衬底上覆盖一层P阱区；在P阱区上部间隔形成多个P+注入扩散区，在所述P+注入扩散区的下方形成PB层或ZP层，所述多个P+注入扩散区同步加工作业完成；在相邻两个P+注入扩散区之间形成多个N+注入扩散区，所述多个N+注入扩散区同步加工作业完成。
进一步地，P阱区上部间隔形成3个P+注入扩散区，相邻的两个P+注入扩散区之间形成3个N+注入扩散区；所述3个N+注入扩散区间隔设置，依次为第一至第三N+注入扩散区；对应第一和第二N+注入扩散区之间的上方、第二和第三N+注入扩散区之间的上方均形成栅氧化层，所述栅氧化层上方设置多晶硅；所述栅氧化层同步加工作业完成。
本发明具有的有益效果：
本发明型衬底上方设有P阱区，P阱区上部间隔设有多个P+注入扩散区，相邻两个P+注入扩散区之间设有多个N+注入扩散区；所述P+注入扩散区的下方设有PB层或ZP层。本发明通过设置PB层、ZP层，可有效提高NMOS阵列的衬底浓度和结深，NMOS阵列的衬底浓度越浓，也就意味着寄生NPN的基区浓度越浓，基区电阻越小，寄生NPN就越不容易启动，从而有效提升NMOS功耗耐受力，提高工作可靠性。经实验证明，在同样大小的NMOS阵列下，本发明结构的功耗耐受能力比常规结构提高38.1％。
本发明P阱区上部间隔设有3个P+注入扩散区，相邻的两个P+注入扩散区之间设有3个N+注入扩散区；所述3个N+注入扩散区间隔设置，依次为第一至第三N+注入扩散区，第一、第三N+注入扩散区作为NMOS阵列结构的源极，第二N+注入扩散区作为NMOS阵列结构的漏极；对应第一、第二N+注入扩散区之间的上方、第二、第三N+注入扩散区之间的上方均设有栅氧化层，所述栅氧化层上方设有多晶硅，所述多晶硅作为NMOS阵列结构的栅极。本发明通过上述NMOS阵列结构设计，进一步保证有效提升NMOS功耗耐受力，提高工作可靠性。本发明的NMOS阵列和其它低压5V的CMOS有相同的栅氧厚度，因此工作电压完全相同，不需要通过其他额外的功能模块来转换，不会增加系统复杂度。
本发明制备方法为，在P型衬底上覆盖一层P阱区；同步作业，在P阱区上部间隔形成多个P+注入扩散区，在所述P+注入扩散区的下方形成PB层或ZP层；同步作业，在相邻两个P+注入扩散区之间形成多个N+注入扩散区。本发明制备方法可有效提高制备效率，而且不需要改变现有的生产设备，有利于节省成本。
附图说明
图1是本发明NMOS阵列的结构示意图。
具体实施方式
下面结合附图所示的实施方式对本发明进行详细说明，但应当说明的是，这些实施方式并非对本发明的限制，本领域普通技术人员根据这些实施方式所作的功能、方法、或者结构上的等效变换或替代，均属于本发明的保护范围之内。
实施例一：
高可靠性NMOS阵列结构
如图1所示，P型衬底1上方设有P阱区2，P阱区2上部间隔设有多个P+注入扩散区，相邻两个P+注入扩散区之间设有多个N+注入扩散区，所述N+注入扩散区之间以及N+注入扩散区的下方通过P阱区连通。本实施例中，P阱区2上部间隔设有3个P+注入扩散区，即，第一P+注入扩散区3，第二P+注入扩散区4，第三P+注入扩散区5。所述P+注入扩散区的下方设有PB层和/或ZP层，所述PB层和/或ZP层的两端和其上方的P+注入扩散区两端对齐设置。本实施例中，第一P+注入扩散区3，第二P+注入扩散区4，第三P+注入扩散区5的下方均设有用于横向双扩散MOS管的PB层17和用于稳压管的ZP层18，以增加NMOS阵列P型衬底的浓度，提高NMOS阵列的可靠性。PB层17和ZP层18，所述ZP层18位于所述PB层17的下方。PB层17、ZP层18的两端和其上方的P+注入扩散区两端对齐设置。
相邻的两个P+注入扩散区之间设有3个N+注入扩散区。以第一P+注入扩散区3、第二P+注入扩散区4之间为例，第一N+注入扩散区6，第二N+注入扩散区7、第三N+注入扩散区8依次间隔设置，第一、第三N+注入扩散区3、5作为NMOS阵列结构的源极，第二N+注入扩散区4作为NMOS阵列结构的漏极；上述N+注入扩散区之间以及N+注入扩散区的下方通过P阱区2连通。与第一P+注入扩散区3、第二P+注入扩散区4之间结构相同，第二P+注入扩散区4、第三P+注入扩散区5之间设有3个N+注入扩散区9、10、11，N+注入扩散区9、11为NMOS阵列结构的源极，N+注入扩散区10作为NMOS阵列结构的漏极。
以第一P+注入扩散区3、第二P+注入扩散区4之间为例，对应第一、第二N+注入扩散区6、7之间的上方、第二、第三N+注入扩散区4、5之间的上方均设有栅氧化层12，栅氧化层12厚度在
Figure BDA0002848465140000061
间，所述栅氧化层12上方设有多晶硅13，所述多晶硅13作为NMOS阵列结构的栅极。多晶硅13厚度在
Figure BDA0002848465140000062
间。所述栅氧化层12的两侧边缘分别与第一N+注入扩散区6的右侧边缘和第二N+注入扩散区7的左侧边缘实质对齐。与第一P+注入扩散区3、第二P+注入扩散区4之间结构相同，第二P+注入扩散区4、第三P+注入扩散区5之间同样设有栅氧化层12、多晶硅13，多晶硅13作为NMOS阵列结构的栅极。
上述P+注入扩散区和N+注入扩散区的上方设有外氧化层14，外氧化层14厚度为
Figure BDA0002848465140000063
所述外氧化层14内设有接触通孔15，对应每个P+注入扩散区和N+注入扩散区上方均设有接触通孔15，金属布线16穿过接触通孔设置，所述金属布线16底端与所述P+注入扩散区或N+注入扩散区相接(形成良好的欧姆接触)，所述金属布线16顶端作为NMOS阵列结构的引线端。外氧化层14内，对应每个多晶硅13的上方均设有接触通孔15，金属布线16穿过接触通孔15设置，所述金属布线16底端与所述多晶硅13相接(形成良好的欧姆接触)，所述金属布线顶端作为NMOS阵列结构的栅极引线端。
P+注入扩散区的引线端作为P型衬底引线端；P+注入扩散区的引线端和与其相邻的N+注入扩散区对应的引线端相连接。以第一P+注入扩散区3为例，第一P+注入扩散区3的引线端和与其相邻的第一N+注入扩散区6对应的引线端相连接。
实施例二：
高可靠性NMOS阵列结构
第一P+注入扩散区3，第二P+注入扩散区4，第三P+注入扩散区5的下方均设有用于横向双扩散MOS管的PB层17或用于稳压管的ZP层18。依据产品所用器件及成本方面的考虑，合理的选用PB层17或ZP层18。例如，产品中只用到NMOS阵列和横向双扩散MOS管，而未用稳压管，同时成本控制要求很严，NMOS阵列可靠性要求不是很高，则可以只用PB层17，不用ZP层18。这样就不会增加额外的光刻次数，从而维持流片成本不增加的前提下部分提高可靠性。同理，若产品只用到NMOS阵列和稳压管，则可以只用ZP层18，在流片成本不增加的前提下部分提高可靠性。
实施例二其余结构同实施例一的结构。
通过实验，比较采用常规结构制作的NMOS阵列和本发明制作的NMOS结构阵列的功耗(电压*电流)耐受点，测试数据如下：(以下每组测试样本总的NMOS管数量均为4个，每两个衬底引出端之间的NMOS管数量为2个，且每个NMOS管宽长比均为20/0.5)
Figure BDA0002848465140000071
通过上述实验数据发现，在使用相同数量NMOS管阵列中，常规结构可以耐受的功耗为7.6*0.47＝3.57(瓦特)；只加PB层的为8.0*0.53＝4.24(瓦特)，比常规结构提高18.8％；只加ZP层的为7.9*0.52＝4.11(瓦特)，比常规结构提高15.1％；PB层和ZP层都加的为8.5*0.58＝4.93(瓦特)，比常规结构提高38.1％。采用本发明技术制作的NMOS阵列，其功耗耐受点的提升，将极大地拓宽该NMOS阵列的产品应用范围，并提高其使用的安全可靠性。
实施例三：
高可靠性NMOS阵列结构的制备方法
在P型衬底上覆盖一层P阱区；在P阱区上部间隔形成多个P+注入扩散区，在所述P+注入扩散区的下方形成PB层或ZP层；所述多个P+注入扩散区同步加工作业完成，即在P阱区的上部同时光刻刻蚀出多个P+窗口，在每个P+窗口内同时进行P型杂质的注入和退火，这样就同时形成了多个P+注入扩散区。
在相邻两个P+注入扩散区之间形成多个N+注入扩散区，所述多个N+注入扩散区同步加工作业完成，即在P阱区上部相邻两个P+注入扩散区之间，同时光刻刻蚀出多个N+窗口，在每个N+窗口内同时进行N型杂质的注入和退火，这样就同时形成了多个N+注入扩散区。
P阱区上部间隔形成3个P+注入扩散区，相邻的两个P+注入扩散区之间形成3个N+注入扩散区；所述3个N+注入扩散区间隔设置，依次为第一至第三N+注入扩散区；对应第一和第二N+注入扩散区之间的上方、第二和第三N+注入扩散区之间的上方均形成栅氧化层，所述栅氧化层上方设有多晶硅，所述栅氧化层同步加工作业完成。即在同一次热氧化过程中，在第一和第二N+注入扩散区之间的上方、第二和第三N+注入扩散区之间的上方同时生长出栅氧化层。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。

Claims (10)

1.一种高可靠性NMOS阵列结构，包括P型衬底，所述P型衬底上方设有P阱区，其特征在于：
P阱区上部间隔设有多个P+注入扩散区，相邻两个P+注入扩散区之间设有多个N+注入扩散区，所述N+注入扩散区之间以及N+注入扩散区的下方通过P阱区连通；
所述P+注入扩散区的下方设有PB层和/或ZP层，所述PB层和/或ZP层的两端和其上方的P+注入扩散区两端对齐设置。
2.根据权利要求1所述的高可靠性NMOS阵列结构，其特征在于：所述P+注入扩散区的下方设有PB层和ZP层，所述ZP层位于所述PB层的下方。
3.根据权利要求1所述的高可靠性NMOS阵列结构，其特征在于：P阱区上部间隔设有3个P+注入扩散区，相邻的两个P+注入扩散区之间设有3个N+注入扩散区；所述3个N+注入扩散区间隔设置，依次为第一至第三N+注入扩散区，第一、第三N+注入扩散区作为NMOS阵列结构的源极，第二N+注入扩散区作为NMOS阵列结构的漏极。
4.根据权利要求3所述的高可靠性NMOS阵列结构，其特征在于：对应第一与第二N+注入扩散区之间的上方以及第二与第三N+注入扩散区之间的上方均设有栅氧化层。
5.根据权利要求4所述的高可靠性NMOS阵列结构，其特征在于：所述栅氧化层上方设有多晶硅，所述多晶硅作为NMOS阵列结构的栅极。
6.根据权利要求1所述的高可靠性NMOS阵列结构，其特征在于：所述P+注入扩散区和N+注入扩散区的上方设有外氧化层，所述外氧化层内设有接触通孔，对应每个P+注入扩散区和N+注入扩散区的上方均设有接触通孔，金属布线穿过接触通孔设置，所述金属布线底端与所述P+注入扩散区或N+注入扩散区相接，所述金属布线顶端作为NMOS阵列结构的引线端。
7.根据权利要求6所述的高可靠性NMOS阵列结构，其特征在于：所述外氧化层内，对应每个多晶硅的上方均设有接触通孔，金属布线穿过接触通孔设置，所述金属布线底端与所述多晶硅相接，所述金属布线顶端作为NMOS阵列结构的栅极引线端。
8.根据权利要求7所述的高可靠性NMOS阵列结构，其特征在于：P+注入扩散区的引线端作为P型衬底引线端；P+注入扩散区的引线端和与其相邻的N+注入扩散区对应的引线端相连接。
9.一种高可靠性NMOS阵列结构的制备方法，其特征在于，包括以下步骤：
在P型衬底上覆盖一层P阱区；
在P阱区上部间隔形成多个P+注入扩散区，在所述P+注入扩散区的下方形成PB层或ZP层，所述多个P+注入扩散区同步加工作业完成；
在相邻两个P+注入扩散区之间形成多个N+注入扩散区，所述多个N+注入扩散区同步加工作业完成。
10.根据权利要求9所述的制备方法，其特征在于，还包括以下步骤：
P阱区上部间隔形成3个P+注入扩散区，相邻的两个P+注入扩散区之间形成3个N+注入扩散区；所述3个N+注入扩散区间隔设置，依次为第一至第三N+注入扩散区；
对应第一和第二N+注入扩散区之间的上方、第二和第三N+注入扩散区之间的上方均形成栅氧化层，所述栅氧化层上方设置多晶硅；所述栅氧化层同步加工作业完成。
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US6323074B1 (en) * 2000-04-24 2001-11-27 Taiwan Semiconductor Manufacturing Company High voltage ESD protection device with very low snapback voltage by adding as a p+ diffusion and n-well to the NMOS drain
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