CN112631168A - FPGA-based deformation detector control circuit design method - Google Patents
FPGA-based deformation detector control circuit design method Download PDFInfo
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- CN112631168A CN112631168A CN202011427526.XA CN202011427526A CN112631168A CN 112631168 A CN112631168 A CN 112631168A CN 202011427526 A CN202011427526 A CN 202011427526A CN 112631168 A CN112631168 A CN 112631168A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B21/00—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
- G01B21/32—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring the deformation in a solid
Abstract
The invention discloses a design method of a deformation detector control circuit based on an FPGA (field programmable gate array), which comprises the following steps of: step S1, dividing the deformation detector control circuit into a plurality of basic modules according to the functional requirements; step S2, designing and inputting a plurality of basic modules to an EDA tool in a hardware description language by utilizing development software; step S3, compiling a plurality of basic modules into a logic connection netlist consisting of basic logic units by a hardware description language; and S4, mapping the logic connection netlist into specific FPGA devices, and generating a total design circuit by arranging and wiring among the FPGA devices. The method comprises the steps of detecting rod data acquisition, inclination angle sensor data acquisition, mileage wheel signal acquisition and data storage and uploading. The detection rods are large in number and high in sampling rate, the parallel acquisition is achieved, the efficiency and the accuracy of pipeline deformation detection are improved, the inheritance structure is applicable to use in any scene, and the adaptability is high.
Description
Technical Field
The invention relates to the technical field of pipeline detection, in particular to a design method of a deformation detector control circuit based on an FPGA (field programmable gate array).
Background
With the rapid development of national economy, the requirement on energy is more and more urgent. Oil and gas resources play a vital role in production and life as important energy sources. Among the transportation modes, pipeline transportation with high reliability and low transportation cost has played an increasingly important role in the transportation of petroleum resources and has become a main transportation channel of petroleum. However, as oil pipelines in China are continuously increased and oil pipelines are increasingly lengthened, accidents of the oil pipelines are increased, and therefore effective measures must be taken to prevent the pipelines from being invalid and reduce the accidents. Excessive deformation is one of the forms causing pipeline failure, so monitoring deformation of oil and gas pipelines becomes one of the research directions in the industry.
The traditional monitoring method for pipeline deformation needs to monitor the pipeline manually and periodically, although the method is easy to implement, the difficulty of processing the acquired signals is high, the technologies are easily influenced by the outside, most importantly, the real-time monitoring cannot be carried out, and therefore the actual deformation state of the pipeline is difficult to reflect.
In recent years, the monitoring of the deformation of the pipeline by the optical fiber can be used for measuring the strain in a long-distance, continuous and real-time online manner, and the method becomes a new method for monitoring the health of the pipeline, but the evaluation capability of the method is poor, the cost of the optical fiber is high, and the method is not suitable for monitoring the long-distance pipeline.
Disclosure of Invention
The invention aims to provide a design method of a deformation detector control circuit based on an FPGA (field programmable gate array), which aims to solve the technical problems of poor measurement precision and poor adaptability in the prior art.
In order to solve the technical problems, the invention specifically provides the following technical scheme:
a design method of a deformation detector control circuit based on an FPGA comprises the following steps:
step S1, dividing the deformation detector control circuit into a plurality of basic modules according to the functional requirements;
step S2, designing and inputting a plurality of basic modules to an EDA tool in a hardware description language by utilizing development software;
step S3, compiling a plurality of basic modules into a logic connection netlist consisting of basic logic units by a hardware description language;
s4, mapping the logic connection netlist into a specific FPGA device, and generating a total design circuit for layout and wiring among the FPGA devices;
and step S5, performing simulation on the total design circuit by using a simulation tool and board-level debugging to confirm the accuracy of the total design circuit.
As a preferred scheme of the present invention, the plurality of base modules include a detection lever sensor data acquisition module, an inclination sensor data acquisition module, a mileage wheel signal acquisition module, an FPGA chip module, and a storage module that stores measurement data acquired by the detection lever sensor data acquisition module and the inclination sensor data acquisition module.
AS a preferred scheme of the present invention, the detection rod sensor data acquisition module adopts a detection rod sensor chip with model AS5048A, the detection sensor chip and the FPGA chip module adopt SPI bus protocol for communication to implement command control and data interaction, and the specific design method is AS follows:
selecting and setting 10 groups of detection sensor chips as a slave mode, and selecting and setting one group of FPGA chip modules as a host mode;
connecting a group of FPGA chip modules with 10 groups of detection sensor chips through 10 SPI interfaces;
and under the action of the control command of the group of FPGA chip modules, reading and storing the measurement data of the 10 groups of detection sensor chips through 10 SPI interfaces.
As a preferred scheme of the present invention, the mileage wheel signal acquisition module is configured to acquire a square-wave mileage wheel signal generated during the rotation of a mileage wheel in a pipeline, and the mileage wheel signal is used to trigger 10 sets of detection sensor chips to acquire measurement data in parallel.
As a preferred scheme of the present invention, the tilt sensor data acquisition module employs a tilt sensor chip with model number VG200, the tilt sensor chip and the FPGA chip module communicate by using RS232 serial protocol to implement instruction control and data interaction, the RS232 serial protocol represents a universal asynchronous transceiver transmitter in a protocol of a link layer, and the specific design manner is as follows:
setting the output frequency of a baud rate generator module to be 16 times of the 9600 baud rate of the serial port communication rate default value of the tilt sensor chip, namely 9600 multiplied by 16 equals to 153.6 kHz;
setting the data transmission frequency of a serial port transmission module to transmit one bit per 16 baud rate clocks;
carrying out maximum likelihood judgment on a data start bit and an effective data bit received by a serial port receiving module, starting sampling by using a first low level appearing at a receiving port, judging as a data frame start bit when a low level sampling value exceeds 8 times in continuous 16 times of sampling, and then judging as a data bit every 16 times of sampling judgment results until 8 effective data bits are received;
and instantiating a baud rate generator module, a serial port sending module and a serial port receiving module to obtain a top-level module for performing operation logic control among the modules.
As a preferred scheme of the present invention, the storage module adopts a FLASH chip with a model number of K9NBG08U5A, and the FLASH chip and the FPGA chip module complete access operations of storing the measurement data into the FLASH chip and reading out the measurement data from the FLASH chip through a FLASH dedicated controller module.
As a preferable scheme of the present invention, the present invention further includes the asynchronous FIFO communication module and a USB bus interface module, and the asynchronous FIFO communication module is used as data buffering between different clock domain modules in the process of storing the measurement data in the FLASH.
As a preferred scheme of the present invention, the USB bus interface module adopts an interface chip with a model CH372, and the interface chip and the FPGA chip module complete data communication between a local end program, a computer-side driver, and a computer-side application program through an interface chip controller.
In a preferred embodiment of the present invention, the hardware description language is Verilog HDL.
As a preferred scheme of the present invention, the FPGA device is a control device formed by integrally packaging the SPI interface, the RS232 serial port, the asynchronous FIFO, the FLASH controller, and the USB controller.
Compared with the prior art, the invention has the following beneficial effects:
the method comprises the steps of detecting rod data acquisition, inclination angle sensor data acquisition, mileage wheel signal acquisition and data storage and uploading. The detection rods are large in number and high in sampling rate, the parallel acquisition is achieved, the efficiency and the accuracy of pipeline deformation detection are improved, the inheritance structure is applicable to use in any scene, and the adaptability is high.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.
FIG. 1 is a flow chart of a method for designing a control circuit of a strain detector according to an embodiment of the present invention;
FIG. 2 is a package diagram of an SPI interface according to an embodiment of the present invention;
fig. 3 is a block diagram of an RS232 serial port according to an embodiment of the present invention;
FIG. 4 is a simple asynchronous circuit diagram provided by an embodiment of the present invention;
FIG. 5 is a diagram of an improved asynchronous circuit provided by an embodiment of the present invention;
FIG. 6 is a diagram of an application operating page on a computer side of a USB device according to an embodiment of the present invention;
fig. 7 is a flowchart of measurement data acquisition according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the invention provides a method for designing a control circuit of a deformation detector based on an FPGA, comprising the following steps:
step S1, dividing the deformation detector control circuit into a plurality of basic modules according to the functional requirements;
step S2, designing and inputting a plurality of basic modules to an EDA tool in a hardware description language by utilizing development software;
step S3, compiling a plurality of basic modules into a logic connection netlist consisting of basic logic units by a hardware description language;
s4, mapping the logic connection netlist into a specific FPGA device, and generating a total design circuit for layout and wiring among the FPGA devices;
and step S5, performing simulation on the total design circuit by using a simulation tool and board-level debugging to confirm the accuracy of the total design circuit.
The plurality of basic modules comprise a detection rod sensor data acquisition module, an inclination angle sensor data acquisition module, a mileage wheel signal acquisition module, an FPGA chip module and a storage module for storing measurement data acquired by the detection rod sensor data acquisition module and the inclination angle sensor data acquisition module.
In this embodiment, the utility model is AS 5048A's test bar sensor chip is adopted to test bar sensor data acquisition module, and test sensor chip and FPGA chip module adopt SPI bus protocol to communicate and realize command control and data interaction, and concrete design does:
v1, selecting and setting 10 groups of detection sensor chips as a slave mode, and selecting one group and setting the FPGA chip module as a host mode;
v2, connecting a group of FPGA chip modules with 10 groups of detection sensor chips through 10 SPI interfaces;
v3, under the control command of a group of FPGA chip modules, reading and storing the measurement data of 10 groups of detection sensor chips through 10 SPI interfaces.
As shown in fig. 2, the pins of the SPI interface package are defined as follows: clk is an external input clock signal and is provided by an FPGA; rst _ n is a reset signal, and when the reset signal is at a low level, the system restores the initial state; SPI _ cmd is an SPI (serial peripheral interface) data transmission control signal; the tx _ data is data to be transmitted; spi _ clk, spi _ cs, spi _ mosi and spi _ miso are a serial clock signal, a chip select signal, a master output slave input and a master input slave output signal respectively; the rx _ data is received data obtained by performing serial-parallel conversion on the spi _ miso signal; tx _ done and rx _ done are indication signals for data transmission completion and data reception completion, respectively.
And a main state machine of the FPGA chip module controls the running state of the whole data acquisition. When the master state machine issues a read control signal, the AS5048A read instruction is also stored in the register tx _ data. The FPGA serves as a host to provide clock signals and chip selection signals for the slave. When the slave AS5048A is selected and a clock signal arrives, a read command is received. At the same time of the next read command, the AS5048A stores the measurement data in the SPI interface module buffer bit-by-bit on the falling edge of the serial clock signal until the clock stops and waits for the next read command. And after the receiving is finished, the measured value after the serial-parallel conversion is stored into a register rx _ data.
The mileage wheel signal acquisition module is used for acquiring square-wave mileage wheel signals generated in the rotation process of the mileage wheel in the pipeline, and the mileage wheel signals are used for triggering 10 groups of detection sensor chips to acquire measurement data in parallel.
And (3) acquiring data in parallel by 60 detection rods of 10 groups of detection sensor chips under the triggering of a mile wheel signal, namely when the rising edge of a mile wheel square wave signal comes, the 10 SPI interfaces start to operate simultaneously. In the process, synchronization of 10 SPI interface clock signals and chip selection enabling signals needs to be ensured, and after each complete acquisition cycle is completed, the SPI clock and the chip selection enabling signals return to an invalid state at the same time to wait for the arrival of the next acquisition trigger signal. Meanwhile, each SPI interface outputs a data receiving completion signal to ensure that 10 interfaces all receive handshake signals which finish giving data flow to the next module
As shown in fig. 3, the tilt sensor data acquisition module adopts a tilt sensor chip with model VG200, the tilt sensor chip and the FPGA chip module adopt RS232 serial protocol to communicate to realize instruction control and data interaction, the RS232 serial protocol represents a universal asynchronous transceiver transmitter in the protocol of the link layer, and the specific design mode is as follows:
t1, setting the output frequency of the baud rate generator module to be 16 times of the default 9600 baud rate of the serial communication rate of the tilt sensor chip, namely 9600 × 16 ═ 153.6 kHz;
t2, setting the data sending frequency of the serial port sending module to be one bit sent by every 16 baud rate clocks;
t3, carrying out maximum likelihood judgment on the data start bit and the effective data bit received by the serial port receiving module, starting sampling with the first low level appearing at the receiving port, judging that the data frame start bit is received when the low level sampling value exceeds 8 times in continuous 16 times of sampling, and then judging that the result of sampling judgment every 16 times is a data bit until 8 effective data bits are received;
t4, instantiating baud rate generator module, serial port sending module and serial port receiving module at the same time to obtain the top module for controlling the operation logic between modules, when the serial port sends data, the top module provides sending command and sending data for the sending module, receives the completion signal from the sending module, and controls the sending of the subsequent data stream; in serial port receiving, 8-bit parallel data from a receiving module and a handshake signal are received.
The storage module adopts a FLASH chip with the model number of K9NBG08U5A, and the FLASH chip and the FPGA chip module complete the access operation of storing the measurement data into the FLASH chip and reading the measurement data from the FLASH chip through a FLASH special controller module.
Due to the particularity of the FLASH chip, a part of bad blocks which cannot be operated exist when the chip leaves a factory. In the using process, repeated reading, writing and erasing operations can also cause new bad blocks to appear, and the embodiment designs a relatively simple and convenient bad block management method: only recording the address of a bad block in the chip, establishing a bad block address table, and storing information in the table to the position of a first page of a first block in the FLASH chip; and matching the current address with the bad block address table during the write operation, and if the current position is a bad block, sequentially changing the current address into the next block address, wherein the write operation is matched with the bad block address in the same way.
The device also comprises an asynchronous FIFO communication module and a USB bus interface module, wherein the asynchronous FIFO communication module is used for buffering data among different clock domain modules in the process of storing the measurement data into the FLASH.
Asynchronous FIFO has the characteristics of high speed, good reliability and the like, and can quickly and conveniently transmit real-time data between two different clock systems.
In asynchronous circuits, metastability, although unavoidable, can be taken to reduce the probability of occurrence to an acceptable level. As shown in fig. 4, which is a common simple asynchronous circuit, clk1 is asynchronous with the clk2 bit circuit. Flip-flop F2 samples the output of flip-flop F1, when clk1 is closer to the rising edge of clk2, if data1 changes in value, clk2 will sample a changing data and the output of flip-flop F2 will be an indeterminate value. Improved asynchronous circuit as shown in fig. 5, E2 and E3 constitute a synchronizer for latching the input signals of different clock domains to reach steady state as much as possible. data1 is unstable as input of E2, and data2 is likely to be stable after waiting for one clock cycle, so that flip-flop E3 samples data2 with a certain value, and E3 outputs a stable value. This measure greatly reduces the possibility of data2 being metastable with only a very small probability.
The 2048 × 8 asynchronous FIFO of this embodiment is used to complete interface data synchronization. The input end comprises a read clock signal, a write clock signal, a reset signal, a parallel 8-bit data input and an enable signal for controlling reading and writing; the output terminal comprises parallel 8-bit data output and FIFO empty and full signals.
The USB bus interface module adopts an interface chip with the model of CH372, a bottom layer protocol in USB communication is built in the interface chip of the CH372, a standard USB enumeration process is automatically completed, the control logic of a USB local end is simplified, and the interface chip and the FPGA chip module complete data communication among a local end program, a computer end drive and a computer end application program through an interface chip controller.
The purpose of the CH372 controller is to modularize the USB data communication function, encapsulate the instruction of the CH372 in a module, and control the USB interface through a few ports by the main state machine, thereby reducing the state quantity of the main state machine and the complexity of the main state machine.
The USB device computer-side application program is developed by using an MFC platform in a Visual C + +6.0 environment, and the application layer interface is a function application-oriented API provided by a CH372 dynamic link library DLL and comprises a device management API, a data transmission API and an interrupt processing API. Wherein, the device API mainly uses CH375Opendevice, CH375CloseDevice, CH375GetDeviceDescr, etc.; the data transmission API mainly uses CH375ReadData, CH375WriteData and the like; the interrupt API uses primarily CH375 readlner. As shown in fig. 6, the program contains four parts, device operation, endpoint 2 download, endpoint 2 upload, and endpoint 1 upload. The measured data of the pipeline detection equipment is uploaded and then stored in a computer in the form of a text file
The hardware description language is Verilog HDL.
The FPGA device is a control device formed by integrally packaging an SPI interface, an RS232 serial port, an asynchronous FIFO, a FLASH controller and a USB controller.
As shown in fig. 7, the specific flow of measurement data acquisition is that the odometer wheel outputs a signal as a trigger signal for data acquisition. And in the rotation process of the mileage wheel, a data acquisition cycle is performed every 17 falling edge trigger signals are generated, and the data acquisition cycle comprises 17 times of data acquisition of the detection rod sensor and 1 time of data acquisition of the inclination angle sensor. The measurement data collected each cycle is filled once in a FIFO of capacity 2048 bytes. When the FIFO full signal is effective, the FIFO read enable signal is triggered immediately, and the data are read out in sequence. The FIFO read clock and the FLASH write clock have the same frequency, and one page of the FLASH can be fully written when all data are read. Because the time required for writing FLASH to a page is very short, the data can be stored before the next cycle. And after one data acquisition cycle is completed, continuing the cycle process until the end point of the oil-gas pipeline to be detected is reached.
The method comprises the steps of detecting rod data acquisition, inclination angle sensor data acquisition, mileage wheel signal acquisition and data storage and uploading. The detection rods are large in number and high in sampling rate, the parallel acquisition is achieved, the efficiency and the accuracy of pipeline deformation detection are improved, the inheritance structure is applicable to use in any scene, and the adaptability is high.
The above embodiments are only exemplary embodiments of the present application, and are not intended to limit the present application, and the protection scope of the present application is defined by the claims. Various modifications and equivalents may be made by those skilled in the art within the spirit and scope of the present application and such modifications and equivalents should also be considered to be within the scope of the present application.
Claims (10)
1. A design method of a deformation detector control circuit based on an FPGA is characterized by comprising the following steps:
step S1, dividing the deformation detector control circuit into a plurality of basic modules according to the functional requirements;
step S2, designing and inputting a plurality of basic modules to an EDA tool in a hardware description language by utilizing development software;
step S3, compiling a plurality of basic modules into a logic connection netlist consisting of basic logic units by a hardware description language;
s4, mapping the logic connection netlist into a specific FPGA device, and generating a total design circuit for layout and wiring among the FPGA devices;
and step S5, performing simulation on the total design circuit by using a simulation tool and board-level debugging to confirm the accuracy of the total design circuit.
2. The method for designing the control circuit of the FPGA-based deformation detector according to claim 1, wherein the plurality of base modules comprise a detection rod sensor data acquisition module, a tilt sensor data acquisition module, a mile wheel signal acquisition module, an FPGA chip module, and a storage module for storing measurement data acquired by the detection rod sensor data acquisition module and the tilt sensor data acquisition module.
3. The design method of the control circuit of the FPGA-based deformation detector, according to claim 2, characterized in that the data acquisition module of the detection rod sensor adopts a detection rod sensor chip with model AS5048A, the detection sensor chip and the FPGA chip module adopt SPI bus protocol for communication to realize command control and data interaction, and the specific design method is AS follows:
selecting and setting 10 groups of detection sensor chips as a slave mode, and selecting and setting one group of FPGA chip modules as a host mode;
connecting a group of FPGA chip modules with 10 groups of detection sensor chips through 10 SPI interfaces;
and under the action of the control command of the group of FPGA chip modules, reading and storing the measurement data of the 10 groups of detection sensor chips through 10 SPI interfaces.
4. The design method of the control circuit of the FPGA-based deformation detector according to claim 3, wherein the odometer wheel signal acquisition module is used for acquiring square-wave odometer wheel signals generated in the rotation process of an odometer wheel in a pipeline, and the odometer wheel signals are used for triggering 10 groups of detection sensor chips to acquire measurement data in parallel.
5. The method for designing the control circuit of the FPGA-based deformation detector according to claim 2, wherein the tilt sensor data acquisition module adopts a tilt sensor chip with a model number of VG200, the tilt sensor chip and the FPGA chip module adopt an RS232 serial port protocol for communication to realize instruction control and data interaction, the RS232 serial port protocol is represented as a universal asynchronous transceiver in a link layer, and the specific design mode is as follows:
setting the output frequency of a baud rate generator module to be 16 times of the 9600 baud rate of the serial port communication rate default value of the tilt sensor chip, namely 9600 multiplied by 16 equals to 153.6 kHz;
setting the data transmission frequency of a serial port transmission module to transmit one bit per 16 baud rate clocks;
carrying out maximum likelihood judgment on a data start bit and an effective data bit received by a serial port receiving module, starting sampling by using a first low level appearing at a receiving port, judging as a data frame start bit when a low level sampling value exceeds 8 times in continuous 16 times of sampling, and then judging as a data bit every 16 times of sampling judgment results until 8 effective data bits are received;
and instantiating a baud rate generator module, a serial port sending module and a serial port receiving module to obtain a top-level module for performing operation logic control among the modules.
6. The method for designing the control circuit of the FPGA-based deformation detector according to claim 2, wherein the storage module adopts a FLASH chip with the model number K9NBG08U5A, and the FLASH chip and the FPGA chip module complete the access operation of storing the measurement data into the FLASH chip and reading the measurement data out of the FLASH chip through a FLASH-dedicated controller module.
7. The design method of the control circuit of the FPGA-based deformation detector according to claim 2, further comprising the asynchronous FIFO communication module and a USB bus interface module, wherein the asynchronous FIFO communication module is used as a data buffer between different clock domain modules in the process of storing the measurement data into FLASH.
8. The method as claimed in claim 7, wherein the USB bus interface module is an interface chip with a model CH372, and the interface chip and the FPGA chip module complete data communication between a local side program, a computer side driver and a computer side application program through an interface chip controller.
9. The design method of the FPGA-based deformation detector control circuit according to claim 1, wherein the hardware description language is Verilog HDL.
10. The method for designing the control circuit of the FPGA-based deformation detector according to claim 2, wherein the FPGA device is a control device formed by integrally packaging the SPI interface, the RS232 serial port, the asynchronous FIFO, the FLASH controller and the USB controller.
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Application publication date: 20210409 |