CN112614901B - Gallium arsenide multi-junction solar cell chip and preparation method thereof - Google Patents
Gallium arsenide multi-junction solar cell chip and preparation method thereof Download PDFInfo
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 title claims abstract description 44
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 44
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- 238000005260 corrosion Methods 0.000 claims description 11
- 230000007797 corrosion Effects 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 8
- 230000003667 anti-reflective effect Effects 0.000 description 8
- 238000003466 welding Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010521 absorption reaction Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000001579 optical reflectometry Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003760 hair shine Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
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Abstract
The invention discloses a gallium arsenide multi-junction solar cell chip and a preparation method thereof, and the gallium arsenide multi-junction solar cell chip comprises a substrate, a cell functional layer, an antireflection layer, an ohmic contact layer and a front electrode, wherein the substrate, the cell functional layer and the antireflection layer are sequentially stacked, an exposed opening is formed in the antireflection layer, a back electrode is arranged on the back of the substrate, the ohmic contact layer is arranged on the cell functional layer and positioned at the exposed opening, the front electrode is connected with the ohmic contact layer and exposed outside the antireflection layer, the antireflection layer cannot cover the front electrode, the front electrode can normally reflect light, the temperature of the front electrode is relatively reduced, the front electrode can be better welded with an external component, and the cell conversion efficiency is improved.
Description
Technical Field
The invention relates to the technical field of battery manufacturing, in particular to a gallium arsenide multi-junction solar battery chip and a preparation method thereof.
Background
Traditional gallium arsenide multijunction solar cell, after preparing the battery chip, can cover antireflection layer at the front of battery functional layer, reduce the reflection of focusing, improve the absorption efficiency that the battery functional layer was set light, however, when producing antireflection layer, preparation technology can make antireflection layer on traditional gallium arsenide multijunction solar cell cover together with the front electrode in the past, lead to the reflectivity on the front electrode to descend, the light shines and turns into the heat on the front electrode, the temperature of electrode has been improved, the conversion efficiency of battery has been reduced. When the front electrode is welded with the outside, the antireflection film can obstruct welding, the antireflection film on the welding area of the front electrode needs to be peeled before welding, and poor welding performance or poor reliability can be easily caused if the antireflection film is not completely peeled.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides the gallium arsenide multi-junction solar cell chip, the front electrode is exposed outside the antireflection layer, the temperature on the front electrode is reduced, and the cell conversion efficiency is improved.
The invention also provides a preparation method of the gallium arsenide multi-junction solar cell chip, so that the front electrode of a finished cell product is exposed outside the antireflection layer, the cell conversion efficiency is improved, and the production is rapid and efficient.
According to a first aspect embodiment of the invention, a gallium arsenide multijunction solar cell chip comprises: the battery comprises a substrate, a battery function layer and an antireflection layer which are sequentially stacked, wherein an exposed opening is formed in the antireflection layer, and a back electrode is arranged on the back of the substrate; an ohmic contact layer disposed on the battery functional layer and at the bare spot; and the front electrode is connected with the ohmic contact layer and is exposed outside the antireflection layer.
The gallium arsenide multi-junction solar cell chip provided by the embodiment of the invention at least has the following beneficial effects:
according to the gallium arsenide multi-junction solar cell chip, the antireflection layer is arranged on the cell functional layer, the antireflection film can reduce the reflection of the surface of the cell functional layer to light, the absorption capacity of the cell functional layer to the light is improved, the ohmic contact layer is arranged at the exposed opening, the front electrode penetrates through the exposed opening to be connected with the ohmic contact layer, so that the front electrode can be normally in conductive connection with the cell functional layer, the antireflection layer cannot cover the front electrode, the front electrode can normally reflect the light, the temperature of the front electrode is relatively reduced, and the conversion efficiency of the cell is improved.
According to some embodiments of the invention, the front electrode further comprises a main gate electrode disposed on the anti-reflection layer and a plurality of fine gate electrodes disposed on the ohmic contact layer, the plurality of fine gate electrodes being connected to the main gate electrode.
According to some embodiments of the invention, a support layer is disposed between the anti-reflective layer and the cell functional layer, and the main gate electrode is located above the support layer.
According to some embodiments of the invention, the support layer and the ohmic contact layer are equal in thickness.
According to some embodiments of the invention, the battery function layer comprises a Ge sub-battery, a GaAs sub-battery, and a GaInP sub-battery, which are sequentially stacked, the Ge sub-battery is disposed on the substrate, and the anti-reflection layer is disposed on the GaInP sub-battery.
According to a second aspect of the invention, the preparation method of the gallium arsenide multi-junction solar cell chip comprises the following steps: sequentially generating a battery function layer and an ohmic contact layer on a substrate; defining an electrode area on the ohmic contact layer by adopting a photoetching process; removing the ohmic contact layer outside the electrode region by adopting an etching process; forming an antireflection layer on the battery functional layer and the surface of the ohmic contact layer after the corrosion process by adopting an evaporation process; defining an electrode area on the antireflection layer by adopting a photoetching process; removing the antireflection layer in the electrode area by adopting a corrosion process; and preparing a front electrode, wherein the front electrode is connected with the ohmic contact layer and is exposed outside the antireflection layer.
The preparation method of the gallium arsenide multi-junction solar cell chip according to the embodiment of the invention at least has the following beneficial effects:
according to the preparation method of the gallium arsenide multi-junction solar cell chip, after a cell functional layer and an ohmic contact layer are generated, a photoetching process is adopted to define a divided electrode area, the ohmic contact layer outside the electrode area is corroded, an antireflection layer is evaporated, the electrode area is defined on the antireflection layer again at the moment, the antireflection layer in the electrode area is removed through the corrosion process, and then the front electrode is prepared, so that the front electrode can be tightly connected with the ohmic contact layer and is exposed outside the antireflection layer, the antireflection layer can reduce the light reflectivity, more light rays are collected and converted by the cell functional layer, the design improves the cell conversion efficiency, the front electrode can be better welded with an external component, and the production is fast and efficient.
According to some embodiments of the invention, the front electrode further comprises a main gate electrode and a plurality of fine gate electrodes; defining an electrode area on the ohmic contact layer by adopting a photoetching process, wherein the electrode area comprises a main gate electrode area and a fine gate electrode area, and removing the ohmic contact layer outside the main gate electrode area and the fine gate electrode area by adopting an etching process; defining a thin gate electrode area on the antireflection layer by adopting a photoetching process, and then removing the antireflection layer in the thin gate electrode area by adopting a corrosion process, wherein the ohmic contact layer at the main gate electrode area is used as a supporting layer; preparing the main grid electrode and the fine grid electrode, wherein the fine grid electrode is connected with the ohmic contact layer and exposed outside the antireflection layer, the main grid electrode is arranged on the antireflection layer and positioned above the supporting layer, and the fine grid electrode is connected with the main grid electrode.
According to some embodiments of the invention, the substrate is a Ge substrate, the battery function layer comprises a Ge subcell, a GaAs subcell, a GaInP subcell, and the ohmic contact layer is a GaAs ohmic contact layer;
according to some embodiments of the invention, a Ge sub-cell, a GaAs sub-cell, a GaInP sub-cell, and a GaAs ohmic contact layer are sequentially formed on a Ge substrate using MOCVD.
According to some embodiments of the invention, the anti-reflective layer in the electrode region is removed using a hydrofluoric acid etch.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic cross-sectional view of one embodiment of a GaAs multijunction solar cell chip of the present invention;
FIG. 2 is a top view of one embodiment of a GaAs multijunction solar cell chip of the present invention;
fig. 3 is a process flow diagram of one embodiment of the method for manufacturing a gallium arsenide multi-junction solar cell chip according to the present invention.
Reference numerals:
the solar cell comprises a substrate 100, a cell functional layer 200, a Ge sub-cell 210, a GaAs sub-cell 220, a GaInP sub-cell 230, an antireflection layer 300, a bare opening 310, a front electrode 400, a main gate electrode 410, a fine gate electrode 420, an ohmic contact layer 500, a support layer 510 and a back electrode 600.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the positional or orientational descriptions referred to, for example, the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., are based on the positional or orientational relationships shown in the drawings and are for convenience of description and simplicity of description only, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, it should be noted that unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
As shown in fig. 1 to 3, a gallium arsenide multi-junction solar cell chip according to an embodiment of the first aspect of the present invention includes a substrate 100, a battery functional layer 200, an anti-reflection layer 300, an ohmic contact layer 500, and a front electrode 400, where the substrate 100, the battery functional layer 200, and the anti-reflection layer 300 are sequentially stacked, an exposure opening 310 is disposed on the anti-reflection layer 300, a back electrode 600 is disposed on a back of the substrate 100, the ohmic contact layer 500 is disposed on the battery functional layer 200 and located at the exposure opening 310, and the front electrode 400 is connected to the ohmic contact layer 500 and exposed outside the anti-reflection layer 300.
In some embodiments of the present invention, the battery function layer 200 includes a Ge subcell 210, a GaAs subcell 220, and a GalnP subcell 230 stacked in sequence, the Ge subcell 210 is disposed on the substrate 100, the antireflection layer 300 is disposed on the GaInP subcell 230, the substrate 100 is a Ge substrate, and the ohmic contact layer 500 is a GaAs ohmic contact layer.
According to the gallium arsenide multi-junction solar cell chip, the antireflection layer 300 is arranged on the cell functional layer 200, reflection of the surface of the cell functional layer 200 to light can be reduced through the antireflection film, the absorption capacity of the cell functional layer 200 to the light is improved, the ohmic contact layer 500 is arranged at the exposed opening 310, the front electrode 400 penetrates through the exposed opening 310 and is connected with the ohmic contact layer 500, therefore, the front electrode 400 can be normally and electrically connected with the cell functional layer 200, the antireflection layer 300 cannot cover the front electrode 400, the front electrode 400 can normally reflect the light, the temperature of the front electrode 400 is relatively reduced, the front electrode 400 can be better welded with external components, and the cell conversion efficiency is improved.
In some embodiments of the present invention, as shown in fig. 2, the front electrode 400 further includes a main grid electrode 410 and a plurality of fine grid electrodes 420, the main grid electrode 410 is disposed on the anti-reflection layer 300, the fine grid electrodes 420 are disposed on the ohmic contact layer 500, the plurality of fine grid electrodes 420 are connected to the main grid electrode 410, specifically, the fine grid electrodes 420 are gathered on the main grid electrode 410, the fine grid electrodes 420 and the main grid electrode 410 are both used for welding with an external component to achieve conductive connection, while the main grid electrode 410 has a larger area and can satisfy more or larger welding points, while the fine grid electrodes 420 need to be conductively connected to the battery functional layer 200 through the ohmic contact layer 500 while being welded with the external component, and the main grid electrode 410 does not need to be conductively connected to the battery functional layer 200 through the ohmic contact layer 500, so that the anti-reflection layer 300 does not need to be provided with the exposed opening 310 at the main grid electrode 410, the main grid electrode 410 is directly arranged on the antireflection layer 300, so that the influence caused by electric leakage of the solar cell functional layer 200 under the main grid electrode 410 can be reduced to a certain extent.
In some embodiments of the present invention, as shown in fig. 1, a support layer 510 is disposed between the anti-reflective layer 300 and the battery functional layer 200, the main gate electrode 410 is located above the support layer 510, the support layer 510 may be made of the same material as the ohmic contact layer 500, the support layer 510 serves to support the main gate electrode 410 by a certain height, and since the thickness of the anti-reflective layer 300 is negligible and the fine gate electrode 420 is supported by the ohmic contact layer 500, the support layer 510 may enable the main gate electrode 410 and the fine gate electrode 420 to be substantially close in height, thereby facilitating the connection between the main gate electrode 410 and the fine gate electrode 420.
Further, the thickness of the support layer 510 and the ohmic contact layer 500 may be equal, thereby further facilitating the connection of the main gate electrode 410 and the fine gate electrode 420.
A method for manufacturing a gallium arsenide multi-junction solar cell chip according to an embodiment of the second aspect of the present invention, as shown in fig. 1 to 3, includes the following steps: sequentially forming a battery function layer 200 and an ohmic contact layer 500 on a substrate 100; defining an electrode region on the ohmic contact layer 500 by using a photolithography process; removing the ohmic contact layer 500 outside the electrode region by using an etching process; forming an antireflection layer 300 on the surfaces of the battery function layer 200 and the ohmic contact layer 500 after the corrosion process by adopting an ion-assisted electron beam evaporation process; defining an electrode region on the anti-reflection layer 300 by using a photolithography process; removing the anti-reflection layer 300 in the electrode region by using a corrosion process; the front electrode 400 is prepared, and the front electrode 400 is connected to the ohmic contact layer 500 and exposed outside the anti-reflective layer 300.
The invention relates to a preparation method of a gallium arsenide multijunction solar cell chip, after a cell functional layer 200 and an ohmic contact layer 500 are generated, a photoetching process is adopted to define a divided electrode area, the ohmic contact layer 500 outside the electrode area is corroded, an antireflection layer 300 is evaporated, at the moment, an electrode area is defined on the antireflection layer 300 again, the antireflection layer 300 in the electrode area is removed by a corrosion process, and a front electrode 400 is prepared, so that the front electrode 400 can be tightly connected with the ohmic contact layer 500 and is exposed outside the antireflection layer 300, the antireflection layer 300 can reduce the light reflectivity, more light is collected and converted by the cell functional layer 200, the design improves the cell conversion efficiency, the production is rapid and high-efficient, in the preparation process, the front electrode 400 is not contacted with the antireflection layer 300 at all, the antireflection layer 300 can not cause any influence on the welding process on the front electrode 400, the front electrode 400 can be better welded with an external member.
The front electrode 400 further includes a main gate electrode 410 and a plurality of fine gate electrodes 420; defining an electrode area on the ohmic contact layer 500 by adopting a photoetching process, wherein the electrode area comprises a main gate electrode 410 area and a fine gate electrode 420 area, and removing the ohmic contact layer 500 outside the main gate electrode 410 area and the fine gate electrode 420 area by adopting an etching process; defining a fine gate electrode 420 area on the anti-reflection layer 300 by adopting a photoetching process, and then removing the anti-reflection layer 300 in the fine gate electrode 420 area by adopting an etching process, wherein the ohmic contact layer 500 at the main gate electrode 410 area is used as a supporting layer 510; preparing a main gate electrode 410 and a fine gate electrode 420, the fine gate electrode 420 being connected to the ohmic contact layer 500 and exposed outside the anti-reflective layer 300, the main gate electrode 410 being disposed on the anti-reflective layer 300 and above the support layer 510, the fine gate electrode 420 being connected to the main gate electrode 410.
Therefore, the support layer 510 mated with the main gate electrode 410 can be formed in the same process as the ohmic contact layer 500 with the fine gate electrode 420, so that the main gate electrode 410 and the fine gate electrode 420 are at the same height for easy connection.
Specifically, the substrate 100 is a Ge substrate, the battery function layer 200 includes a Ge subcell 210, a GaAs subcell 220, and a GalnP subcell 230, and the ohmic contact layer 500 is a GaAs ohmic contact layer;
in some embodiments of the present invention, MOCVD is used to sequentially generate a Ge sub-cell 210, a GaAs sub-cell 220, a GaInP sub-cell 230, and a GaAs ohmic contact layer on a Ge substrate.
In some embodiments of the present invention, the anti-reflective layer 300 in the electrode region is removed using a hydrofluoric acid etch.
After the primary cell chip is manufactured, the finished gallium arsenide multi-junction solar cell chip can be formed through annealing, cutting and side wall passivation.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (7)
1. A gallium arsenide multi-junction solar cell chip, comprising:
a substrate, a battery function layer and an antireflection layer which are sequentially stacked,
an exposed opening is formed in the antireflection layer, and a back electrode is arranged on the back of the substrate;
an ohmic contact layer disposed on the battery functional layer and at the bare spot;
the front electrode is connected with the ohmic contact layer and is exposed outside the antireflection layer;
the front electrode further comprises a main grid electrode and a plurality of fine grid electrodes, the main grid electrode is arranged on the antireflection layer, the fine grid electrodes are arranged on the ohmic contact layer, and the fine grid electrodes are connected with the main grid electrode;
and a supporting layer is arranged between the antireflection layer and the battery functional layer, and the main grid electrode is positioned above the supporting layer.
2. The gallium arsenide multijunction solar cell chip of claim 1, wherein: the thickness of the support layer is equal to that of the ohmic contact layer.
3. The gallium arsenide multijunction solar cell chip of claim 1, wherein: the battery function layer comprises a Ge sub battery, a GaAs sub battery and a GaInP sub battery which are sequentially stacked, the Ge sub battery is arranged on the substrate, and the antireflection layer is arranged on the GaInP sub battery.
4. A preparation method of a gallium arsenide multi-junction solar cell chip comprises the following steps:
sequentially generating a battery function layer and an ohmic contact layer on a substrate;
defining an electrode area on the ohmic contact layer by adopting a photoetching process;
removing the ohmic contact layer outside the electrode region by adopting an etching process;
forming an antireflection layer on the battery functional layer and the surface of the ohmic contact layer after the corrosion process by adopting an evaporation process;
defining an electrode area on the antireflection layer by adopting a photoetching process;
removing the antireflection layer on the electrode area by adopting a corrosion process;
and preparing a front electrode, wherein the front electrode is connected with the ohmic contact layer and is exposed outside the antireflection layer.
5. The method of claim 4, wherein the method comprises the steps of: the front electrode also comprises a main grid electrode and a plurality of fine grid electrodes;
defining an electrode area on the ohmic contact layer by adopting a photoetching process, wherein the electrode area comprises a main gate electrode area and a fine gate electrode area, and removing the ohmic contact layer outside the main gate electrode area and the fine gate electrode area by adopting an etching process;
defining a thin gate electrode area on the antireflection layer by adopting a photoetching process, and then removing the antireflection layer in the thin gate electrode area by adopting a corrosion process, wherein the ohmic contact layer at the main gate electrode area is used as a supporting layer;
preparing the main grid electrode and the fine grid electrode, wherein the fine grid electrode is connected with the ohmic contact layer and exposed outside the antireflection layer, the main grid electrode is arranged on the antireflection layer and positioned above the supporting layer, and the fine grid electrode is connected with the main grid electrode.
6. The method of claim 4, wherein the method comprises the steps of: the substrate is a Ge substrate, the battery function layer comprises a Ge sub battery, a GaAs sub battery and a GaInP sub battery, and the ohmic contact layer is a GaAs ohmic contact layer;
and sequentially generating a Ge sub-battery, a GaAs sub-battery, a GaInP sub-battery and a GaAs ohmic contact layer on the Ge substrate by adopting MOCVD.
7. The method of claim 4, wherein the method comprises the steps of: and removing the antireflection layer in the electrode area by adopting hydrofluoric acid corrosion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011506396.9A CN112614901B (en) | 2020-12-18 | 2020-12-18 | Gallium arsenide multi-junction solar cell chip and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011506396.9A CN112614901B (en) | 2020-12-18 | 2020-12-18 | Gallium arsenide multi-junction solar cell chip and preparation method thereof |
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| CN112614901A CN112614901A (en) | 2021-04-06 |
| CN112614901B true CN112614901B (en) | 2021-10-26 |
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