CN112614836A - Protective semiconductor device - Google Patents
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- CN112614836A CN112614836A CN202011491131.6A CN202011491131A CN112614836A CN 112614836 A CN112614836 A CN 112614836A CN 202011491131 A CN202011491131 A CN 202011491131A CN 112614836 A CN112614836 A CN 112614836A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 187
- 230000001681 protective effect Effects 0.000 title abstract description 10
- 239000002019 doping agent Substances 0.000 claims description 20
- 230000005684 electric field Effects 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 210000000746 body region Anatomy 0.000 claims description 4
- 230000009471 action Effects 0.000 abstract description 5
- 230000004044 response Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 13
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- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000001960 triggered effect Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
The invention discloses a protective semiconductor device, relates to a semiconductor device, and solves the technical problems of low response speed, robustness and reliability of the protective semiconductor device under high voltage or high power. Multiple electron-hole-electron-hole circulation reciprocating can be formed between the N-VLD area and the P-type anode area, so that strong current is formed between the anode and the cathode, and the working state of each unit cell is kept highly consistent under the dynamic current equalizing action of the N-VLD area. Therefore, when surge current occurs in an external circuit, a channel of the maximum current can be formed between the anode and the cathode by actively controlling the trigger electrode, the capacity of the device for passing the surge current is improved, and active protection of a circuit system is realized.
Description
Technical Field
The present disclosure relates to semiconductor devices, and more particularly to a protected semiconductor device with respect to high voltage and/or high power.
Background
The semiconductor protective device is widely applied to the fields of consumer electronics, white home appliances, industrial control, power electronics, national defense electronics and the like. As an electronic component which instantly releases redundant voltage or current, in a normal state, the protection device is only used as an auxiliary element of the main circuit and does not participate in or influence the normal circuit function of the main circuit; only when the voltage at two ends of the protection device or the current flowing through the protection device exceeds a certain threshold value, the protection device enters a breakdown clamping or latching working state, and redundant energy in the circuit is discharged from the protection device of the bypass, so that the purpose of protecting the main circuit is achieved.
Because most of the protective devices are passive elements and cannot control the work of the protective devices in advance or in a delayed manner, the protective devices are not suitable for some application fields needing active circuit energy discharge; secondly, particularly in the application occasions of high voltage or high power protection, the method puts forward the strict requirements on the response speed, robustness and reliability of the protection type semiconductor device, and the existing protection device is difficult to be qualified for the application in the fields. The main reason is that a semiconductor device is often formed by arranging thousands of minimum cell units in parallel, and all the cells in the device are extremely difficult to work consistently due to the influence of factors such as process deviation, lead parasitic parameters and the like, so that the dynamic performance of the device is greatly influenced, the safe working area of the device is reduced, and even the device fails.
Disclosure of Invention
The present disclosure provides a protection type semiconductor device, the technical purpose of which is: under high voltage or high power, the response speed of the protective semiconductor device is improved, and the robustness and reliability of the protective semiconductor device are enhanced.
The technical purpose of the present disclosure is achieved by the following technical solutions:
a protection type semiconductor device comprises a first conductivity type semiconductor region, wherein a first second conductivity type semiconductor region is arranged at the bottom of the first conductivity type semiconductor region, and an anode is connected to the bottom of the first second conductivity type semiconductor region;
a second conductive type semiconductor region is arranged on the top of the first conductive type semiconductor region, and a second first conductive type semiconductor region with the doping amount changed along the horizontal direction is arranged in the second conductive type semiconductor region;
a trigger region is arranged on one side of the second conductive type semiconductor region, and a cathode is arranged on the other side of the second conductive type semiconductor region, wherein the trigger region comprises a part of the first conductive type semiconductor region, a part of the second conductive type semiconductor region and a part of the second conductive type semiconductor region; the cathode forms an ohmic contact with both a part of the second conductivity type semiconductor region and a part of the second first conductivity type semiconductor region;
at least one trigger electrode is further arranged in the trigger area, and the trigger electrode and part of the second conductivity type semiconductor area form ohmic contact; or
The trigger electrode is isolated from a part of the first conductivity type semiconductor region, a part of the second conductivity type semiconductor region and a part of the second first conductivity type semiconductor region by a medium.
Further, the second conductivity-type semiconductor region is:
a second conductivity type semiconductor region having the same dopant amount in the horizontal direction; or
A second conductivity type semiconductor region of varying dopant amount in a horizontal direction.
Further, the dopant amount of the impurity of the second first-conductivity-type semiconductor region gradually increases in a direction from the trigger region to the cathode;
when the second conductivity type semiconductor region is changed in the dopant amount in the horizontal direction, the dopant amount of the impurity of the second conductivity type semiconductor region is gradually increased in the direction from the trigger electrode to the cathode.
Further, the trigger area comprises a planar gate MOSFET structure and a trench gate MOSFET structure;
the trigger area is when plane bars MOSFET structure, plane bars MOSFET structure includes: a part of the first conduction type semiconductor region becomes a drain region of the planar gate MOSFET structure, a part of the second conduction type semiconductor region becomes a source body region of the planar gate MOSFET structure, and a part of the second first conduction type semiconductor region becomes a source region of the planar gate MOSFET structure, a first medium exists along the horizontal direction to cover a part of the first conduction type semiconductor region, a part of the second conduction type semiconductor region and a part of the second first conduction type semiconductor region, the first medium becomes a first gate medium of the planar gate MOSFET structure, the trigger electrode covers the first gate medium, and the trigger electrode becomes a gate electrode of the planar gate MOSFET structure;
when the MOSFET structure is deleted to the groove to the trigger area, the MOSFET structure is deleted to the groove includes: part of the first conduction type semiconductor region becomes a drain region of the trench gate MOSFET structure, part of the second conduction type semiconductor region becomes a source body region of the trench gate MOSFET structure, and part of the second first conduction type semiconductor region becomes a source region of the trench gate MOSFET structure, a second medium exists to cover part of the first conduction type semiconductor region, part of the second conduction type semiconductor region and part of the second first conduction type semiconductor region along the vertical direction, the second medium becomes a second gate medium of the trench gate MOSFET structure, the trigger electrode is in direct contact with the second gate medium, and the trigger electrode becomes a gate electrode of the trench gate MOSFET structure;
further, at least two MIS (metal-dielectric-semiconductor) structures are arranged on the top of the second conductivity type semiconductor region, different bias voltages are applied to each MIS structure so as to obtain the inversion charge density of each MIS structure, and therefore the second first conductivity type semiconductor region with the doping amount changed along the horizontal direction is obtained.
Further, a third first conductivity type semiconductor region is connected to the anode, the third first conductivity type semiconductor region being in contact with the first second conductivity type semiconductor region, the third first conductivity type semiconductor region being also in contact with the first conductivity type semiconductor region.
Further, a fourth first conductivity type semiconductor region is further provided at the bottom of the first conductivity type semiconductor region, and the fourth first conductivity type semiconductor region is in contact with the first second conductivity type semiconductor region.
The beneficial effect of this disclosure lies in: the protection type semiconductor device comprises a first conduction type semiconductor region, wherein a first second conduction type semiconductor region is arranged at the bottom of the first conduction type semiconductor region, and an anode is connected to the bottom of the first second conduction type semiconductor region. And a second conductive type semiconductor region is arranged on the top of the first conductive type semiconductor region, and a second first conductive type semiconductor region with the doping amount changed along the horizontal direction is arranged in the second conductive type semiconductor region.
Because the second first conductivity type semiconductor region is a semiconductor region with variable doping, a plurality of electron-hole-electron-hole cycles can be formed between the second first conductivity type semiconductor region and the second conductivity type semiconductor region, so that a strong current is formed between the anode A and the cathode K, and the process only needs tens of nanoseconds. Therefore, when surge current occurs in an external circuit, a channel with extremely large current can be formed between the anode A and the cathode K by actively controlling the trigger electrode T, and the capacity of the device for passing the surge current is greatly improved, so that active protection of the semiconductor device is realized, the response speed of the semiconductor device is improved, and the robustness and the reliability of the semiconductor device are enhanced.
Drawings
FIG. 1 is a schematic structural diagram of a protected semiconductor device according to the present invention;
FIG. 2 is a schematic diagram of a cell unit of a protection type semiconductor device;
FIG. 3 is a schematic diagram of a structure for multi-step doping to achieve N-VLD and P-VLD;
FIG. 4 is a schematic structural diagram of a planar gate MOSFET structure in a trigger area;
FIG. 5 is a schematic structural diagram of a trench gate MOSFET structure in a trigger area;
FIG. 6 is a schematic diagram of a structure for implementing N-VLD using multiple MIS structures;
FIG. 7 is a schematic diagram of a structure employing a planar gate MOSFET structure as the trigger region and an MIS structure as part of the N-VLD region;
FIG. 8 is a schematic diagram of a structure employing a trench gate MOSFET structure as a trigger region and a MIS structure as part of the N-VLD region;
FIG. 9 is a schematic diagram of a structure employing an anode short-circuiting method;
fig. 10 is a schematic view of a structure of adding a buffer layer.
Detailed Description
The technical scheme of the disclosure will be described in detail with reference to the accompanying drawings. In the description of the present application, it is to be understood that the terms "first", "second", "third" and "fourth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated, but merely as differentiating between different components. In the description of the present application, the first conductive type includes an N-type and a P-type, the second conductive type also includes an N-type and a P-type, and when the first conductive type is an N-type, the second conductive type is a P-type; when the first conductivity type is P-type, the second conductivity type is N-type.
Furthermore, the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "side wall", "vertical", "horizontal", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing and simplifying the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, elements having similar structures are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for understanding and ease of description, but the present application is not limited thereto.
In the drawings, the range of configurations of devices, systems, components, circuits is exaggerated for clarity, understanding, and ease of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.
In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components. Further, in the specification, "on.
To further illustrate the technical means and effects adopted by the present application to achieve the predetermined objects, the following detailed description will be given of embodiments, structures, features and effects of a high-voltage and/or high-power active protection type semiconductor device according to the present application with reference to the accompanying drawings and specific embodiments.
The protection type semiconductor device is a high-voltage-resistant protection type semiconductor three-terminal device and is provided with an independent control port. Fig. 1 is a schematic structural diagram of a guard type semiconductor device according to the present invention, and as shown in fig. 1, the guard type semiconductor device includes a first conductivity type semiconductor region, a first second conductivity type semiconductor region is disposed at the bottom of the first conductivity type semiconductor region, and an anode a is connected to the bottom of the first second conductivity type semiconductor region.
The top of the first conductivity type semiconductor region is provided with a second conductivity type semiconductor region in which a second first conductivity type semiconductor region of which the dopant amount is changed in the horizontal direction is provided. One side of the second conductive type semiconductor region is provided with a trigger region, and the other side of the second conductive type semiconductor region is provided with a cathode K, wherein the trigger region comprises a part of the first conductive type semiconductor region, a part of the second conductive type semiconductor region and a part of the second first conductive type semiconductor region; the cathode forms ohmic contacts with both the second conductivity type semiconductor region of the K portion and a portion of the second first conductivity type semiconductor region.
At least one trigger electrode T is further disposed in the trigger region, and the trigger electrode T forms an ohmic contact with a portion of the second-conductivity-type semiconductor region (the trigger region shown in fig. 1) or is isolated from a portion of the first-conductivity-type semiconductor region, a portion of the second-conductivity-type semiconductor region, and a portion of the second first-conductivity-type semiconductor region by a dielectric (the trigger region shown in fig. 4).
Fig. 2 is a schematic structural diagram of an embodiment of a cell unit in a protection type semiconductor device, that is, the protection type semiconductor device at least includes one cell unit. In fig. 2, the semiconductor device includes a semiconductor substrate 002(N region 002) of the first conductivity type N type, and a doped region 001 of the second conductivity type P type, called an anode region, is disposed at the bottom of the semiconductor substrate, and the P doped region 001(P region 001) contacts the anode metal layer a. The top of the semiconductor substrate 002 is provided with a P-type semiconductor region (P-VLD) which is doped along the transverse change and is called a P-type base region, an N-type semiconductor region (N-VLD) which is doped along the transverse change is arranged in the P-type semiconductor region which is doped along the transverse change, a trigger region is arranged on one side of the P-VLD region, a trigger electrode T is arranged in the trigger region, and a metal layer of the trigger electrode T is in ohmic contact with the P-VLD region. And a cathode K is arranged on the other side of the P-VLD region, and a metal layer of the cathode K is in ohmic contact with part of the P-VLD region and part of the N-VLD region. Although fig. 2 illustrates the first conductivity type as N-type and the second conductivity type as P-type, the first conductivity type as P-type and the second conductivity type as N-type are also applicable, and the following is the same.
The operation principle of the protection type semiconductor device shown in fig. 2 is specifically as follows. Before the semiconductor device is triggered, a positive bias voltage V is applied between the anode A and the cathode KAKAnd a voltage V between the trigger electrode T and the cathode KTKLess than or equal to 0, the device works in a voltage-resistant blocking state, and a large-impedance resistor is equivalently arranged between the anode A and the cathode K. When the external circuit system detects the arrival of surge voltage or surge current, only one trigger electrode T and a cathode K are needed to be filled with the current for achieving the purpose of active protectionConstant trigger current IAKAt this time IAKFlows through the P-VLD region from the trigger electrode T to the cathode electrode K and forms a transverse voltage drop (namely V) gradually reduced from the T electrode to the K electrode in the P-VLD regionTK>0). Obviously, the trigger current I is controlledAKAnd can control the magnitude of the lateral voltage drop of the P-VLD region. When triggering current IAKIncreasing to a certain threshold value makes part of the potential of the P-VLD region exceed the potential of the adjacent N-VLD region by the built-in potential of the PN junction (taking silicon material as an example, the built-in potential of the PN junction is about 0.7V), and then a large number of electrons flow through the N-VLD region from the cathode K and are injected into the P-VLD region, wherein a small part of the electrons are recombined with holes in the P-VLD region and disappear, and most of the rest electrons pass through the P-VLD region to reach the N region 002 and reach the P region 001 under the action of a strong electric field of a reverse biased PN junction formed by the N region 002 and the P-VLD region. The electrons reach the P region 001, a large number of holes in the P region 001 are injected into the N region 002, a part of the holes are recombined with the electrons and disappear, and the rest holes move to the P-VLD region under the double effects of an electric field and concentration gradient distribution and are further injected into the N-VLD region; the arrival of holes at the N-VLD region will in turn result in the injection of a large number of electrons into the P-VLD region and eventually to the P region 001, a process of enhanced electron-hole circulation, i.e. a positive feedback process of electron-hole bipolar injection. Generally, the time of the reciprocation process of triggering the primary hole by the primary electron is usually in the order of nanoseconds, and a strong current can be formed between the anode a and the cathode K after a plurality of electron-hole-electron-hole cyclic reciprocations, and the process only needs tens of nanoseconds. Therefore, when surge current occurs in an external circuit, a channel for extremely large current can be formed between the anode A and the cathode K by actively controlling the trigger electrode T.
The semiconductor device is often formed by stacking thousands of cells of repeatable unit cells in parallel, and one semiconductor device can be formed by stacking the unit cells shown in fig. 2 in parallel. However, in practical situations, due to the influence of process deviation, layout wiring parasitic parameters and other factors, each cell arranged in parallel cannot guarantee an absolutely synchronous working state, so that the working state of a local cell is easily caused to be prior to other cells to cause current concentration, the surge impact resistance of the device is greatly reduced, and the device fails under more serious conditions. In order to achieve the effect of synchronous operation of each unit cell in the device, the active protection type semiconductor device provided by the invention is provided with a P type semiconductor region (P-VLD) doped along the transverse change and an N type semiconductor region (N-VLD) doped along the transverse change, and the working principle is as follows:
after the device is triggered, a certain trigger current IAK is injected between the trigger electrode T and the cathode electrode K, and a lateral voltage drop gradually decreasing from the T electrode to the K electrode is formed in the P-VLD region. Obviously, the PN junction formed by P-VLD and N-VLD is firstly triggered to be conducted at the place close to the trigger area, and the PN junction at the side close to the cathode does not enter the forward conduction state, so that the current path from the anode A to the cathode K is mainly concentrated at the side close to the trigger area. According to the invention, the doping amount of acceptor impurities in the P-VLD region is gradually increased along the direction from the T pole to the K pole, so that the transverse voltage drop in the P-VLD region is also nonlinear, the transverse voltage drop close to the trigger region is the largest, and the transverse voltage drop close to the cathode K is the smallest, so that holes in a PN junction which is firstly triggered and conducted can be quickly diffused towards the cathode K under the action of the transverse voltage drop, and a current path between AKs is further driven to be quickly diffused from one side of the trigger region to one side of the cathode region, thereby achieving the purpose of quick current equalization. The invention also arranges that the dopant quantity of the donor impurity of the N-VLD region is gradually increased along the direction from the T pole to the K pole, so that the injection efficiency of the nonequilibrium carriers of the PN junction formed by the P-VLD and the N-VLD is gradually increased along the direction from the T pole to the K pole, and when the PN junction formed by the P-VLD and the N-VLD is firstly triggered to be conducted at the place close to the trigger region, the lower injection efficiency of the nonequilibrium carriers limits the sharp increase of the current; furthermore, the current is limited from sharply increasing because the current flows through the N-VLD region in the transverse direction and generates a transverse voltage drop in the N-VLD region, which gradually decreases from the T pole to the K pole, and the existence of the transverse voltage drop in turn weakens the forward voltage drop of the PN junction near the trigger region. On one hand, the current is quickly equalized due to the action of the P-VLD region, and on the other hand, the current of the PN junction which is firstly conducted is limited due to the action of the N-VLD region, so that other cells which are arranged in parallel can have enough time to enter the working state which is the same as that of the cell, the purpose of quickly equalizing the current of the device can be greatly improved, and the capacity of the device for passing surge current is greatly improved.
As a specific embodiment, in order to obtain a compromise between the electrical performance of the fast current sharing and the process complexity, the P-VLD region may also adopt a first-order segmentation method, that is, all regions of the P-VLD region have the same doping, as shown in the P-VLD region in fig. 8.
Fig. 3, 4, 5, 6 and 7 each show a schematic structure diagram of implementing N-VLD and P-VLD by multi-step doping, and for understanding and convenience of description, the N1, N2 and N3 regions and the P1, P2 and P3 regions in the drawings are merely examples, and it is obvious that the present application is not limited thereto. In fig. 3, the relationship between the doping amounts of the N1, N2 and N3 regions is: the dopant dose of the N1 region < the dopant dose of the N2 region < the dopant dose of the N3 region; the relation of the doping doses of the P1, P2 and P3 regions is as follows: dopant dose of P1 region < dopant dose of P2 region < dopant dose of P3 region; the working principle is similar to that of fig. 2, and is not described again.
Fig. 4 is a schematic structural diagram of a trigger region adopting a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) structure, which is different from the current trigger method of fig. 2, and fig. 4 adopts voltage control triggering, and the operating principle thereof is as follows. As shown in fig. 4, a portion of N region 002 is covered with dielectric regions, a portion of P1 is covered with dielectric regions, and a portion of N1 is covered with a trigger electrode T conductor, forming a planar gate N-MOSFET, a portion of N region 002 is the drain region of the planar gate N-MOSFET, a portion of P1 is the source region of the planar gate N-MOSFET, a portion of N1 is the source region of the planar gate N-MOSFET, and electrode T is the gate of the planar gate N-MOSFET. When a positive voltage V is applied to trigger electrode TTKWhen V isTKWhen the threshold voltage of the planar gate N-MOSFET is exceeded, the planar gate N-MOSFET is started, at the moment, current flows from the cathode K to the planar gate N-MOSFET channel region through the N-VLD region, enters the N region 002 through the planar gate N-MOSFET channel region and finally reaches the P region 001, and electrons reach the P region 001 to cause a large number of holes in the P region 001 to be injected into the N region 001A region 002, in which a part of holes and electrons are recombined and disappear, and the rest holes move to the P-VLD region under the dual action of electric field and concentration gradient distribution, and then are injected into the N-VLD region; the arrival of holes at the N-VLD region will in turn result in a large number of electrons being injected into the P-VLD region and eventually into the P region 001, creating a positive feedback of electron-hole bipolar injection. Generally, the time of the reciprocation process of triggering the primary hole by the primary electron is usually in the order of nanoseconds, and a strong current can be formed between the anode a and the cathode K after a plurality of electron-hole-electron-hole cyclic reciprocations, and the process only needs tens of nanoseconds. Therefore, when surge current occurs in an external circuit, a channel for extremely large current can be formed between the anode A and the cathode K by actively controlling the trigger electrode T. Wherein the roles of the N-VLD region and the P-VLD region are similar to those of FIG. 2, and are not described herein again.
Fig. 5 shows a structure using a trench gate MOSFET as a trigger region, and as shown in fig. 5, a dielectric region is provided on the sidewall of a part of N region 002 and a part of P1 region and on the top of a part of N1 region, and a conductor of a trigger electrode T is covered on the other side of the dielectric region to form a trench gate N-MOSFET, where N region 002 is a drain region of the trench gate N-MOSFET, a part of P1 is a source region of the trench gate N-MOSFET, a part of N1 is a source region of the trench gate N-MOSFET, and an electrode T is a gate of the trench gate N-MOSFET. When a positive voltage V is applied to trigger electrode TTKWhen V isTKWhen the threshold voltage of the trench gate N-MOSFET is exceeded, the trench gate N-MOSFET is started, at the moment, current flows from the cathode K through the N-VLD region to reach the trench gate N-MOSFET channel region, passes through the trench gate N-MOSFET channel region, enters the N region 002 and finally reaches the P region 001, electrons reach the P region 001, a large number of holes in the P region 001 are injected into the N region 002, a part of the holes and the electrons are compounded and disappear, and the rest of the holes move to the P-VLD region under the double effects of an electric field and concentration gradient distribution and are further injected into the N-VLD region; the arrival of holes at the N-VLD region will in turn result in a large number of electrons being injected into the P-VLD region and eventually into the P region 001, creating a positive feedback of electron-hole bipolar injection. In general, the time for triggering the reciprocating process of the primary hole by the primary electron is usually in the order of nanoseconds, and the electron passes several timesThe hole-electron-hole cycle can form strong current between the anode A and the cathode K, and the process only needs tens of nanoseconds. Therefore, when surge current flows in an external circuit, a channel with large current can be formed between the anode A and the cathode K by actively controlling the trigger electrode T, wherein the functions of the N-VLD region and the P-VLD region are similar to those of FIG. 2, and are not described again here.
Fig. 6 shows a structure in which an N-VLD region is realized using an inversion electron shell of a plurality of MIS (Metal-Insulator-Semiconductor) structures. The difference from fig. 3 is that fig. 6 obtains N-type semiconductor regions (N-VLD) equivalent to varying the dopant amount in the horizontal direction by employing MIS structures in which a plurality of metal-dielectric-semiconductors are provided and obtaining different doses of inversion electron shells (different inversion charge densities of the respective MIS structures) by applying different bias voltages to the respective MIS structures. It is noted that since the different MIS structures are spaced apart from one another, fig. 6 provides an n + region between the MIS structures to electrically communicate the inversion electron shells of the MIS structures. The method of fig. 6 is simpler than that of fig. 3 because the N region is doped a plurality of times with different doses.
Fig. 7 shows a protection type semiconductor device using a planar gate MOSFET structure as a trigger region and a MIS structure as a part of an N-VLD region, as a specific embodiment.
As a specific embodiment, fig. 8 shows a protection type semiconductor device employing a trench gate MOSFET structure as a trigger region and an MIS structure as an N-VLD region portion. The P-VLD region adopts a first-stage segmentation method (namely, the doping of the P-VLD region is the same) so as to obtain the compromise of the electrical performance and the process complexity of the rapid current sharing.
Fig. 9 is a semiconductor structure employing an anode short, specifically: the anode metal is in contact with not only the P region 001 but also the N + region 007 (which may be understood as a third first conductivity type semiconductor region), thereby forming an anode short structure. The anode short-circuit structure shown in fig. 9 can make the withstand voltage of the device higher and the reverse bias leakage current smaller, and can also form a body diode composed of a P-VLD region, an N region 002 and an N + region 007, which is particularly suitable for a scene needing follow current application.
Different from fig. 9, in fig. 10, a buffer layer 008 (i.e., a fourth first conductivity type semiconductor region) is added at the bottom of the n region 002 (i.e., an n-buffer layer), and the arrangement of the n-buffer layer can make the electric field of the voltage-resistant region of the device approach to a trapezoid, so that the thickness of the n region 002 of the voltage-resistant region is smaller under a certain breakdown voltage, thereby reducing the internal resistance of the device during conduction and improving the overcurrent capability.
The foregoing is an exemplary embodiment of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.
Claims (7)
1. A protection type semiconductor device is characterized by comprising a first conduction type semiconductor region, wherein a first second conduction type semiconductor region is arranged at the bottom of the first conduction type semiconductor region, and an anode is connected to the bottom of the first second conduction type semiconductor region;
a second conductive type semiconductor region is arranged on the top of the first conductive type semiconductor region, and a second first conductive type semiconductor region with the doping amount changed along the horizontal direction is arranged in the second conductive type semiconductor region;
a trigger region is arranged on one side of the second conductive type semiconductor region, and a cathode is arranged on the other side of the second conductive type semiconductor region, wherein the trigger region comprises a part of the first conductive type semiconductor region, a part of the second conductive type semiconductor region and a part of the second conductive type semiconductor region; the cathode forms an ohmic contact with both a part of the second conductivity type semiconductor region and a part of the second first conductivity type semiconductor region;
at least one trigger electrode is further arranged in the trigger area, and the trigger electrode and part of the second conductivity type semiconductor area form ohmic contact; or
The trigger electrode is isolated from a part of the first conductivity type semiconductor region, a part of the second conductivity type semiconductor region and a part of the second first conductivity type semiconductor region by a medium.
2. A protected semiconductor device according to claim 1, wherein the second-conductivity-type semiconductor region is:
a second conductivity type semiconductor region having the same dopant amount in the horizontal direction; or
A second conductivity type semiconductor region of varying dopant amount in a horizontal direction.
3. A guarded semiconductor device according to claim 2, wherein a dopant amount of the impurity of the second first-conductivity-type semiconductor region is gradually increased in a direction from the trigger region to the cathode;
when the second conductivity type semiconductor region is changed in the dopant amount in the horizontal direction, the dopant amount of the impurity of the second conductivity type semiconductor region is gradually increased in the direction from the trigger electrode to the cathode.
4. The protected semiconductor device of claim 3, wherein the trigger region comprises a planar gate MOSFET structure and a trench-cut MOSFET structure;
the trigger area is when plane bars MOSFET structure, plane bars MOSFET structure includes: a part of the first conduction type semiconductor region becomes a drain region of the planar gate MOSFET structure, a part of the second conduction type semiconductor region becomes a source body region of the planar gate MOSFET structure, and a part of the second first conduction type semiconductor region becomes a source region of the planar gate MOSFET structure, a first medium exists along the horizontal direction to cover a part of the first conduction type semiconductor region, a part of the second conduction type semiconductor region and a part of the second first conduction type semiconductor region, the first medium becomes a first gate medium of the planar gate MOSFET structure, the trigger electrode covers the first gate medium, and the trigger electrode becomes a gate electrode of the planar gate MOSFET structure;
when the MOSFET structure is deleted to the groove to the trigger area, the MOSFET structure is deleted to the groove includes: part of the first conductivity type semiconductor region becomes a drain region of the trench gate MOSFET structure, part of the second conductivity type semiconductor region becomes a source body region of the trench gate MOSFET structure, and part of the second first conductivity type semiconductor region becomes a source region of the trench gate MOSFET structure, there is a second medium which covers part of the first conductivity type semiconductor region, part of the second conductivity type semiconductor region and part of the second first conductivity type semiconductor region along the vertical direction, the second medium becomes the second gate medium of the trench gate MOSFET structure, the trigger electrode directly contacts with the second gate medium, and the trigger electrode becomes a gate of the trench gate MOSFET structure.
5. A guard type semiconductor device according to claim 4, wherein at least two MIS (metal-dielectric-semiconductor) structures are provided on top of said second conductivity type semiconductor region, and different bias voltages are applied to each of said MIS structures to obtain an inversion charge density of each of said MI structures, thereby obtaining said second first conductivity type semiconductor region with a dopant amount varying in a horizontal direction.
6. A protected semiconductor device according to claim 5, wherein a third semiconductor region of the first conductivity type is further connected to the anode, said third semiconductor region of the first conductivity type being referred to as an anode short, said third semiconductor region of the first conductivity type being in contact with said semiconductor region of the second conductivity type, said third semiconductor region of the first conductivity type being further in contact with said first semiconductor region of the first conductivity type.
7. A protected semiconductor device according to any of claims 1-6, wherein a fourth semiconductor region of the first conductivity type is further provided at the bottom of the semiconductor region of the first conductivity type, said fourth semiconductor region of the first conductivity type being called a buffer region or an electric field stop region, and said fourth semiconductor region of the first conductivity type being in contact with said semiconductor region of the first second conductivity type.
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| CN202011491131.6A CN112614836B (en) | 2020-12-17 | 2020-12-17 | Protective semiconductor device |
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| CN202011491131.6A CN112614836B (en) | 2020-12-17 | 2020-12-17 | Protective semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113972264A (en) * | 2021-12-27 | 2022-01-25 | 南京芯舟科技有限公司 | Current protection type semiconductor device |
| CN117334694A (en) * | 2023-12-01 | 2024-01-02 | 南京芯舟科技有限公司 | Overcurrent protection device |
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| CN112614836B (en) | 2021-07-30 |
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