CN112599491A - Silicon substrate based on low thermal stress through silicon via - Google Patents
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- CN112599491A CN112599491A CN202011477841.3A CN202011477841A CN112599491A CN 112599491 A CN112599491 A CN 112599491A CN 202011477841 A CN202011477841 A CN 202011477841A CN 112599491 A CN112599491 A CN 112599491A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 139
- 239000010703 silicon Substances 0.000 title claims abstract description 139
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 133
- 239000000758 substrate Substances 0.000 title claims abstract description 95
- 230000008646 thermal stress Effects 0.000 title claims abstract description 35
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 55
- 229910052802 copper Inorganic materials 0.000 claims abstract description 49
- 239000010949 copper Substances 0.000 claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 239000007769 metal material Substances 0.000 claims abstract description 7
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 25
- 239000002210 silicon-based material Substances 0.000 claims description 24
- 239000003989 dielectric material Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 27
- 238000005498 polishing Methods 0.000 description 15
- 238000005530 etching Methods 0.000 description 11
- 238000011049 filling Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000003792 electrolyte Substances 0.000 description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- -1 polydithio-dipropyl Polymers 0.000 description 3
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 2
- 239000002202 Polyethylene glycol Substances 0.000 description 2
- 229910018503 SF6 Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000005495 cold plasma Effects 0.000 description 2
- BSXVKCJAIJZTAV-UHFFFAOYSA-L copper;methanesulfonate Chemical compound [Cu+2].CS([O-])(=O)=O.CS([O-])(=O)=O BSXVKCJAIJZTAV-UHFFFAOYSA-L 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
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- 239000003112 inhibitor Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229920001223 polyethylene glycol Polymers 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 229910052708 sodium Inorganic materials 0.000 description 2
- 239000011734 sodium Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- BDHFUVZGWQCTTF-UHFFFAOYSA-M sulfonate Chemical compound [O-]S(=O)=O BDHFUVZGWQCTTF-UHFFFAOYSA-M 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 230000000930 thermomechanical effect Effects 0.000 description 1
- 239000000080 wetting agent Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a silicon substrate based on low-thermal-stress through silicon vias, which belongs to the technical field of three-dimensional integrated circuits, and reduces the thermal stress of the silicon substrate while ensuring the electrical performance, and comprises a silicon substrate plate, wherein the upper surface and the lower surface of the silicon substrate plate are respectively attached with a first insulating layer; the upper and lower bottom surfaces of the metal copper are respectively connected with a contact lead wire disc made of metal materials.
Description
Technical Field
The invention belongs to the technical field of three-dimensional integrated circuits, relates to a silicon substrate, and particularly relates to a silicon substrate based on a low-thermal-stress through silicon via, which can be used for designing and manufacturing a high-integration three-dimensional integrated circuit.
Background
With the continuous development of portable electronic products, the application of integrated circuits in electronic products becomes very wide, the traditional integrated circuits are manufactured on two-dimensional planes, but as the functions realized by the products are more and more complex, the device integration level on a silicon substrate in the integrated circuits is continuously improved, and as the number of devices on the silicon substrate is increased sharply, the interconnection problem of the two-dimensional integrated circuits becomes more and more prominent, while the interconnection problem of the two-dimensional integrated circuits is solved by the three-dimensional integrated circuits. In the three-dimensional integrated circuit, silicon substrates with different functions are stacked in the vertical direction, so that the device integration level of the integrated circuit is improved, the silicon through holes are used as important components of the silicon substrate in the three-dimensional integrated circuit and are very important for further improving the integration level of devices on the silicon substrate, and the silicon substrate adopts a vertical interconnection mode to connect circuit devices on the silicon substrate, so that the length of an interconnection line is greatly shortened, and the silicon substrate with higher device integration level and smaller size can be realized.
Since the manufacturing process of silicon substrates involves a plurality of materials and there is a significant difference in thermal expansion coefficient between different materials, large thermal stress is formed during the manufacturing process and during the use process. Wherein the through-silicon via is the main part that produces thermal stress, and the traditional structure of through-silicon via is: the method comprises the steps of filling metal copper in circular through holes etched in a silicon substrate plate, wherein the circular through holes are used for electric signal transmission among devices, preventing crosstalk among electric signals in the transmission process and ensuring the integrity of the electric signals, and an insulating layer is arranged between the metal copper and the silicon substrate plate and used for isolating copper atom diffusion and preventing leakage current from influencing the performance of the devices in the silicon substrate plate. Excessive thermal stress can cause problems of thermo-mechanical reliability such as interlayer dielectric rupture on the silicon substrate, peeling of the silicon through hole and the silicon substrate plate, bonding failure and the like. Meanwhile, due to the existence of the piezoresistive effect in the silicon material, the generated thermal stress can affect the mobility of a transistor placed in the silicon substrate, influence the performance and the time sequence of a single device or even the whole circuit, and even cause the circuit to be incapable of working normally.
In order to reduce the thermal stress in the silicon substrate, for example, in the patent application with application publication No. CN 108933101 a entitled "TSV structure for eliminating thermal stress", a silicon substrate structure with low thermal stress is disclosed, the invention includes a silicon substrate layer, wherein the upper side and the lower side of the silicon substrate layer are both provided with an insulating layer, and a copper pillar penetrating through the silicon substrate layer is arranged in the silicon substrate layer, an air gap is arranged between the side surface of the copper pillar and the silicon substrate layer, and an aluminum substrate is connected to the upper end and the lower end of the copper pillar. The annular air gap is used as an insulating layer between the copper column of the silicon through hole and the silicon substrate, and when the copper column deforms at high temperature, the air gap provides a free deformation area for the expansion of the copper column, so that the copper column does not extrude the silicon substrate any more, and the thermal stress in the silicon substrate is weakened. In the silicon substrate structure provided by the invention, the extrusion between the copper column and the silicon substrate is avoided only by introducing the air gap, the heat and the deformation degree of the copper column in the high-temperature process are not reduced, and the air gap in the silicon substrate causes the copper column and the silicon substrate to be not tightly attached, so that the mechanical reliability of the silicon through hole is reduced, and the service life of the silicon substrate is shortened.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a silicon substrate based on a low thermal stress through silicon via, which can reduce the thermal stress of the silicon substrate while ensuring the electrical performance.
In order to achieve the purpose, the invention adopts the technical scheme that:
a silicon substrate based on low thermal stress silicon through holes is characterized by comprising a silicon substrate plate 1, wherein the upper surface and the lower surface of the silicon substrate plate 1 are respectively attached with a first insulating layer 2, a plurality of silicon through holes 3 penetrating through the upper plate surface and the lower plate surface are arranged on the silicon substrate plate 1, the silicon through holes 3 comprise a cylindrical dielectric material 31, a hollow cylindrical metal copper 32, a hollow cylindrical silicon material 33 and a hollow cylindrical second insulating layer 34 which are sequentially nested from inside to outside, and the thermal expansion coefficient of the silicon material 33 is the same as that of the silicon substrate plate 1; the upper and lower bottom surfaces of the metal copper 32 are respectively connected with a contact lead pad 4 made of metal material;
the implementation method of the through silicon via 3 is as follows: etching a circular through hole on the silicon substrate plate 1, filling a dielectric material 31 into the circular through hole, etching a first annular through hole around the cylindrical surface of the dielectric material 31, filling metal copper 32 into the circular through hole, etching a second annular through hole around the cylindrical surface of the metal copper 32, attaching a second insulating layer 34 on the inner wall of the second annular through hole, and filling a silicon material 33 between the outer cylindrical surface of the metal copper 32 and the second insulating layer 34.
The low thermal stress through-silicon-via based silicon substrate of claim 1, wherein the dielectric material 31 is silicon dioxide, silicon nitride or benzocyclobutene.
The low thermal stress through-silicon-via based silicon substrate of claim 1, wherein the contact lead pad 4 is made of copper, aluminum or tungsten.
The low thermal stress through-silicon-via-silicon-based silicon substrate according to claim 1, wherein the through-silicon-via 3 has a central axis perpendicular to the plane of the silicon substrate plate 1.
The low thermal stress through-silicon via-based silicon substrate of claim 1, wherein the metallic copper 32, silicon material 33 and second insulating layer 34 have their central axes coincident with the central axis of the dielectric material 31.
Compared with the prior art, the invention has the following advantages:
1. the silicon through holes adopted by the invention comprise cylindrical dielectric materials, hollow cylindrical metal copper, hollow cylindrical silicon materials and hollow cylindrical second insulating layers which are sequentially nested from inside to outside, and the hollow cylindrical metal copper has smaller volume than the metal columns under the condition that the diameters of the silicon through holes are the same, so that the heat and the deformation degree generated in the temperature changing process are reduced, the extrusion between the metal copper and other materials is weakened, and the thermal stress existing in the silicon substrate is effectively reduced.
2. According to the invention, the silicon material is filled between the silicon substrate plate and the metal copper, the maximum point of the thermal stress is moved to the contact surface of the metal copper and the silicon material in the silicon substrate plate from the boundary of the silicon through hole, a buffer area for descending is provided before the thermal stress enters the silicon substrate plate, the thermal stress in the silicon substrate is further reduced, and the silicon substrate plate and the silicon through hole are tightly attached due to the solid filling in the silicon through hole, so that the mechanical reliability of the silicon through hole is improved, and the service life of the silicon substrate is prolonged.
Drawings
FIG. 1 is an overall schematic view of the present invention;
FIG. 2 is a schematic view of a through-silicon via according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the following figures and specific examples:
referring to fig. 1, the present invention includes a silicon substrate board 1, a first insulating layer 2, through-silicon vias 3 and contact lead pads 4; the manufacturing method comprises the steps of manufacturing circuit devices on a silicon substrate plate 1, wherein first insulating layers 2 are respectively attached to the upper surface and the lower surface of the silicon substrate plate 1, the insulating layers can isolate electric signals between vertically stacked silicon substrates, and the circuit on each layer of silicon substrate is guaranteed to achieve a correct function.
A plurality of silicon through holes 3 penetrating through the upper plate surface and the lower plate surface are formed in the silicon substrate plate 1, referring to fig. 2, the silicon through holes 3 comprise cylindrical dielectric materials 31, hollow cylindrical metal copper 32, hollow cylindrical silicon materials 33 and hollow cylindrical second insulating layers 34 which are sequentially nested from inside to outside, and the thermal expansion coefficients of the silicon materials 33 and the silicon substrate plate 1 are the same; the upper and lower bottom surfaces of the metal copper 32 are respectively connected with a contact lead pad 4 made of metal material; the implementation method of the through silicon via 3 is as follows: etching a circular through hole on a silicon substrate plate 1 by adopting a process of etching the circular through hole by an ion reaction etching method, wherein the etching process conditions are as follows: using sulfur hexafluoride SF6Etching with gas under glow dischargeThe fluorine atoms are decomposed electrically and react with the surface silicon atoms to generate gaseous products, so that the purpose of etching is achieved, wherein the pressure of reaction gas is 30 pascals, the flow rate of the reaction gas is 40 milliliters per minute, and the radio frequency power range is 350 watts. Meanwhile, the helium cooling technology is needed to be used for controlling the temperature on the back surface of the silicon substrate plate 1, so that the temperature of the silicon substrate plate 1 is uniformly maintained at 150 ℃ in the whole etching process. The circular through hole penetrates through the silicon substrate plate 1 and the first insulating layer 2 simultaneously when being etched, then a dielectric material 31 is filled in the circular through hole, the dielectric material 31 is made of silicon dioxide, silicon nitride or benzocyclobutene, when thermal stress is a main consideration factor, the silicon dioxide is preferably used, a process is plasma enhanced chemical vapor deposition, the process utilizes a radio frequency induction method to generate large-area glow cold plasma for deposition, and the process conditions are that the radio frequency power is 300 watts, the argon flow is 5 milliliters per minute, and the oxygen flow is 15 milliliters per minute; after the circular through hole is filled with the dielectric material 31, a first annular through hole is etched around the cylindrical surface of the dielectric material 31, metal copper 32 is filled into the circular through hole, the manufacturing process and the conductive property are comprehensively considered, an electroplating process is selected as a process used in the filling process, the process conditions are that electrolyte of a copper methyl sulfonate solution is selected, an accelerator of sodium polydithio-dipropyl sulfonate and an inhibitor of polyethylene glycol with the concentration ratio of 1.5:9 are added into the electrolyte, a direct current precision power supply is used as an electroplating power supply for electrolysis, and copper metal is electroplated in the first annular through hole under the condition that the direct current density of 0.2 ampere/square foot is loaded into the electrolyte, so that the metal copper 32 is formed. Etching a second annular through hole around the cylindrical surface of the metal copper 32, attaching a second insulating layer 34 on the inner wall of the second annular through hole for isolating the diffusion of copper atoms and reducing the influence of leakage current, and adopting thermal oxidation growth or plasma enhanced chemical vapor deposition, but because the insulating layer grown by thermal oxidation can generate larger residual stress, the preferred process is plasma enhanced chemical vapor deposition, and a large-area glow cold plasma is generated by using a radio frequency induction method for deposition, and under the process conditions that the radio frequency power is 300 watts, the argon gas flow is 5 ml/min, and the oxygen flow is 15 ml/min, the second annular through hole is filled with a metal material, so that the metal material is subjected to plasma enhanced chemical vapor deposition, and the deposition is carried out under the processAn insulating layer is deposited on the inner walls of the holes, forming a second insulating layer 34.
After the second insulating layer 34 is attached to the inner wall of the second annular via, a silicon material 33 is filled between the outer cylindrical surface of the metal copper 32 and the second insulating layer 34. The thermal expansion coefficients of the silicon material 33 and the silicon substrate plate 1 are the same, and the material with the same thermal expansion coefficient is used, so that the thermal stress is prevented from being generated again at the boundary of the silicon through hole, and the thermal stress in the silicon substrate plate 1 is further ensured to be reduced; filling silicon material 33 between the outer cylindrical surface of the metal copper 32 and the second insulating layer 34 by using a vacuum assisted spin coating technology, and the steps are as follows: after the wetting agent and the silicon material 33 are well dispersed on the silicon substrate plate 1, the silicon substrate plate 1 is placed into a closed chamber, air extraction treatment is carried out to enable the closed chamber to form a vacuum environment, and the sealed chamber is kept in the vacuum environment for 10 minutes and then taken out; taking out the silicon substrate plate 1, eccentrically placing the silicon substrate plate on a glue homogenizing table, rotating at a high rotating speed of 3000 rpm for 60 seconds, pre-curing the silicon material 33 for 5 minutes in a low-temperature environment at 120 ℃, finally curing for 60 minutes at a high temperature of 250 ℃ to complete the filling of the silicon material 33, and annealing the filled silicon substrate plate 1 at 400 ℃.
Chemically and mechanically polishing the upper and lower surfaces of the annealed silicon substrate plate 1 and the annealed through silicon via 3, and roughly polishing the upper and lower surfaces of the silicon substrate plate 1 and the annealed through silicon via 3 under the conditions that the polishing temperature is 33 ℃ and the pH value of a polishing solution is 10.5; finely polishing the silicon blind holes after rough polishing under the conditions that the polishing temperature is 32 ℃ and the pH value of the polishing solution is 10.5; and (3) finely polishing the silicon blind holes after fine polishing at the polishing temperature of 30 ℃ and the pH value of the polishing solution of 9.0, and sequentially performing three steps of rough polishing, fine polishing and fine polishing on the upper and lower surfaces of the annealed silicon substrate plate 1 and the silicon through hole 3 to enable the upper and lower surfaces of the silicon substrate plate 1 and the silicon through hole 3 to be flush.
The upper bottom surface and the lower bottom surface of the metal copper 32 are respectively connected with a contact lead pad 4 made of metal materials, the contact lead pad 4 can be made of metal copper, metal aluminum or metal tungsten, and the metal copper is preferably used in consideration of the existing process production flow; the process used in the filling process selects an electroplating process, selects an electrolyte of a copper methylsulfonate solution, adds an accelerator of sodium polydithio dipropyl sulfonate and an inhibitor of polyethylene glycol with the concentration ratio of 1.5:9 into the electrolyte, uses a direct current precision power supply as an electroplating power supply to carry out electrolysis, and electroplates the upper and lower bottom surfaces of the metal copper 32 to form the contact lead pads 4 respectively under the condition of loading 0.2 ampere/square foot of direct current density in the electrolyte.
The process of reducing the thermal stress during the work of the invention is as follows: firstly, due to the reduction of the volume of the metal copper 32, the expansion degree generated by the metal copper 32 is reduced, namely, the expansion degree difference between the metal copper 32 and the silicon material 33 is reduced, so that the thermal stress generated by the through silicon via 3 is reduced; secondly, the position where the original metal copper 32 and the silicon substrate plate 1 are extruded is transferred from the contact position of the silicon substrate plate 1 and the through silicon hole 3 to the inside of the through silicon hole 3, namely the contact position of the silicon material 33 and the metal copper 32, although thermal stress is still generated at the contact position of the silicon material 33 and the metal copper 32, the thermal stress at the contact position of the silicon substrate plate 1 and the through silicon hole 3 is reduced due to the buffering effect of the silicon material 33, and therefore the thermal stress existing in the silicon substrate is reduced.
Claims (5)
1. A silicon substrate based on low thermal stress through silicon vias is characterized by comprising a silicon substrate plate (1) with upper and lower surfaces respectively attached with a first insulating layer (2), wherein the silicon substrate plate (1) is provided with a plurality of through silicon vias (3) penetrating through the upper and lower plate surfaces, the through silicon vias (3) comprise cylindrical dielectric materials (31), hollow cylindrical metal copper (32), hollow cylindrical silicon materials (33) and hollow cylindrical second insulating layers (34) which are sequentially nested from inside to outside, and the thermal expansion coefficients of the silicon materials (33) and the silicon substrate plate (1) are the same; the upper bottom surface and the lower bottom surface of the metal copper (32) are respectively connected with a contact lead wire disc (4) made of metal materials;
the implementation method of the through silicon via (3) comprises the following steps: a circular through hole is etched on a silicon substrate plate (1), a dielectric material (31) is filled into the circular through hole, a first annular through hole is etched around the cylindrical surface of the dielectric material (31), metal copper (32) is filled into the circular through hole, a second annular through hole is etched around the cylindrical surface of the metal copper (32), a second insulating layer (34) is attached to the inner wall of the second annular through hole, and then silicon materials (33) are filled between the outer cylindrical surface of the metal copper (32) and the second insulating layer (34).
2. The low thermal stress through-silicon-via based silicon substrate according to claim 1, wherein the dielectric material (31) is silicon dioxide, silicon nitride or benzocyclobutene.
3. Silicon substrate based on low thermal stress through silicon vias according to claim 1, characterized in that the contact lead pads (4) are made of metallic copper, metallic aluminum or metallic tungsten.
4. The low thermal stress through-silicon-via based silicon substrate according to claim 1, wherein the through-silicon-via (3) has a central axis perpendicular to the plane of the silicon substrate plate (1).
5. The low thermal stress through-silicon via-based silicon substrate of claim 1, wherein the metallic copper (32), silicon material (33) and second insulating layer (34) have their central axes coincident with the central axis of the dielectric material (31).
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| CN202011477841.3A CN112599491A (en) | 2020-12-15 | 2020-12-15 | Silicon substrate based on low thermal stress through silicon via |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116259606A (en) * | 2023-05-15 | 2023-06-13 | 之江实验室 | TSV structure and preparation method thereof |
| CN116435290A (en) * | 2023-06-13 | 2023-07-14 | 中诚华隆计算机技术有限公司 | Three-dimensional stacking structure and stacking method of chips |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050121768A1 (en) * | 2003-12-05 | 2005-06-09 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
| CN102214624A (en) * | 2011-05-17 | 2011-10-12 | 北京大学 | Semiconductor structure with through holes and manufacturing method thereof |
| JP2016213349A (en) * | 2015-05-11 | 2016-12-15 | 国立研究開発法人産業技術総合研究所 | Through electrode and manufacturing method of through electrode and semiconductor device and manufacturing method of semiconductor device |
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| CN116259606A (en) * | 2023-05-15 | 2023-06-13 | 之江实验室 | TSV structure and preparation method thereof |
| CN116259606B (en) * | 2023-05-15 | 2023-08-11 | 之江实验室 | TSV structure and preparation method thereof |
| CN116435290A (en) * | 2023-06-13 | 2023-07-14 | 中诚华隆计算机技术有限公司 | Three-dimensional stacking structure and stacking method of chips |
| CN116435290B (en) * | 2023-06-13 | 2023-08-22 | 中诚华隆计算机技术有限公司 | Three-dimensional stacking structure and stacking method of chips |
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