CN111081632A - Silicon through hole structure for reducing thermal stress and manufacturing method thereof - Google Patents
Silicon through hole structure for reducing thermal stress and manufacturing method thereof Download PDFInfo
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- CN111081632A CN111081632A CN201911274573.2A CN201911274573A CN111081632A CN 111081632 A CN111081632 A CN 111081632A CN 201911274573 A CN201911274573 A CN 201911274573A CN 111081632 A CN111081632 A CN 111081632A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
Abstract
The invention provides a ring-shaped silicon through hole structure for reducing thermal stress and a manufacturing method thereof, wherein the ring-shaped silicon through hole structure comprises the following steps: manufacturing a metal gasket layer and an insulating medium layer on one side of a silicon substrate layer of a wafer; and manufacturing a through hole penetrating through the silicon substrate layer in the silicon substrate layer, and filling the organic polymer and the electroplated copper column in the through hole to form a through hole column. The through-hole pillar comprises an organic polymer and a copper pillar which is surrounded by the organic polymer and both ends of which are exposed outside the organic polymer; the through hole column is arranged in the through hole in a penetrating mode and is in contact with the inner side wall of the through hole column, the insulating medium layer and the metal gasket layer are arranged on one side of the silicon substrate layer, and one end of the copper column is in electrical contact with the metal gasket layer. The silicon through hole structure can effectively reduce the thermal stress between the silicon substrate and the copper column, and the manufacturing method has the advantages of strong process compatibility and high mechanical reliability and is widely applied to the field of 3D wafer level packaging.
Description
Technical Field
The invention relates to a through silicon via structure, in particular to a through silicon via structure for reducing thermal stress and a manufacturing method thereof.
Background
Through Silicon vias (TSV for short) are formed between chips or between wafers, and Through holes are formed in the vertical direction to connect the chips, so that the chips are interconnected. Compared with the conventional packaging technology, the through silicon via technology has the advantages of large stacking density in the three-dimensional direction, small outline size after packaging, low power consumption and the like, becomes the most potential electronic packaging technology at present, and is widely applied to various high-speed circuits and miniaturized systems.
Conventional through-silicon vias are formed by filling copper metal to form copper pillars and using silicon dioxide as an insulating layer between the copper and silicon substrates. Because the thermal expansion coefficient difference between copper and the silicon substrate is large, when the temperature rises, the thermal deformation of the copper column is synchronously enlarged, so that the silicon dioxide insulating layer and the silicon substrate are extruded, a large thermal stress is generated, the stability of the silicon through hole structure is deteriorated, and even the silicon through hole can not realize the chip interconnection function in serious conditions.
In the through silicon via structure in the prior art, air and an organic film are respectively used for replacing silicon oxide as an insulating medium, or a metal copper layer is used for replacing traditional solid filling copper, the schemes can reduce the thermal stress between copper and a silicon substrate to a certain extent, but the through silicon via structure has the defects of being not concise in process manufacturing, smaller in thermal deformation control range of a copper column, high in cost of an isolation layer metal material on the surface of the through silicon via copper layer, easy to influence the connection by the isolation layer material and the like.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a through silicon via structure for reducing thermal stress and a manufacturing method thereof, which are used for solving the defect of poor stability of the through silicon via caused by larger thermal stress along with the rise of temperature of the through silicon via in the traditional technology; and the method is also used for solving the defects of the prior art that the process is not concise in manufacturing, the range of the thermal deformation free area of the copper column is narrow and the connection of the silicon through hole is not tight.
In order to achieve the purpose, the invention adopts the following technical scheme on one hand:
a through silicon via structure for reducing thermal stress comprises a silicon substrate layer, an insulating medium layer, a metal gasket layer and a through hole column, wherein a through hole is formed in the silicon substrate layer, and the through hole column comprises an organic polymer and a metal connector which is surrounded by the organic polymer and two ends of which are exposed outside the organic polymer; the through hole column is arranged in the through hole in a penetrating mode and is in contact with the inner side wall of the through hole column, the insulating medium layer and the metal gasket layer are arranged on one side of the silicon substrate layer, and one end of the metal connector is in electrical contact with the metal gasket layer.
In another aspect, the present invention further provides a method for manufacturing a through silicon via structure with reduced thermal stress, including:
1) providing a silicon wafer, and manufacturing a metal gasket layer on one side of a silicon substrate layer of the silicon wafer;
2) manufacturing an insulating medium layer on one side of the silicon substrate layer, which is provided with the metal gasket layer;
3) constructing a through hole penetrating and communicating two opposite side surfaces in the silicon substrate layer;
4) arranging a through hole column in a through hole of the silicon substrate layer, wherein the through hole column comprises an organic polymer and a metal connector which is surrounded by the organic polymer and two ends of which are exposed outside the organic polymer; the through hole column is arranged in the through hole in a penetrating mode and is in contact with the inner side wall of the through hole column, and one end of the metal connector is in electrical contact with the metal gasket layer.
Compared with the prior art, the invention has the following beneficial effects:
according to the silicon through hole structure, when the temperature rises, the organic polymers arranged on the inner side and the outer side of the copper column provide larger free deformation areas for the thermal deformation of the copper column, the thermal deformation force of the copper column firstly extrudes the organic polymers on the inner side and the outer side, and when the thermal deformation force reaches the side wall of the silicon substrate through the organic polymers, the acting force is greatly reduced, so that the thermal stress between the silicon substrate and the copper column is effectively reduced.
Drawings
FIGS. 1 and 2 are a cross-sectional view and a top view, respectively, of a through-silicon via structure in an embodiment of the present invention;
fig. 3 and fig. 4 are a cross-sectional view and a top view, respectively, of a flow chart for fabricating a through-silicon via structure in an embodiment of the present invention.
In the figure: 10. a protective dielectric layer; 11. an intermetallic dielectric layer; 12. a metal gasket layer; 13. a silicon substrate layer; 14. an organic polymer; 15. copper column
Detailed Description
The invention is further described in detail below with reference to the accompanying drawings, and specific embodiments are given.
Referring to fig. 1 and 2, the invention provides a through silicon via structure for reducing thermal stress, which includes a silicon-based substrate layer 13, an insulating medium layer, a metal spacer layer 12 and a via post, wherein the silicon-based substrate layer is provided with a via hole, and the via post includes an organic polymer 14 and a metal connector surrounded by the organic polymer and having two ends exposed outside the organic polymer; the through hole column is arranged in the through hole in a penetrating mode and is in contact with the inner side wall of the through hole column, the insulating medium layer and the metal gasket layer 12 are arranged on one side of the silicon substrate layer 13, and one end of the metal connector is in electrical contact with the metal gasket layer 12.
Specifically, the organic polymer 14 includes two parts, namely an inner cylinder and an outer cavity, and the metal connector is interposed between the inner cylinder and the outer cavity of the organic polymer 13; the outer side wall of the outer cavity is in contact with the inner side wall of the silicon substrate layer 13, the inner side wall of the outer cavity is in contact with the outer side wall of the metal connector, and the inner side wall of the metal connector is in contact with the inner cylinder; the metal connector and the inner side wall of the via hole are mutually separated, and the inner cylinder and the outer cavity are mutually separated.
Specifically, the insulating dielectric layer comprises an intermetallic dielectric layer 11 and a protective dielectric layer 10, and both the intermetallic dielectric layer 11 and the protective dielectric layer 10 can be made of silicon dioxide, silicon nitride or silicon oxynitride material; the intermetallic dielectric layer 11 is located between the protective dielectric layer 10 and the silicon-based substrate layer 13, and the metal gasket layer 12 is located between the intermetallic dielectric layer 11 and the silicon-based substrate layer 13.
Preferably, the metal gasket layer 12 is disposed in the middle of one side of the silicon substrate layer 13, and the axis of the metal gasket layer is consistent with the axis of the via hole and the axis of the metal connector; the radial area of the metal gasket layer 12 at the end contacting the metal connector is larger than the radial area of the via hole at the side.
In the above scheme, the metal connector is a ring-shaped copper pillar 15, and the ring shape may be a circular ring shape or a square ring shape; the metal connector utilizes the annular structure, so that the connection area of the silicon through hole structure is increased, and the disconnection problem caused by a manufacturing process is effectively avoided; the organic Polymer 14 can be Polyimide (PI), Polymer or Benzocyclobutene (BCD), and has a thermal expansion coefficient comparable to that of a copper material by utilizing the particularly excellent characteristics and high-temperature resistance and thermal insulation of an insulating film such as polyimide, Polymer or benzocyclobutene, and the organic Polymer can be used as a substitute isolation layer of silicon dioxide, so that the device performance is better and the thermal stress is smaller; the organic polymer 14 is arranged on the inner side and the outer side of the copper column 15, when the temperature rises, the organic polymer provides a larger free deformation area for the thermal deformation of the copper column, the thermal deformation force of the copper column extrudes the organic polymer on two sides, and only a small thermal deformation force reaches the side wall of the silicon substrate, so that the thermal stress between the silicon substrate and the copper column is effectively reduced.
Referring to fig. 3 and 4, the present invention also provides a method for manufacturing a through silicon via structure with reduced thermal stress, including:
1) providing a silicon wafer, and manufacturing a metal gasket layer 12 on one side of a silicon substrate layer 13 of the silicon wafer;
2) manufacturing an insulating medium layer on one side of the silicon substrate layer 13, which is provided with the metal gasket layer 12;
3) constructing a through hole penetrating and communicating two opposite side surfaces in the silicon substrate layer;
4) arranging a through hole column in a through hole of the silicon substrate layer, wherein the through hole column comprises an organic polymer 14 and a metal connector which is surrounded by the organic polymer and two ends of the metal connector are exposed out of the organic polymer; the through hole column is penetratingly arranged in the through hole and is in contact with the inner side wall of the through hole, and one end of the metal connector is electrically contacted with the metal gasket layer 12.
Specifically, the metal pad layer 12 is formed by a first photolithography and a first etching process.
Specifically, the insulating dielectric layer is formed by sequentially depositing an intermetallic dielectric layer 11 and a protective dielectric layer 10 through a first chemical vapor deposition process.
Specifically, the via hole is formed by a second photolithography and a second etching process, and the time of the second etching process is controlled until the metal pad layer 12 in the via hole is exposed.
Specifically, the manufacturing steps of the through-hole column include:
1) depositing an organic polymer 14 in the through hole of the silicon substrate layer by utilizing a second chemical vapor deposition process;
2) carrying out third photoetching and third etching processes on the organic polymer to etch an annular through hole which penetrates through the organic polymer and is communicated with two opposite side surfaces of the organic polymer and has a certain thickness;
3) depositing a seed layer in the annular through hole by using a physical vapor deposition process, and then filling a metal thin film layer to form a through hole column prototype;
4) and carrying out a chemical mechanical grinding process on the through hole column prototype to expose the silicon substrate layer 13 and the through hole columns which are flush with the silicon substrate layer.
Preferably, the organic Polymer 14 may be Polyimide (PI), Polymer, or Benzocyclobutene (BCD).
Preferably, the seed layer can be made of Ta, TaN or Cu; the metal thin film layer is manufactured by electroplating a copper layer through electrochemical polishing (ECP), and a copper pillar 15 is formed.
In the scheme, the processes of deposition, photoetching, etching, electroplating, chemical mechanical grinding and the like are conventional process means and conventionally available process materials, so that the method has the advantages of strong compatibility with the conventional semiconductor process, high mechanical reliability and cost saving.
Finally, the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all of them should be covered in the claims of the present invention.
Claims (11)
1. A through silicon via structure for reducing thermal stress comprises a silicon substrate layer, an insulating medium layer, a metal gasket layer and a through hole column, wherein a through hole is formed in the silicon substrate layer; the through hole column is arranged in the through hole in a penetrating mode and is in contact with the inner side wall of the through hole column, the insulating medium layer and the metal gasket layer are arranged on one side of the silicon substrate layer, and one end of the metal connector is in electrical contact with the metal gasket layer.
2. The tsv structure of claim 1, wherein the organic polymer comprises two parts, namely an inner pillar and an outer cavity, and the metal connector is interposed between the inner pillar and the outer cavity; the outer side wall of the outer cavity is in contact with the inner side wall of the silicon substrate layer, the inner side wall of the outer cavity is in contact with the outer side wall of the metal connector, and the inner side wall of the metal connector is in contact with the inner cylinder; the metal connector and the inner side wall of the via hole are mutually separated, and the inner cylinder and the outer cavity are mutually separated.
3. The through-silicon-via structure for reducing thermal stress according to claim 1, wherein the insulating dielectric layer comprises an intermetallic dielectric layer and a protective dielectric layer, and the intermetallic dielectric layer and the protective dielectric layer are made of silicon dioxide, silicon nitride or silicon oxynitride; the intermetallic dielectric layer is positioned between the protective dielectric layer and the silicon substrate layer, and the metal gasket layer is positioned between the intermetallic dielectric layer and the silicon substrate layer.
4. A method for fabricating a thermal stress reduced through-silicon via structure according to any of claims 1-3, comprising:
s1, providing a silicon wafer, and manufacturing a metal gasket layer on one side of a silicon substrate layer of the silicon wafer;
s2, manufacturing an insulating medium layer on one side of the silicon substrate layer, where the metal gasket layer is arranged;
s3, constructing a through hole penetrating and communicating two opposite side surfaces in the silicon substrate layer;
s4, arranging a through hole column in the through hole of the silicon substrate layer, wherein the through hole column comprises an organic polymer and a metal connector which is surrounded by the organic polymer and two ends of which are exposed outside the organic polymer; the through hole column is arranged in the through hole in a penetrating mode and is in contact with the inner side wall of the through hole column, and one end of the metal connector is in electrical contact with the metal gasket layer.
5. The manufacturing method of claim 4, wherein in the step S1, the metal gasket layer is formed by a first photolithography and a first etching process.
6. The method of claim 4, wherein in step S2, the insulating dielectric layer is formed by depositing an inter-metal dielectric layer and a protective dielectric layer in sequence by a first chemical vapor deposition process.
7. The method as claimed in claim 4, wherein in the step S3, the via hole is formed by a second photolithography and a second etching process, and the time of the second etching process is controlled to expose the metal pad layer in the via hole.
8. The manufacturing method according to claim 4, wherein in the step S4, the step of manufacturing the through-hole pillar includes:
s01, depositing organic polymer in the via hole of the silicon substrate layer by using a second chemical vapor deposition process;
s02, carrying out third photoetching and third etching processes on the organic polymer, and etching an annular through hole which penetrates through the organic polymer and is communicated with two opposite side surfaces of the organic polymer and has a certain thickness;
s03, depositing a seed layer in the annular through hole by using a physical vapor deposition process, and filling a metal thin film layer to form a through hole column prototype;
and S04, carrying out chemical mechanical grinding process on the through hole column prototypes to expose the silicon-based substrate layer and the through hole columns which are flush with the silicon-based substrate layer.
9. The manufacturing method according to claim 8, wherein the organic Polymer is Polyimide (PI), Polymer, or Benzocyclobutene (BCD).
10. The manufacturing method according to claim 8, wherein the seed layer is Ta, TaN, or Cu.
11. The method of manufacturing of claim 8, wherein the metal film layer is formed by electro-chemical polishing (ECP) copper plating.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911274573.2A CN111081632A (en) | 2019-12-12 | 2019-12-12 | Silicon through hole structure for reducing thermal stress and manufacturing method thereof |
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| CN201911274573.2A CN111081632A (en) | 2019-12-12 | 2019-12-12 | Silicon through hole structure for reducing thermal stress and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112194095A (en) * | 2020-09-29 | 2021-01-08 | 中国航空工业集团公司雷华电子技术研究所 | Miniaturized radio frequency coaxial structure based on silicon-based MEMS technology and manufacturing method |
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Application publication date: 20200428 |