CN112599157B

CN112599157B - Three-dimensional memory and programming method thereof

Info

Publication number: CN112599157B
Application number: CN202011495919.4A
Authority: CN
Inventors: 刘红涛; 靳磊; 黄莹; 蒋颂敏; 黄德佳
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-12-17
Filing date: 2020-12-17
Publication date: 2022-05-27
Anticipated expiration: 2040-12-17
Also published as: CN112599157A

Abstract

The invention relates to a three-dimensional memory and a control method thereof. The three-dimensional memory includes a plurality of memory strings, each of the memory strings includes a plurality of memory cells, and the programming method of the three-dimensional memory includes: performing a first programming on a first memory cell of the plurality of memory cells using a first verify voltage; programming other memory cells of the plurality of memory cells with a first verify voltage and a second verify voltage; and performing a second programming of the first memory cell using the second verify voltage; wherein the first verify voltage is less than the second verify voltage. The three-dimensional memory and the programming method thereof increase the time interval between the first programming and the second programming of the first memory cell, and in the time interval, the charges at the shallow energy level in the first memory cell are leaked, so that the charges after the second programming are more at the deep energy level, thereby reducing the reduction of the reading window caused by the rapid charge loss.

Description

Three-dimensional memory and programming method thereof

Technical Field

The invention relates to the field of manufacturing of integrated circuits, in particular to a three-dimensional memory and a programming method thereof.

Background

In order to overcome the limitation of the two-dimensional memory device, a memory device having a three-dimensional (3D) structure, which increases integration density by arranging memory cells three-dimensionally over a substrate, has been developed and mass-produced in the industry. The 3D NAND flash memory is a three-dimensional memory device including a large number of memory cells. Fig. 1A is a schematic structural diagram of a memory cell of a 3D NAND flash memory. The structure of the memory cell is generally divided into a conductive layer 110, a tunneling layer 120, a memory layer 130, and a blocking layer 140 from the channel 101 to the gate, as shown in fig. 1A. When writing data, charges are injected from the conductive layer 110 to the storage layer 130 through the tunneling layer 120 under the strong electric field. The memory layer 130 has a large number of traps in which charges are trapped, and the deeper the energy level of the traps, the better the charge retention characteristics. However, in practice, the trap level is deep or shallow, and the trap of the shallow level has poor charge storage characteristics, and thus charge leakage is likely to occur. Still some charges, such as the charge 102 shown in fig. 1A, are trapped in the traps of the tunneling layer 120 during writing, where the retention characteristics are poor, and the charge 102 will leave the tunneling layer 120 and return to the conductive layer within a short time after programming, resulting in a low threshold voltage shift.

Fig. 1B is a schematic diagram of threshold shift due to rapid charge loss. The diagram is an example of a technique that includes 16 different program states QLC. The horizontal axis represents the threshold voltage Vt, and the vertical axis represents the number of memory cells. The solid line L1 represents the threshold voltage distribution just after the end of programming, and the broken line L2 represents the threshold voltage distribution after a certain time (less than 1s) has elapsed. It is apparent that the dotted line L2 drifts to a low voltage and the threshold voltage distribution is broadened. For QLC technology, the read window is inherently small, and the fast charge loss further reduces the read window.

Disclosure of Invention

The invention provides a three-dimensional memory with an improved read window and a programming method thereof.

The present invention is directed to a method for programming a three-dimensional memory, wherein the three-dimensional memory includes a plurality of memory strings, each of the memory strings includes a plurality of memory cells, and the method includes: performing a first programming on a first memory cell of the plurality of memory cells using a first verify voltage; programming other memory cells of the plurality of memory cells with a first verify voltage and a second verify voltage; and performing a second programming of the first memory cell using the second verify voltage; wherein the first verify voltage is less than the second verify voltage.

In an embodiment of the present invention, the step of programming the other memory cells of the plurality of memory cells by using the first verify voltage and the second verify voltage further includes: performing the first programming on a third memory cell among the other memory cells using the first verify voltage; performing the first programming on a fourth memory cell adjacent to the third memory cell in the memory string using the first verify voltage; and performing the second programming on the third memory cell using the second verify voltage.

In an embodiment of the present invention, the first programming and the second programming are based on incremental step pulses, wherein a pulse step size of the first programming is larger than a pulse step size of the second programming.

In an embodiment of the invention, the first programmed memory cells are programmed to N programmed states, the second programmed memory cells are programmed to 2N programmed states, and N is a positive integer.

In an embodiment of the invention, the first programmed memory cells are programmed to N programmed states, and the second programmed memory cells are programmed to N programmed states, where N is a positive integer.

In an embodiment of the present invention, each memory cell is at a respective cell depth in the memory string, the programming method includes: and programming operation is carried out on the page of the memory cells at the same cell depth layer by layer through the word lines along the extension direction of the channel structure of the memory string.

The present invention further provides a three-dimensional memory for solving the above technical problems, comprising: a memory cell array comprising a plurality of memory strings, each of the memory strings extending vertically above a substrate and comprising a plurality of memory cells arranged vertically in series; a controller configured to: performing a first programming on a first memory cell of the plurality of memory cells using a first verify voltage; programming other memory cells of the plurality of memory cells with a first verify voltage and a second verify voltage; and performing a second programming of the first memory cell using the second verify voltage; wherein the first verify voltage is less than the second verify voltage.

In an embodiment of the invention, the controller is further configured to: performing the first programming on a third memory cell among the other memory cells using the first verify voltage; performing the first programming on a fourth memory cell adjacent to the third memory cell in the memory string using the first verify voltage; and performing the second programming on the third memory cell using the second verify voltage.

In an embodiment of the invention, the memory further comprises a plurality of word lines, each of the word lines being coupled to a page of memory cells at a same cell depth, wherein each memory cell is at a corresponding cell depth in the memory string.

In an embodiment of the invention, the other memory unit is located above the first memory unit in the memory string.

In an embodiment of the invention, the fourth storage unit is located above the third storage unit in the memory string.

In an embodiment of the present invention, each of the memory cells is a multi-level cell (MLC).

In one embodiment of the present invention, the three-dimensional memory is a 3D NAND flash memory.

According to the three-dimensional memory and the programming method thereof, the first programming is firstly carried out on the first memory cell, then the other memory cells are programmed, and then the second programming is carried out on the first memory cell, so that the time interval between the first programming and the second programming of the first memory cell is increased, and in the time interval, the charges at the shallow energy level in the first memory cell leak out, so that the charges after the second programming are more at the deep energy level, and the reading window caused by rapid charge loss can be reduced to be small.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1A is a schematic diagram of a 3D NAND flash memory cell structure;

FIG. 1B is a schematic diagram of threshold shift due to rapid charge loss;

FIG. 2 is an exemplary flow chart of a method of programming a three-dimensional memory according to one embodiment of the invention;

FIG. 3 is a schematic diagram of a memory string of a three-dimensional memory according to an embodiment of the invention;

FIG. 4 is a schematic diagram of a memory string of a three-dimensional memory according to an embodiment of the invention;

FIG. 5 is a diagram illustrating threshold voltage distributions of memory cells of a programming method according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating threshold voltage distributions of memory cells of a programming method according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of the improvement of threshold voltage distribution obtained by the programming method of the three-dimensional memory according to the present invention;

FIG. 8 is a block diagram of a three-dimensional memory according to one embodiment of the invention;

FIG. 9 is a circuit schematic of a memory block that can be used with embodiments of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited.

The term "three-dimensional (3D) memory device" as used herein refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," e.g., NAND strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertically" means nominally perpendicular to a lateral surface of a substrate.

As used herein, the term "substrate" refers to a material upon which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

The term "layer" as used in this application refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, which may include one or more layers therein, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.

Fig. 2 is an exemplary flowchart of a programming method of a three-dimensional memory according to an embodiment of the present invention. The three-dimensional memory comprises a plurality of memory strings, and each memory string comprises a plurality of memory units. Referring to fig. 2, the programming method of this embodiment includes:

step S210: performing a first programming on a first memory cell of the plurality of memory cells using a first verify voltage;

step S220: programming other memory cells of the plurality of memory cells with a first verify voltage and a second verify voltage; and

step S230: performing a second programming on the first memory cell using a second verify voltage; wherein the first verify voltage is less than the second verify voltage.

FIG. 3 is a diagram of a memory string of a three-dimensional memory according to an embodiment of the invention. The programming method of fig. 2 is described below in conjunction with fig. 3.

Referring to fig. 3, the memory string 300 includes a channel structure 310 and a multi-layer gate layer 320 penetrated by the channel structure 310. It is understood that the multi-layer gate layers 320 are respectively connected to Word Lines (WL) of the three-dimensional memory, and voltages can be applied to the respective gate layers 320 through the word lines to perform programming, reading, erasing, and the like. Each layer of gate layer 320 corresponds to a memory cell. In fig. 3, a memory cell currently performing a program operation is denoted by C. The memory cell WLn is connected to an nth word line.

The invention does not limit the location of the memory cell WLn in the memory string 300.

Referring to fig. 3, in step S210, a first program is performed on the first memory cell C1 using a first verify voltage Vverify 1. Here, the first memory cell C1 may be any memory cell in a memory string that can be used for programming. The first memory cell C1 is connected to the nth word line WLn.

In step S220, other memory cells of the plurality of memory cells are programmed using the first and second verify voltages Vverify1 and Vverify 2. The other memory cells herein refer to other memory cells than the first memory cell C1, such as C2, …, Cx +1 shown in fig. 3, which are connected to the word lines WLn +1, …, WLn + x, respectively. The value of x is related to the number of layers of the three-dimensional memory. The gate layer 320 is also included below the gate layer of the first memory cell C1 in fig. 3, and the gate layer 320 may correspond to a bottom select gate of the three-dimensional memory.

In step S230, the first memory cell C1 is second programmed with the second verify voltage Vverify 2.

In steps S210-S230, the first verify voltage Vverify1 is less than the second verify voltage Vverify 2.

The first programming and the second programming in the programming method of the present invention are different in the program verification voltage used. The second programming makes the threshold voltage distribution of the memory cells subjected to the second programming narrower relative to the threshold voltage distribution of the memory cells subjected to the first programming due to the use of the larger second verify voltage Vverify 2. Therefore, the second programming is also referred to as fine programming, and the first programming is correspondingly referred to as coarse programming.

According to the embodiment shown in FIG. 2, the first memory cell C1 is first programmed, then the other memory cells are programmed, and then the first memory cell C1 is second programmed. According to this programming method, a time interval between the first programming and the second programming of the first memory cell C1 is increased, and during this time, charges at a shallow level in the first memory cell C1 are leaked out, so that charges after the second programming are more at a deep level, and thus a read window due to a rapid charge loss can be reduced to be small.

The present invention does not limit the programming manner of the other memory cells in step S220, and any general programming method can be adopted.

In some embodiments, the programming other memory cells of the plurality of memory cells with the first and second verify voltages in step S220 of fig. 2 includes:

step S221: performing a first programming on a third memory cell among the other memory cells using a first verify voltage Vverify 1;

step S222: first programming a fourth memory cell adjacent to the third memory cell in the memory string using a first verify voltage Vverify 1; and

step S223: the third memory cell is second programmed using a second verify voltage Vverify 2.

FIG. 4 is a diagram of a memory string of a three-dimensional memory according to an embodiment of the invention. The memory string shown in fig. 4 may be part of the memory string shown in fig. 3. The third memory cell and the fourth memory cell both belong to the other memory cells shown in fig. 3.

Referring to fig. 4, in step S221, the third memory cell D1 is first programmed with a first verify voltage Vverify 1. The third memory cell D1 is connected to the mth word line WLm. The third memory cell D1 in fig. 4 may be located anywhere in the memory string.

In step S222, a fourth memory cell D2 adjacent to the third memory cell D1 in the memory string is first programmed using a first verify voltage Vverify 1. The fourth memory cell D2 represents the next memory cell to be programmed after the first programming of the third memory cell D1 is performed.

In the example shown in fig. 4, the fourth memory cell D2 is located above the third memory cell D1 in the extending direction of the channel structure 410, and when programming the three-dimensional memory, the memory cells in the gate layer are programmed layer by layer from bottom to top through the word lines along the extending direction of the channel structure 410.

In other embodiments, the fourth memory cell D2 may be located below the third memory cell D1 in the extending direction of the channel structure 410.

In some embodiments, each memory cell is at a respective cell depth in the memory string, the programming method of the present invention comprising: along the extending direction of the channel structure of the memory string, the programming operation is carried out to the page of the memory cells at the same cell depth layer by layer through the word lines.

In step S223, after the first programming is performed on the fourth memory cell D2, the third memory cell D1 is second programmed using the second verify voltage Vverify 2.

After steps S221-S223, the programming process for third memory cell D1 is complete. In the subsequent programming process, with the selected memory cell as the third memory cell D1, steps S221 to S223 are performed to complete the programming of the selected memory cell.

It is to be understood that the above-mentioned "first", "second", "third" and "fourth" are not limited to a specific location of the memory unit, nor to only one memory unit.

In some embodiments, the first programming and the second programming are both based on incremental step pulses (ISPP), wherein the pulse step size of the first programming is greater than the pulse step size of the second programming. According to these embodiments, the pulse step size for the second programming is smaller, and accordingly the programming accuracy is higher. Therefore, the second programming adopts a larger second verification voltage and a smaller pulse step size, so that the precision of the second programming can be further improved, and a narrower threshold voltage distribution can be obtained.

In some embodiments, the first programmed plurality of memory cells are programmed to N programmed states and the second programmed plurality of memory cells are programmed to 2N programmed states, N being a positive integer.

The number of bits stored in each memory cell is not limited by the present invention. The present specification takes a QLC (quadra Level cell) with a memory bit number of 4 as an example, and the QLC has 16 program states.

FIG. 5 is a diagram illustrating threshold voltage distributions of memory cells according to a programming method of the present invention. Referring to fig. 5, four threshold voltage distribution diagrams, I1, I2, I3, and I4, are included, and all of the four threshold voltage distribution diagrams are threshold voltage distributions of a plurality of memory cells on a memory page corresponding to a certain word line WLn. Where I1 indicates the initial state, programming has not begun, and the memory cells are in the erased state E0.

I2 indicates that after the first programming, the memory cells are programmed to N-8 programmed states, P0-P7.

I3 shows that after the first programming, the programming states of the memory cells corresponding to the word line WLn +1 are still 8.

I4 shows the memory cells corresponding to word line WLn after the second programming, the memory cells are programmed to 16 program states, P0-P15.

In some embodiments, the first programmed plurality of memory cells are programmed to N programmed states and the second programmed plurality of memory cells are programmed to N programmed states, N being a positive integer.

FIG. 6 is a diagram illustrating threshold voltage distributions of memory cells according to a programming method of the present invention. Referring to fig. 6, four threshold voltage distributions, J1, J2, J3 and J4, are included, and the four threshold voltage distributions are threshold voltage distributions of a plurality of memory cells on a memory page corresponding to a word line WLn. Where J1 indicates the initial state, programming has not begun, and the memory cells are all in the erased state E0.

J2 indicates that after the first programming of the memory cells, the memory cells are programmed to N-16 programmed states, P0-P15.

J3 shows threshold voltage distributions of a plurality of memory cells corresponding to word line WLn after first programming of the memory cell corresponding to word line WLn + 1.

J4 represents the threshold voltage distribution of the memory cells corresponding to word line WLn after the second programming.

Fig. 5 and 6 are examples only, and so on for the case where the number of bits stored in a memory cell is equal to 1, 2, 3 bits.

FIG. 7 is a schematic diagram of the improvement of threshold voltage distribution obtained by the programming method of the three-dimensional memory according to the present invention. Referring to fig. 7, a threshold voltage distribution of a plurality of memory cells corresponding to a word line WLn after the first programming is completed is shown; the dotted line and the solid line represent threshold voltage distribution conditions of a plurality of memory cells corresponding to the word line WLn after a period of time (less than 1 second) by adopting a common layer-by-layer programming method instead of the programming method of the invention; the thick solid line represents the threshold voltage distribution of a plurality of memory cells corresponding to the word line WLn after a period of time (less than 1 second) by using the programming method of the present invention. Obviously, by adopting the programming method of the invention, the threshold voltage distribution is narrowed, and the reading wide opening is increased.

FIG. 8 is a block diagram of a three-dimensional memory according to an embodiment of the invention. The aforementioned programming method of the three-dimensional memory according to the present invention can be applied to the three-dimensional memory according to this embodiment, and therefore, the aforementioned drawings and descriptions can be applied to the three-dimensional memory according to the present invention.

Referring to fig. 8, the three-dimensional memory includes a memory cell array 810 and a controller 820. The memory cell array 810 includes a plurality of memory strings, each memory string extending vertically above a substrate and including a plurality of memory cells arranged vertically in series. The controller 820 is configured to: first programming a first memory cell of the plurality of memory cells using a first verify voltage Vverify 1; programming other memory cells of the plurality of memory cells using a first verify voltage Vverify1 and a second verify voltage Vverify 2; and second programming the first memory cell using a second verify voltage Vverify 2; wherein the first verify voltage Vverify1 is less than the second verify voltage Vverify 2.

In some embodiments, the controller 820 is further configured to: performing a first programming on a third memory cell among the other memory cells using a first verify voltage Vverify 1; first programming a fourth memory cell adjacent to the third memory cell in the memory string using a first verify voltage Vverify 1; and second programming the third memory cell using a second verify voltage Vverify 2.

The controller 820 can adopt the programming method of the three-dimensional memory of the present invention to realize the above functions, so that the foregoing figures and descriptions can be used to explain the specific functions of the controller 820 of the three-dimensional memory of the present invention, and the same contents will not be expanded.

In the present embodiment, each memory cell included in the memory cell array 810 may be a single-level memory cell SLC in which 1-bit data is stored, or a multi-level memory cell (MLC) in which 2-bit or more data may be stored, such as MLC, TLC, QLC, and the like, or any combination of a single-level memory cell and a multi-level memory cell. Preferably, each of the memory cells is a multi-level cell (MLC).

In some embodiments, the first programming and the second programming are both based on incremental step pulses, wherein the pulse step size for the first programming is greater than the pulse step size for the second programming.

In the present embodiment, memory cells in the memory cell array 810 may be connected to word lines WL and bit lines BL. Meanwhile, the memory cell array 810 may also be connected to other selection lines such as a string selection line SSL, a ground selection line GSL, and the like. Specifically, the memory cell array 810 may be connected to a word line decoder 850 via a word line WL or a select line (SSL and/or GSL), and further connected to a voltage generator 860. The memory cell array 810 may be connected to a bit line decoder 830 via a bit line BL and further connected to an input/output (I/O) circuit 840. Controller 820 is coupled to bit line decoder 830, I/O circuit 840, word line decoder 850, and voltage generator 860, respectively.

When one or more memory cells are to be erased, programmed, read/written, or verified, the controller 820 can send the addresses of the one or more memory cells to the bit line decoder 830 and the word line decoder 850, and then be addressed by the bit line BL via the bit line decoder 830 and the word line WL via the word line decoder 850.

In some embodiments, the functions of the bit line decoder 830 and the word line decoder 850 may be implemented by a unified address decoder. The address decoder may also include components such as an address buffer.

The I/O circuit 840 may receive data from the controller 820 and/or the outside and store the received data in the memory cell array 810 for a write operation, on the one hand, and may read data from the memory cell array 810 and output the read data to the controller 820 and/or the outside for a read operation, on the other hand.

The voltage generator 860 may generate various voltages for performing operations of erasing, programming, reading, writing, verifying, and the like on the memory cell array 810 in response to a control signal from the controller 820. Specifically, the voltage generator 860 may generate a word line voltage, such as a program voltage (or a write voltage), a program inhibit voltage, a read voltage, a verify voltage, and the like. The voltage generator 860 may generate a bit line voltage, such as a bit line force voltage or an inhibit voltage. In an embodiment of the present invention, the voltage generator 860 may generate the first verify voltage Vverify1 and the second verify voltage Vverify2, etc., as described above. The controller 820 may also control the pulse step size for the first programming and the pulse step size for the second programming at the time of incremental step pulse programming.

The controller 820 may output control signals to the bit line decoder 830, the I/O circuit 840, the word line decoder 850, and the voltage generator 860. For example, controller 820 may output voltage control signals to voltage generator 860, word line addresses to word line decoder 850, bit line addresses to bit line decoder 830, write data to I/O circuit 840 and read data from I/O circuit 840.

In some embodiments, the controller 820 controls the bit line decoder 830 to select some bit lines BL and controls the word line decoder 850 to select some bit lines WL, and the voltage generator 860 applies a certain voltage to these bit lines BL and word lines WL. For example, during a read operation, a read voltage may be applied to a selected word line WL, and for a memory cell inhibited from being read, a read inhibit voltage may be applied to an unselected bit line BL. During a program operation, a program voltage and a verify voltage may be applied to a selected word line WL, and a program inhibit voltage may be applied to unselected bit lines BL.

The controller 820 of the embodiment of the present invention may further include a processor, an I/O interface, and the like. The control logic of controller 820 to bit line decoder 830, I/O circuit 840, word line decoder 850, and voltage generator 860 is not limited to that described above. The controller 820 may also implement any other logic control functions for the non-volatile memory as will be appreciated by those skilled in the art.

In some embodiments, the controller 820 may instruct the memory cell array 810 to perform desired memory operations based on software.

In an embodiment of the present invention, the memory strings extend vertically above the substrate. The substrate may be a Silicon substrate (Si), a Germanium substrate (Ge), a Silicon Germanium substrate (SiGe), a Silicon On Insulator (SOI), a Germanium On Insulator (GOI), or the like. In some embodiments, the substrate may also be a substrate comprising other elemental or compound semiconductors, such as GaAs, InP, SiC, or the like. But also a stacked structure such as Si/SiGe or the like. Other epitaxial structures may also be included, such as Silicon Germanium On Insulator (SGOI) and the like. In some embodiments, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers, among others. The substrate may have undergone some necessary processing, such as having formed the common active region and having undergone necessary cleaning, etc.

A stack structure, which may be a stack of alternating first and second material layers, is included over the substrate. The first material layer and the second material layer may be selected from materials and include at least one insulating dielectric such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and the like, and combinations thereof. The first material layer and the second material layer have different etching selectivity. For example, a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, or the like. The deposition method of the first material layer and the second material layer of the stack structure may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), Atomic Layer Deposition (ALD), or a physical vapor deposition method such as Molecular Beam Epitaxy (MBE), thermal oxidation, evaporation, sputtering, and the like, among various methods thereof. In an embodiment of the invention, the first material layer may be a gate layer, and the second material layer is a dielectric layer. The gate layer may be formed after removing the dummy gate layer. The material for the gate sacrificial layer may be, for example, a silicon nitride layer. The material for the gate layer may be a conductive material such as tungsten, cobalt, copper, nickel, etc., or may be polysilicon, doped silicon, or any combination thereof. The material for the dielectric layer may be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like.

In an embodiment of the invention, the material of the substrate is, for example, silicon. The first material layer and the second material layer are, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, a stacked structure may be formed by alternately depositing silicon nitride and silicon oxide on a substrate in sequence by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable deposition methods.

Although exemplary configurations of the initial semiconductor structure are described herein, it will be appreciated that one or more features may be omitted, substituted, or added to the semiconductor structure. For example, various well regions may be formed in the substrate as desired. In addition, the materials of the various layers illustrated are merely exemplary, e.g., the substrate may also be other silicon-containing substrates, such as SOI (silicon on insulator), SiGe, Si: C, etc. The gate layer may also be other conductive layers such as tungsten, cobalt, nickel, etc. The second material layer may also be other dielectric materials such as aluminum oxide, hafnium oxide, tantalum oxide, and the like.

A channel structure corresponding to the memory cell may be formed in a channel hole vertically passing through the stack structure, and thus the channel structure may be cylindrical. The channel structure may include a channel layer and a memory layer. In the overall view, the memory layer and the channel layer are arranged in sequence from the outside to the inside along the radial direction of the channel structure. The memory layer may include a blocking layer, a charge trapping layer, and a tunneling layer sequentially disposed from outside to inside in a radial direction of the channel structure. A filling layer can be arranged in the channel layer. The filler layer may function as a support. The material of the filling layer may be silicon oxide. The filling layer can be solid or hollow without affecting the reliability of the device. The formation of the channel structure may be accomplished using one or more thin film deposition processes, such as ALD, CVD, PVD, the like, or any combination thereof.

In some embodiments, the three-dimensional memory of the present invention further comprises a plurality of word lines, each word line coupled to a page of memory cells at the same cell depth, wherein each memory cell is at a corresponding cell depth in the memory string.

FIG. 9 is a circuit schematic of a memory block that can be used with embodiments of the present invention. The memory cell array 810 shown in fig. 8 may include several memory blocks. Referring to fig. 9, where mc (memory cell) represents a memory cell, each memory cell has a corresponding cell depth. For example, memory cell MC in fig. 9 is in the gate layer to which word line WL8 is coupled. The memory string STR connects a plurality of memory cells in series along the increasing number of layers of word lines WL1-WL 8. Memory cells at the same cell depth are in the same PAGE (PAGE). The controller 820 generates voltages to be applied to the respective word lines according to the set control voltage generator 860, thereby controlling the voltages applied to each memory cell.

Each string STR may further include a string selection transistor SST and a ground selection transistor GST respectively connected to both ends of the memory cells MC connected in series. CSL is a common source line. The number of memory strings STR, the number of word lines WL, and the number of bit lines BL may vary according to embodiments.

The illustration in fig. 9 is merely an example, and is not intended to limit the specific structure of the three-dimensional memory, the number of layers of word lines, and the like of the present invention.

In some embodiments, the other memory cells are located above the first memory cell in the memory string.

In some embodiments, the fourth memory cell is located above the third memory cell in the memory string.

The upper direction here refers to the direction along which the channel structure extends.

In some embodiments, the three-dimensional memory of the present invention is a 3D NAND flash memory.

According to the three-dimensional memory, after the first programming is carried out on the selected first storage unit, other storage units are programmed, then the second programming is carried out on the first storage unit, so that charges in the shallow energy level in the first storage unit are leaked, more charges after the second programming are in the deep energy level, and therefore the reduction of a reading window caused by rapid charge loss can be reduced.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims

1. A programming method of a three-dimensional memory including a plurality of memory strings each including a plurality of memory cells, comprising:

performing a first programming on a first memory cell of the plurality of memory cells using a first verify voltage;

after the first programming of the first memory cell is completed, programming other memory cells except the first memory cell among the plurality of memory cells using a first verify voltage and a second verify voltage; and

after the programming of the other memory cells is completed, second programming the first memory cell with the second verify voltage;

wherein the first verify voltage is less than the second verify voltage.

2. The programming method of claim 1, wherein the other memory cells include at least a third memory cell and a fourth memory cell adjacent to each other, and the programming the other memory cells of the plurality of memory cells using the first verify voltage and the second verify voltage comprises:

performing the first programming on the third memory cell using the first verify voltage;

performing the first programming on the fourth memory cell using the first verify voltage; and

performing the second programming on the third memory cell using the second verify voltage.

3. The programming method of claim 1 or 2, wherein the first programming and the second programming are both based on incremental step pulses, wherein a pulse step size of the first programming is larger than a pulse step size of the second programming.

4. The programming method according to claim 1 or 2, wherein the plurality of memory cells subjected to the first programming are programmed to N program states, and the plurality of memory cells subjected to the second programming are programmed to 2N program states, N being a positive integer.

5. The programming method according to claim 1 or 2, wherein the plurality of memory cells subjected to the first programming are programmed to N program states, and the plurality of memory cells subjected to the second programming are programmed to N program states, N being a positive integer.

6. The programming method of claim 1, wherein each memory cell is at a respective cell depth in the memory string, the programming method comprising: and programming operation is carried out on the page of the memory cells at the same cell depth layer by layer through the word lines along the extension direction of the channel structure of the memory string.

7. A three-dimensional memory, comprising:

a memory cell array comprising a plurality of memory strings, each of the memory strings extending vertically above a substrate and comprising a plurality of memory cells arranged vertically in series;

a controller configured to: performing a first programming on a first memory cell of the plurality of memory cells using a first verify voltage;

wherein the first verify voltage is less than the second verify voltage.

8. The three-dimensional memory according to claim 7, wherein the other memory cells include at least a third memory cell and a fourth memory cell adjacent to each other, the controller further configured to: performing the first programming on the third memory cell using the first verify voltage;

9. The three-dimensional memory of claim 7 or 8, wherein the first programming and the second programming are both based on incremental step pulses, wherein a pulse step size of the first programming is greater than a pulse step size of the second programming.

10. The three-dimensional memory according to claim 7 or 8, wherein the plurality of memory cells subjected to the first programming are programmed to N program states, and the plurality of memory cells subjected to the second programming are programmed to 2N program states, N being a positive integer.

11. The three-dimensional memory according to claim 7 or 8, wherein the plurality of memory cells subjected to the first programming are programmed to N program states, and the plurality of memory cells subjected to the second programming are programmed to N program states, N being a positive integer.

12. The three-dimensional memory of claim 7, further comprising a plurality of word lines, each coupled to a page of memory cells at a same cell depth, wherein each memory cell is at a corresponding cell depth in the memory string.

13. The three-dimensional memory according to claim 7, wherein the other memory cells are located above the first memory cell in the memory string.

14. The three-dimensional memory according to claim 8, wherein the fourth memory cell is located above the third memory cell in the memory string.

15. The three-dimensional memory of claim 7, wherein each of the memory cells is a multi-level cell (MLC).

16. The three-dimensional memory according to claim 7, wherein the three-dimensional memory is a 3DNAND flash memory.