CN112802507B

CN112802507B - Three-dimensional memory and control method thereof

Info

Publication number: CN112802507B
Application number: CN202110096756.0A
Authority: CN
Inventors: 黄莹; 罗哲; 刘红涛; 李达
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-01-25
Filing date: 2021-01-25
Publication date: 2022-11-29
Anticipated expiration: 2041-01-25
Also published as: CN112802507A; CN115579030A

Abstract

The invention relates to a control method of a three-dimensional memory, wherein the three-dimensional memory comprises a plurality of memory strings, each memory string comprises a plurality of memory units, each memory unit comprises a first memory unit, and the method comprises the following steps: providing a first read sensing current to a selected first memory cell when performing a read operation, wherein the first read sensing current is less than a verify sensing current provided to the selected first memory cell during a program verify phase; and providing a first read voltage to the selected first memory cell, wherein the first read voltage includes applying a first bias voltage at a first read voltage level of the selected first memory cell. According to the three-dimensional memory and the control method thereof, threshold voltage distribution broadening and drifting caused by BPD effect can be effectively reduced, a reading window is enlarged, reading interference is avoided, and the reliability of the three-dimensional memory is improved.

Description

Three-dimensional memory and control method thereof

Technical Field

The invention relates to the field of manufacturing of integrated circuits, in particular to a three-dimensional memory and a control method thereof.

Background

In order to overcome the limitation of the two-dimensional memory device, memory devices having a three-dimensional (3D) structure have been developed and mass-produced in the industry, which increases integration density by three-dimensionally arranging memory cells over a substrate. With the development of multi-value memory technology, the number of stacked layers of a three-dimensional memory device is increased, and the problems of structure and electrical characteristics of the three-dimensional memory device are also increased. Among them, BPD (Background Pattern Dependency) is a problem with an increased number of layers. BPD refers to the forward shift of the drain resistance change of a previously programmed memory cell in the threshold voltage (Vt) of the memory cell during the program verify phase and the read phase. Because of the difference between the programming patterns (Pattern) of different memory strings, the Vt variation caused by the drain resistance variation is also different, which causes the distribution of threshold voltage to be widened, thereby reducing the read window.

Disclosure of Invention

The invention aims to provide a three-dimensional memory for improving BPD effect influence and a control method thereof.

The present invention has been made to solve the above-mentioned problems, and an aspect of the present invention is a method for controlling a three-dimensional memory, the three-dimensional memory including a plurality of memory strings, each of the memory strings including a plurality of memory cells, the memory cells including a first memory cell, the method including: providing a first read sensing current to a selected first memory cell when performing a read operation, wherein the first read sensing current is less than a verify sensing current provided to the selected first memory cell during a program verify phase; and providing a first read voltage to the selected first memory cell, wherein the first read voltage comprises applying a first bias voltage at a first read voltage level of the selected first memory cell.

In one embodiment of the present invention, the memory cells further include a second memory cell, wherein the first memory cell is programmed before the second memory cell in a program operation, the method further comprising: while performing a read operation, providing a second read sensing current to a selected second memory cell, wherein the second read sensing current is less than the verify sensing current; and providing a second read voltage to the selected second memory cell, the second read voltage comprising applying a second bias voltage at a second read voltage level of the second memory cell.

In an embodiment of the present invention, the memory cell further includes a second memory cell, wherein the first memory cell is programmed before the second memory cell in a programming operation, the method further comprising: while performing a read operation, providing a second read sense current to a selected second memory cell, wherein the second read sense current is equal to the verify sense current; and providing a second read voltage to the selected second memory cell, the second read voltage comprising applying a second bias voltage at a second read voltage level of the second memory cell.

In an embodiment of the present invention, the first bias voltage is calculated according to a threshold voltage distribution of the selected first memory cell, and the second bias voltage is calculated according to a threshold voltage distribution of the selected second memory cell.

In an embodiment of the present invention, the plurality of first memory cells include one or more first sub memory cells and one or more second sub memory cells, wherein the first sub memory cells are programmed before the second sub memory cells in a program operation, the method further includes: in performing a read operation, a third read sense current is provided to a selected first sub memory cell and a fourth read sense current is provided to a selected second sub memory cell, wherein the third read sense current is less than the fourth read sense current, and the third read sense current and the fourth read sense current are both less than the verify sense current.

In an embodiment of the present invention, the read operation is performed after the programming of the plurality of memory cells is completed.

The present invention further provides a three-dimensional memory for solving the above technical problems, comprising: a memory cell array comprising a plurality of memory strings, each of the memory strings extending vertically above a substrate and comprising a plurality of memory cells arranged vertically in series, the memory cells comprising a first memory cell; a controller configured to: providing a first read sensing current to a selected first memory cell when performing a read operation, wherein the first read sensing current is less than a verify sensing current provided to the selected first memory cell during a program verify phase; and providing a first read voltage to the selected first memory cell, wherein the first read voltage includes applying a first bias voltage at a first read voltage level of the selected first memory cell.

In one embodiment of the present invention, the memory cell further includes a second memory cell, wherein the first memory cell is programmed before the second memory cell in a program operation, the controller is further configured to: while performing a read operation, providing a second read sense current to a selected second memory cell, wherein the second read sense current is less than the verify sense current; and providing a second read voltage to the selected second memory cell, the second read voltage comprising applying a second bias voltage at a second read voltage level of the second memory cell.

In an embodiment of the invention, the controller is further configured to: while performing a read operation, providing a second read sense current to a selected second memory cell, wherein the second read sense current is equal to the verify sense current; and providing a second read voltage to the selected second memory cell, the second read voltage comprising applying a second bias voltage at a second read voltage level of the second memory cell.

In an embodiment of the invention, the controller is further configured to: the first bias voltage is calculated according to the threshold voltage distribution of the selected first memory cell, and the second bias voltage is calculated according to the threshold voltage distribution of the selected second memory cell.

In an embodiment of the invention, the plurality of first memory cells includes one or more first sub memory cells and one or more second sub memory cells, wherein the first sub memory cells are programmed before the second sub memory cells in a program operation, the controller is further configured to: in performing a read operation, a third read sense current is provided to a selected first sub memory cell and a fourth read sense current is provided to a selected second sub memory cell, wherein the third read sense current is less than the fourth read sense current, and the third read sense current and the fourth read sense current are both less than the verify sense current.

In an embodiment of the invention, the controller is further configured to: the read operation is performed after the programming of the plurality of memory cells is completed.

In an embodiment of the invention, further comprising a bit line and a word line connected to the memory cell, the controller is further configured to: a read sense current is provided to the memory cell through the bit line and a read voltage is provided to the memory cell through the word line.

In an embodiment of the invention, the first storage unit is located close to a substrate of the three-dimensional memory, and the second storage unit is located far away from the substrate.

In one embodiment of the present invention, the three-dimensional memory is a 3D NAND flash memory.

According to the three-dimensional memory and the control method thereof, the first reading sensing current I _ read1 which is smaller than the verification sensing current I _ verify is provided for the pre-programmed memory cell which is greatly influenced by the BPD, the threshold voltage distribution broadening and drifting caused by the BPD effect can be effectively reduced, the reading window is enlarged, the reading conduction voltage of the non-selected memory cell does not need to be increased, the further reading interference is avoided, and the reliability of the three-dimensional memory is improved.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1A is a schematic diagram of a memory string in a three-dimensional memory;

FIG. 1B is a diagram illustrating a structure of a memory string in a three-dimensional memory;

FIG. 1C is a schematic diagram of threshold voltage distribution broadening due to the BPD effect;

FIG. 2A is a schematic diagram of a read operation performed on a memory cell in the memory string shown in FIG. 1A;

FIG. 2B is a schematic diagram of a read operation performed on a memory cell in the memory string shown in FIG. 1A;

FIG. 2C is a schematic diagram of the threshold voltage distribution after the read operation of FIG. 2B;

FIG. 3 is an exemplary flow chart of a method of controlling a three-dimensional memory according to an embodiment of the invention;

FIG. 4 is an Id-Vg curve for a three-dimensional memory;

fig. 5 is an exemplary flowchart of a control method of a three-dimensional memory according to another embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating an effect of a control method of a three-dimensional memory according to an embodiment of the invention;

FIG. 7 is a block diagram of a three-dimensional memory according to one embodiment of the invention;

FIG. 8 is a circuit schematic of a memory block that can be used with embodiments of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and in the claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to include the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" are intended to cover only the explicitly identified steps or elements as not constituting an exclusive list and that the method or apparatus may comprise further steps or elements.

In describing embodiments of the present invention in detail, the cross-sectional views illustrating the device structures are not enlarged partially in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatial relationship terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of above and below. Other orientations of the device are possible (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited.

The term "three-dimensional (3D) memory device" as used herein refers to a semiconductor device having vertically oriented memory cell transistor strings (referred to herein as "memory strings," e.g., NAND strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertically" means nominally perpendicular to a lateral surface of a substrate.

As used herein, the term "substrate" refers to a material upon which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

The term "layer" as used in this application refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along the tapered surface. The substrate may be a layer, which may include one or more layers therein, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Flowcharts are used herein to illustrate the operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. At the same time, other operations are either added to or removed from these processes.

Fig. 1A is a schematic structural diagram of a memory string in a three-dimensional memory. Referring to fig. 1A, a memory string 110 corresponds to a channel structure in a three-dimensional memory, and has a plurality of memory cells 120 along an extending direction of the memory string, and the memory cells 120 at different positions correspond to different layers in the three-dimensional memory. In the three-dimensional memory, a word line is connected to a gate layer corresponding to each memory cell 120, and a word line voltage is applied to a gate of a transistor corresponding to the memory cell 120. Referring to FIG. 1A, the top of the memory string is a bit line selector switch BLS, which is connected to the drain of the memory cell; the bottom is an array common source ACS connected to the source of the memory cell. Fig. 1A shows an example of a programming operation performed on a memory cell 121, and a letter P in an oval shape representing the memory cell 121 indicates that the memory cell 121 has undergone the programming operation. The plurality of memory cells 122 above the memory cell 121 are in an erased state (Erase).

FIG. 1B is a diagram illustrating a structure of a memory string in a three-dimensional memory. Referring to FIG. 1B, memory cell 121 and the other memory cells 122 located above it in memory string 110 are both in a programmed state, indicating that they have passed through the programming phase.

Fig. 1C is a schematic diagram of threshold voltage distribution broadening due to the BPD effect. Referring to fig. 1C, the abscissa represents the threshold voltage Vt of the memory cell, and the ordinate represents the number of memory cells. Fig. 1C illustrates four threshold voltage distribution ranges of a memory cell, which are an E state, a P1 state, a P2 state, and a P3 state, by taking a multi-level cell (MLC) technology as an example. Wherein, the E state is an erasing state corresponding to the erasing action, and the corresponding data format is 11; the P1 state, P2 state and P3 state are all programming states corresponding to a programming action, and correspond to data formats 00, 01 and 10, respectively.

As shown in FIG. 1C, the solid black line 131 corresponds to the threshold voltage distribution curve of the memory cell 121 when the memory cell 122 is in the erased state as shown in FIG. 1A, and the dashed black line 132 corresponds to the threshold voltage distribution curve of the memory cell 121 when both the

memory cells

121 and 122 are in the programmed state as shown in FIG. 1B. It can be understood that there is a certain distance between the threshold voltage distribution curves of adjacent states, and the distance represents the read space for the lower state in the adjacent states, and if the distance is larger, the read space is large, and errors are not easy to occur; if the distance is small, the reading space is small, and errors are easy to occur. When the

memory cells

121 and 122 are both in the programmed state, the read space is reduced and read disturb is easily caused due to the shift and spread of the threshold voltage caused by the BPD effect.

Fig. 2A is a schematic diagram of a read operation performed on a memory cell in the memory string shown in fig. 1A. Referring to fig. 2A, after a program operation is performed on all memory cells on a memory string, when a read operation is performed on a selected memory cell 221, a read voltage Vread is applied to the memory cell 221, and a read turn-on voltage Vread _ pass is applied to other non-selected memory cells 222.

FIG. 2B is a schematic diagram of a read operation performed on a memory cell in the memory string shown in FIG. 1A. In order to improve the influence of the BPD effect on the threshold voltage, referring to fig. 2B, when the read voltage Vread is applied to the memory cell 221, a voltage greater than the read on voltage Vread _ pass, which is Vread _ pass + Δ as shown in fig. 2B, is applied to the non-selected memory cell 222, that is, the voltage is greater than the read on voltage Vread _ pass by Δ.

FIG. 2C is a schematic diagram of threshold voltage distributions after the read operation of FIG. 2B. Wherein the solid black line 231 corresponds to the threshold voltage distribution curve of the memory cell 121 after the read operation shown in fig. 1A, and the dashed black line 232 corresponds to the threshold voltage distribution curve of the memory cell 121 after the read operation shown in fig. 1B. It is apparent that the problem of threshold voltage distribution broadening is improved to some extent after the read operation process of fig. 2B. However, since the read turn-on voltage in the read operation causes a weak programming effect on the non-selected memory cells, the weak programming effect is more significant when the read turn-on voltage is increased, and serious read disturbance is caused after a plurality of read operations.

Fig. 3 is an exemplary flowchart of a control method of a three-dimensional memory according to an embodiment of the present invention. The three-dimensional memory includes a plurality of memory strings, each memory string including a plurality of memory cells including one or more first memory cells. Referring to fig. 3, the control method of the embodiment includes:

step S310: providing a first read sensing current to a selected first memory cell when performing a read operation, wherein the first read sensing current is less than a verify sensing current provided to the selected memory cell during a program verify phase; and

step S320: a first read voltage is provided to a selected first memory cell, wherein the first read voltage includes applying a first bias voltage at a first read voltage level of the selected memory cell.

In some embodiments, the read operation in step S310 is performed after the programming of the plurality of memory cells is completed. That is, after all the memory cells are programmed, the read operation is performed on the programmed memory cells.

FIG. 4 is an Id-Vg curve for a three-dimensional memory. Where Id represents a drain current provided at a bit line of the memory string, and Vg represents a gate voltage provided from a word line of the three-dimensional memory. Referring to fig. 1A, 1B and 4, a first curve 410 corresponds to the situation shown in fig. 1A, i.e., the memory cell 121 is programmed, and the memory cells 122 above the memory cell 121 are in an erased state. The second curve 420 corresponds to the situation shown in fig. 1B, i.e. memory cell 121 and the other memory cells 122 located above it are already in the programmed state. The difference between the first curve 410 and the second curve 420 is due to the BPD effect.

As shown in FIG. 4, in the program verification phase and the read phase, a read sensing current I _ read1 is supplied to the selected memory cell, and at this time, the threshold voltage corresponding to the first curve 410 is Vt11, and the threshold voltage corresponding to the second curve 420 is Vt12, the threshold voltage is spread due to the BPD effect to Vt12-Vt11. Also referring to FIG. 4, the read sensing current I _ read2 is supplied to the selected memory cell, I _ read2< I _ read1, where the threshold voltage corresponding to the first curve 410 is Vt21, and the threshold voltage corresponding to the second curve 420 is Vt22, the threshold voltage spreads to Vt22-Vt21 due to the BPD effect. Obviously, vt12-Vt11> Vt22-Vt21. That is, when the read sense current provided is small, the threshold voltage spread due to the BPD effect is also small.

Assume that a verify sense current I _ verify is supplied to a selected memory cell during a program verify phase.

According to the principle shown in FIG. 4, the present invention provides a first read sensing current I _ read1 to the selected first memory cell in step S310, wherein the first read sensing current I _ read1 is smaller than the verification sensing current I _ verify. In this way, the extent of threshold voltage spread caused to the memory cell by the BPD effect can be reduced. And, during a read operation, a normal turn-on voltage is still provided for unselected memory cells without increasing the turn-on voltage, thereby avoiding a weak programming effect.

Meanwhile, a first read voltage for the selected first memory cell is adjusted at step S320. Assuming that the normal first read voltage level of the first memory cell is V _ read10, the first read voltage V _ read11= V _ read10+ V _ offset1 is provided to the first memory cell in step S320. Where V _ offset1 is the first offset voltage. The threshold voltage of the memory cell may widen or shift due to the BPD effect or other reasons, and if the original first read voltage level V _ read10 is continuously used to read the data in the memory cell, the Fail Bit Count (FBC) may be increased. Therefore, the original first read voltage level V _ read10 is already not applicable to the first memory cell. The original first reading voltage level V _ read10 is adjusted by the first bias voltage, so that the first reading voltage V _ read11 is more suitable for the first memory cell after programming, and the FBC is reduced.

The invention does not limit the positive or negative of the first offset voltage V _ offset1, and the first read voltage V _ read11 can be higher than the first read voltage level V _ read10 or the first read voltage V _ read11 can be lower than the first read voltage level V _ read10 by applying the first offset voltage V _ offset1.

In some embodiments, the first offset voltage V _ offset1 is calculated according to the threshold voltage distribution of the selected first memory cell. An actual threshold voltage distribution of the first memory cell is obtained through measurement, an appropriate first read voltage V _ read11 is determined according to the threshold voltage distribution, and a first offset voltage V _ offset1 is determined according to a difference between the appropriate first read voltage V _ read11 and an original first read voltage level V _ read10.

In some embodiments, the memory cell further includes a second memory cell, wherein the first memory cell is programmed before the second memory cell in a programming operation. That is, the first memory cell is a memory cell that is programmed first with respect to the second memory cell. In these embodiments, the first memory cell represents a first-programmed memory cell and the second memory cell represents a second-programmed memory cell.

According to the embodiment shown in FIG. 3, the first read sensing current I _ read1, which is smaller than the verify sensing current I _ verify, is provided to the first memory cell programmed first. The magnitude of the second read sensing current supplied to the post-programmed second memory cell is not limited.

In some embodiments, the second read sense current provided to the second memory cell is less than or equal to the verify sense current I _ verify.

Referring to fig. 3, in some embodiments, the control method of the present invention further comprises:

step S330: when the read operation is executed, providing a second read sensing current to the selected second memory cell, wherein the second read sensing current is smaller than the verification sensing current; and

step S340: providing a second read voltage to the selected second memory cell, the second read voltage comprising applying a second bias voltage at a second read voltage level for the second memory cell.

In these embodiments, both the first read sense current I _ read1 and the second read sense current I _ read2 are less than the verify sense current I _ verify. Thereby reducing the threshold voltage spread of both the selected first memory cell and the second memory cell.

The relative magnitudes of the first read sense current I _ read1 and the second read sense current I _ read2 are not limited by the present invention. The first read sensing current I _ read1 may be greater than, equal to, or less than the second read sensing current I _ read2.

Similarly to step S320, the threshold voltage of the second memory cell after multiple programming shifts or widens, so that the read voltage is adjusted in step S340, such that the second read voltage V _ read21 applies the second offset voltage V _ offset2 on the basis of the second read voltage level V _ read20 of the second memory cell, i.e. V _ read21= V _ read20+ V _ offset2.

The invention does not limit the sign of the second offset voltage V _ offset2, and the second read voltage V _ read21 can be higher than the second read voltage level V _ read20 by applying the second offset voltage V _ offset2, and the second read voltage V _ read21 can also be lower than the second read voltage level V _ read20.

In some embodiments, the second offset voltage V _ offset2 is calculated according to the threshold voltage distribution of the selected second memory cell. An actual threshold voltage distribution of the second memory cells is obtained through measurement, an appropriate second read voltage V _ read21 is determined according to the threshold voltage distribution, and a second offset voltage V _ offset2 is determined according to a difference between the appropriate second read voltage V _ read21 and the original second read voltage level V _ read20.

In some embodiments, the second read sense current provided to the second memory cell is equal to the verify sense current I _ verify.

For a three-dimensional memory, the memory cells programmed first are more affected by the BPD effect, and the memory cells programmed later are less affected by the BPD effect than the memory cells programmed first. Therefore, the memory cells programmed first and the memory cells programmed later can be controlled separately.

Fig. 5 is an exemplary flowchart of a control method of a three-dimensional memory according to another embodiment of the present invention. Referring to fig. 5, the control method of this embodiment further includes:

step S510: providing a first read sensing current to a selected first memory cell when performing a read operation, wherein the first read sensing current is less than a verify sensing current provided to the selected memory cell during a program verify phase;

step S520: providing a first read voltage to a selected first memory cell, wherein the first read voltage comprises applying a first bias voltage at a first read voltage level of the selected memory cell;

step S530: while performing the read operation, providing a second read sensing current to the selected second memory cell, wherein the second read sensing current is equal to the verify sensing current; and

step S540: providing a second read voltage to the selected second memory cell, the second read voltage comprising applying a second bias voltage at a second read voltage level of the second memory cell.

Steps S510 and S520 are the same as steps S310 and S320 of the embodiment shown in fig. 3, respectively.

In these embodiments, the first storage unit and the second storage unit are treated differently. Since the second memory cell that is programmed later is less affected by the BPD effect, the normal verify sensing current is adopted as the second read sensing current in step S530, i.e., I _ read2= I _ verify. Accordingly, the second read voltage V _ read2 of the selected second memory cell is adjusted in step S540 such that it applies the second offset voltage V _ offset2 on the basis of the second read voltage level V _ read20 of the second memory cell, i.e. V _ read21= V _ read20+ V _ offset2.

In some embodiments, the second offset voltage V _ offset2 is calculated according to the threshold voltage distribution of the selected second memory cell. An actual threshold voltage distribution of the second memory cells is obtained by measurement, an appropriate second read voltage V _ read21 is determined based on the threshold voltage distribution, and a second offset voltage V _ offset2 is determined based on a difference between the appropriate second read voltage V _ read21 and the original second read voltage level V _ read20.

It should be noted that the second read voltage V _ read21 in the embodiments shown in fig. 3 and fig. 5 is determined according to the actual measurement result, that is, the second read voltage V _ read21 in step S340 and step S540 may be equal or different.

In some embodiments, the plurality of first memory cells includes one or more first sub memory cells and one or more second sub memory cells, wherein the first sub memory cells are programmed before the second sub memory cells in a program operation, and the control method of the present invention further includes:

when a read operation is performed, a third read sensing current I _ read3 is supplied to a selected first sub memory cell, and a fourth read sensing current I _ read4 is supplied to a selected second sub memory cell, wherein the third read sensing current I _ read3 is less than the fourth read sensing current I _ read4, and the third read sensing current I _ read3 and the fourth read sensing current I _ read4 are both less than the verification sensing current I _ verify.

In the embodiments, the first memory unit is further divided, wherein the first sub-memory unit is programmed first in the programming process, and is greatly influenced by the BPD effect; the second sub-memory cell is programmed later and is less affected by the BPD effect.

According to the embodiment, different read sensing currents are respectively provided for the first sub-memory cell and the second sub-memory cell, and the memory cell can be accurately controlled according to different degrees of the memory cell influenced by the BPD effect.

In some embodiments, the magnitude of the sense current is controlled by controlling the discharge time of the bit line. The discharge time is long, and the sensing current is small; the discharge time is short and the sensing current is large. By accurately controlling the magnitude of the induced current provided to different memory cells, unnecessary time waste can be avoided, and efficiency can be improved.

In some embodiments, the first sub-memory cells and/or the second sub-memory cells may be further subdivided, so that the plurality of first memory cells may be divided into a plurality of memory cell groups, the programming order of the memory cell groups is different, the read sense current provided to the memory cell programmed first is smaller, the read sense current provided to the memory cell programmed later is larger, and the read sense currents are smaller than the verify sense current I _ verify.

Fig. 6 is a schematic diagram illustrating an effect of a control method of a three-dimensional memory according to an embodiment of the invention. Threshold voltage distribution curves of the memory cell in three cases are shown, wherein a first curve 610 is a normal threshold voltage distribution curve in a case where the memory cell is not affected by the BPD; the second curve 620 is a threshold voltage distribution curve when the memory cell is affected by the BPD and the read sense current provided to the memory cell is equal to the verify sense current I _ verify; the third curve 630 is a threshold voltage distribution curve when the memory cell is affected by the BPD and the read sense current provided to the memory cell is less than the verify sense current I _ verify. A third curve 630 is the threshold voltage distribution curve of the memory cell after the control method of the present invention is applied.

Referring to the upper graph of fig. 6, the horizontal axis represents the threshold voltage Vt, and the vertical axis represents the number of memory cells (not shown). The figure is suitable for comparing a first curve 610 and a second curve 620, it being clear that the second curve 620 is broadened and shifted with respect to the first curve 610.

Referring to the lower graph of fig. 6, the horizontal axis represents the threshold voltage Vt, and the vertical axis represents the number of memory cells (not shown). This figure is suitable for comparing the first curve 610 with the third curve 630, and it is clear that the third curve 630 is also shifted with respect to the first curve 610, and that the third curve 630 is broadened to a lesser extent with respect to the second curve 620.

Referring to the superimposed graph of the left second curve 620 and the third curve 630 in fig. 6, it can be seen that the third curve 630 is broadened to a lesser extent than the second curve 620.

Therefore, according to the control method of the present invention, the first read sensing current I _ read1 smaller than the verification sensing current I _ verify is provided to the pre-programmed memory cell greatly affected by BPD, which can effectively reduce the threshold voltage distribution broadening and drifting caused by the BPD effect, increase the read window, and avoid further read disturb because the read turn-on voltage of the non-selected memory cell does not need to be increased.

FIG. 7 is a block diagram of a three-dimensional memory according to an embodiment of the invention. The aforementioned control method of the three-dimensional memory according to the present invention can be used to control the three-dimensional memory according to this embodiment, and therefore the aforementioned drawings and descriptions can be used to describe the three-dimensional memory according to the present invention.

Referring to fig. 7, the three-dimensional memory includes a memory cell array 710 and a controller 720. The memory cell array 710 includes a plurality of memory strings, each memory string extending vertically above a substrate and including a plurality of memory cells arranged vertically in series. The plurality of memory cells includes one or more first memory cells. The controller 720 is configured to provide a first read sensing current to the selected first memory cell when performing a read operation, wherein the first read sensing current is less than a verify sensing current provided to the selected first memory cell during a program verify phase; and providing a first read voltage to the selected first memory cell, wherein the first read voltage includes applying a first bias voltage at a first read voltage level of the selected first memory cell.

In some embodiments, the memory cells further include a second memory cell, wherein the first memory cell is programmed before the second memory cell in the programming operation, the controller 720 is further configured to: when the read operation is executed, providing a second read sensing current to the selected second memory cell, wherein the second read sensing current is smaller than the verification sensing current; and providing a second read voltage to the selected second memory cell, the second read voltage comprising applying a second bias voltage at a second read voltage level for the second memory cell.

In some embodiments, controller 720 is further configured to: while performing a read operation, providing a second read sensing current to the selected second memory cell, wherein the second read sensing current is equal to the verify sensing current; and providing a second read voltage to the selected second memory cell, the second read voltage comprising applying a second bias voltage at a second read voltage level for the second memory cell.

In some embodiments, controller 720 is further configured to: a first bias voltage is calculated based on a threshold voltage distribution of the selected first memory cell, and a second bias voltage is calculated based on a threshold voltage distribution of the selected second memory cell.

In some embodiments, the plurality of first memory cells includes one or more first sub-memory cells and one or more second sub-memory cells, wherein the first sub-memory cells are programmed before the second sub-memory cells in the programming operation, the controller 720 is further configured to: when a read operation is performed, a third read sensing current is supplied to a selected first sub memory cell, and a fourth read sensing current is supplied to a selected second sub memory cell, wherein the third read sensing current is less than the fourth read sensing current, and the third read sensing current and the fourth read sensing current are both less than the verify sensing current.

In some embodiments, the controller is further configured to: the read operation is performed after the programming of the plurality of memory cells is completed.

In some embodiments, the three-dimensional memory of the present invention includes bit lines and word lines connected to the memory cells, the controller further configured to: a read sense current is provided to the memory cell through the bit line and a read voltage is provided to the memory cell through the word line. The read sense current here includes a first read sense current and a second read sense current, and the read voltage includes a first read voltage and a second read voltage.

The controller 720 can adopt the control method of the three-dimensional memory of the present invention to realize the above functions, so that the foregoing figures and descriptions can be used to describe the specific functions of the controller 720 of the three-dimensional memory of the present invention, and the same contents will not be expanded.

In the present embodiment, each memory cell included in the memory cell array 710 may be a single-level memory cell SLC in which 1-bit data is stored, or a multi-level memory cell (MLC) in which 2-bit or more data may be stored, such as MLC, TLC, QLC, and the like, or any combination of a single-level memory cell and a multi-level memory cell.

In the present embodiment, memory cells in the memory cell array 710 may be connected to word lines WL and bit lines BL. Meanwhile, the memory cell array 710 may also be connected to other selection lines such as a string selection line SSL, a ground selection line GSL, and the like. Specifically, the memory cell array 710 may be connected to a word line decoder 750 via a word line WL or a select line (SSL and/or GSL), and further connected to a voltage generator 760. The memory cell array 710 may be connected to a bit line decoder 730 via a bit line BL and further connected to an input/output (I/O) circuit 740. The controller 720 is connected to the bit line decoder 730, the I/O circuit 740, the word line decoder 750, and the voltage generator 760, respectively.

When one or more memory cells are to be erased, programmed, read/written, or verified, the controller 720 may send the address of the one or more memory cells to the bit line decoder 730 and the word line decoder 750, and then be addressed by the bit line BL via the bit line decoder 730 and the word line WL via the word line decoder 750.

In some embodiments, the functions of the bit line decoder 730 and the word line decoder 750 may be implemented by a unified address decoder. The address decoder may also include components such as an address buffer.

The I/O circuit 740 may receive data from the controller 720 and/or the outside and store the received data in the memory cell array 710 for a write operation, on the one hand, and may read data from the memory cell array 710 and output the read data to the controller 720 and/or the outside for a read operation, on the other hand.

The voltage generator 760 may generate various voltages for performing operations of erasing, programming, reading, writing, and verifying, etc. on the memory cell array 710 in response to a control signal from the controller 720. Specifically, the voltage generator 760 may generate word line voltages, such as a program voltage (or a write voltage), a program inhibit voltage, a read voltage, a verify voltage, and the like. Voltage generator 760 may generate a bit line voltage, such as a bit line force voltage or an inhibit voltage. In an embodiment of the invention, the voltage generator 760 may generate the first read sensing current I _ read1, the second read sensing current I _ read2, the verification sensing current I _ verify, the first read voltage level V _ read10, the first read voltage V _ read11, the second read voltage level V _ read20, the second read voltage V _ read21, and the like as described above.

The controller 720 may output control signals to the bit line decoder 730, the I/O circuit 740, the word line decoder 750, and the voltage generator 760. For example, controller 720 may output voltage control signals to voltage generator 760, word line addresses to word line decoder 750, bit line addresses to bit line decoder 730, write data to I/O circuit 740, and read data from I/O circuit 740.

In some embodiments, the controller 720 controls the bit line decoder 730 to select some bit lines BL and controls the word line decoder 750 to select some bit lines WL, and applies certain voltages to these bit lines BL and word lines WL through the voltage generator 760. For example, during a read operation, a read voltage may be applied to a selected word line WL, and for a memory cell inhibited from being read, a read inhibit voltage may be applied to an unselected bit line BL. During a program operation, a program voltage and a verify voltage may be applied to a selected word line WL, and a program inhibit voltage may be applied to unselected bit lines BL.

The controller 720 of the present embodiment may also include a processor, I/O interface, and the like. The control logic of the controller 720 to the bit line decoder 730, the I/O circuit 740, the word line decoder 750, and the voltage generator 760 is not limited to the above. The controller 720 may also implement any other logic control functions for the non-volatile memory as would be understood by one of ordinary skill in the art.

In some embodiments, the controller 720 may instruct the memory cell array 710 to perform a desired memory operation based on software.

In an embodiment of the present invention, the memory strings extend vertically above the substrate. The substrate may be a Silicon substrate (Si), a Germanium substrate (Ge), a Silicon Germanium substrate (SiGe), a Silicon On Insulator (SOI), a Germanium On Insulator (GOI), or the like. In some embodiments, the substrate may also be a substrate comprising other elemental or compound semiconductors, such as GaAs, inP, or SiC, among others. But also a stacked structure such as Si/SiGe or the like. Other epitaxial structures may also be included, such as Silicon Germanium On Insulator (SGOI) and the like. In some embodiments, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers, among others. The substrate may have undergone some necessary processing such as the formation of the common active area and the necessary cleaning, etc.

A stack structure, which may be a stack of alternating first and second material layers, is included over the substrate. The first material layer and the second material layer may be of a material selected from the group consisting of silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and the like, and combinations thereof, and at least include an insulating dielectric. The first material layer and the second material layer have different etching selectivity. For example, a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, or the like may be used. The deposition method of the first material layer and the second material layer of the stack structure may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic Layer Deposition (ALD), or a physical vapor deposition method such as Molecular Beam Epitaxy (MBE), thermal oxidation, evaporation, sputtering, and the like, among various methods thereof. In an embodiment of the invention, the first material layer may be a gate layer, and the second material layer is a dielectric layer. The gate layer may be formed after removing the dummy gate layer. The material for the gate sacrificial layer may be, for example, a silicon nitride layer. The material for the gate layer may be a conductive material such as tungsten, cobalt, copper, nickel, etc., or may be polysilicon, doped silicon, or any combination thereof. The material for the dielectric layer may be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like.

In an embodiment of the invention, the material of the substrate is, for example, silicon. The first material layer and the second material layer are for example a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, a stacked structure may be formed by alternately depositing silicon nitride and silicon oxide on a substrate in sequence by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or other suitable deposition methods.

Although exemplary constructions of the initial semiconductor structure are described herein, it will be appreciated that one or more features may be omitted, substituted, or added to the semiconductor structure. For example, various well regions may be formed in the substrate as desired. In addition, the materials of the various layers illustrated are merely exemplary, e.g., the substrate may also be other silicon-containing substrates, such as SOI (silicon on insulator), siGe, si: C, etc. The gate layer may also be other conductive layers such as tungsten, cobalt, nickel, etc. The second material layer may also be other dielectric materials such as aluminum oxide, hafnium oxide, tantalum oxide, etc.

A channel structure corresponding to the memory cell may be formed in a channel hole vertically passing through the stack structure, and thus the channel structure may be cylindrical. The channel structure may include a channel layer and a memory layer. Viewed from the whole, the memory layer and the channel layer are arranged in sequence from the outside to the inside in the radial direction of the channel structure. The memory layer may include a blocking layer, a charge trapping layer, and a tunneling layer sequentially disposed from outside to inside in a radial direction of the channel structure. A filling layer can be arranged in the channel layer. The filling layer may function as a support. The material of the filling layer may be silicon oxide. The filling layer can be solid or hollow without affecting the reliability of the device. The formation of the channel structure may be accomplished using one or more thin film deposition processes, such as ALD, CVD, PVD, the like, or any combination thereof.

FIG. 8 is a circuit schematic of a memory block that can be used with embodiments of the present invention. The memory cell array 710 shown in fig. 7 may include several memory blocks. Referring to fig. 7, where MC (Memory Cell) represents one Memory Cell, each Memory Cell has a corresponding Cell depth. For example, memory cell MC in fig. 7 is in the gate layer to which word line WL8 is coupled. The memory string STR connects a plurality of memory cells in series along a direction in which the number of layers of the word lines WL1 to WL8 increases. Memory cells at the same cell depth are in the same PAGE (PAGE). The controller 720 generates voltages to be applied to the respective word lines according to the set control voltage generator 760, thereby controlling the voltages applied to each memory cell.

Each string STR may further include a string selection transistor SST and a ground selection transistor GST respectively connected to both ends of the memory cells MC connected in series. CSL is a common source line. The number of memory strings STR, the number of word lines WL, and the number of bit lines BL may vary according to embodiments.

The illustration in fig. 8 is merely an example, and is not intended to limit the specific structure of the three-dimensional memory of the present invention, the number of layers of word lines, and the like.

The present invention does not limit the specific number of the first memory cells and the second memory cells. Can be determined according to actual conditions.

In some embodiments, a first memory cell of the plurality of memory cells of the present invention is located near a substrate of the three-dimensional memory and a second memory cell is located far from the substrate.

In some embodiments, the program operation for the three-dimensional memory is performed in an arrangement order of word lines. For example, programming can begin with a word line near the substrate and continue to a word line at the drain side of the memory block. Thus, the first memory cell is close to the substrate and the second memory cell is far from the substrate.

In some embodiments, the three-dimensional memory of the present invention is a 3D NAND flash memory.

The three-dimensional memory of the invention provides the first reading sensing current I _ read1 which is smaller than the verification sensing current I _ verify to the pre-programmed memory cell greatly influenced by BPD, can effectively reduce the threshold voltage distribution broadening and drifting caused by BPD effect, increases the reading window, avoids further reading interference and improves the reliability of the three-dimensional memory because the reading conducting voltage of the non-selected memory cell does not need to be increased.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims

1. A method of controlling a three-dimensional memory, the three-dimensional memory including a plurality of memory strings, each of the memory strings including a plurality of memory cells, the memory cells including a first memory cell, the method comprising:

providing a first read sensing current to a selected first memory cell when performing a read operation, wherein the first read sensing current is less than a verify sensing current provided to the selected first memory cell during a program verify phase; and

providing a first read voltage to the selected first memory cell, wherein the first read voltage comprises applying a first bias voltage at a first read voltage level of the selected first memory cell.

2. The method of claim 1, wherein the memory cells further include a second memory cell, wherein the first memory cell is programmed before the second memory cell in a program operation, the method further comprising:

while performing a read operation, providing a second read sensing current to a selected second memory cell, wherein the second read sensing current is less than the verify sensing current; and

providing a second read voltage to the selected second memory cell, the second read voltage comprising applying a second bias voltage at a second read voltage level of the second memory cell.

3. The method of claim 1, wherein the memory cells further include a second memory cell, wherein the first memory cell is programmed before the second memory cell in a program operation, the method further comprising:

while performing a read operation, providing a second read sense current to a selected second memory cell, wherein the second read sense current is equal to the verify sense current; and

4. The control method according to claim 2 or 3, wherein the first bias voltage is calculated from the threshold voltage distribution of the selected first memory cell, and the second bias voltage is calculated from the threshold voltage distribution of the selected second memory cell.

5. The method of any of claims 1 to 3, wherein the plurality of first memory cells includes one or more first sub memory cells and one or more second sub memory cells, wherein the first sub memory cells are programmed prior to the second sub memory cells in a programming operation, the method further comprising:

when a read operation is performed, a third read sensing current is provided to a selected first sub memory cell, and a fourth read sensing current is provided to a selected second sub memory cell, wherein the third read sensing current is less than the fourth read sensing current, and the third read sensing current and the fourth read sensing current are both less than the verify sensing current.

6. The control method of claim 1, wherein the read operation is performed after the programming of the plurality of memory cells is completed.

7. A three-dimensional memory, comprising:

a memory cell array comprising a plurality of memory strings, each of the memory strings extending vertically above a substrate and comprising a plurality of memory cells arranged vertically in series, the memory cells comprising a first memory cell;

a controller configured to: providing a first read sensing current to a selected first memory cell when performing a read operation, wherein the first read sensing current is less than a verify sensing current provided to the selected first memory cell during a program verify phase; and

8. The three-dimensional memory of claim 7, wherein the memory cells further comprise a second memory cell, wherein the first memory cell is programmed prior to the second memory cell in a programming operation, the controller further configured to: while performing a read operation, providing a second read sense current to a selected second memory cell, wherein the second read sense current is less than the verify sense current; and

9. The three-dimensional memory according to claim 7, wherein the controller is further configured to: while performing a read operation, providing a second read sense current to a selected second memory cell, wherein the second read sense current is equal to the verify sense current; and

10. The three-dimensional memory according to claim 8 or 9, wherein the controller is further configured to: the first bias voltage is calculated according to the threshold voltage distribution of the selected first memory cell, and the second bias voltage is calculated according to the threshold voltage distribution of the selected second memory cell.

11. The three-dimensional memory according to any one of claims 7 to 9, wherein the plurality of first memory cells includes one or more first sub memory cells and one or more second sub memory cells, wherein the first sub memory cells are programmed prior to the second sub memory cells in a program operation, the controller further configured to:

12. The three-dimensional memory according to claim 7, wherein the controller is further configured to: the read operation is performed after the programming of the plurality of memory cells is completed.

13. The three-dimensional memory of claim 7, further comprising bit lines and word lines connected to the memory cells, the controller further configured to: a read sense current is provided to the memory cell through the bit line and a read voltage is provided to the memory cell through the word line.

14. The three-dimensional memory according to claim 8 or 9, wherein the first storage unit is located at a position close to a substrate of the three-dimensional memory, and the second storage unit is located at a position far from the substrate.

15. The three-dimensional memory of claim 7, wherein the three-dimensional memory is a 3D NAND flash memory.