TWI791309B - Non-volatile memory and programming method thereof - Google Patents

Abstract

A non-volatile memory and a programming method thereof are provided. The programming method of the non-volatile memory includes the following steps. A coarse programming procedure is performed for programing all of a plurality of memory cells in an erase state to 2^N-1 or 2^N program states. N is a positive integer. A fine programming procedure is performed for pushing all of memory cells into 2^N-1 or 2^N verify levels.

Description

Non-volatile memory and its programming method

The present disclosure relates to a memory and its operation programming method, and in particular to a non-volatile memory and its programming method.

With the development of semiconductor technology, the storage density of memory keeps increasing. Traditionally, memory errors need to be corrected through an error correcting code (ECC) circuit to ensure data accuracy. After a long time of operation and multiple programming/erasing, the reliability of the data usually decreases.

As the number of bits increases, stronger ECC circuits are required. However, ECC circuits occupy memory area and increase decoding delay time. In order to improve the area utilization rate and speed up the decoding speed, researchers are working on developing a memory that does not require an ECC circuit or a memory that only requires a small area of the ECC circuit.

This disclosure relates to a non-volatile memory and its programming method, which removes the erasing state during the execution of the programming method, so the erasing state is related to the programming method Bit errors between states are greatly reduced, so ECC circuits are no longer needed or can be scaled down.

According to one aspect of the present disclosure, a programming method of a non-volatile memory is provided. The programming method of the non-volatile memory includes the following steps. Executing a coarse programming procedure to program all the memory cells in an erase state to 2^N-1 or 2^N program states. N is a positive integer. A fine programming procedure is performed to push all memory cells to 2^N-1 or 2^N verify levels.

According to another aspect of the present disclosure, a non-volatile memory is provided. The non-volatile memory includes a memory array and a controller. The memory array includes several memory cells. The controller is used to execute a rough programming procedure to program all memory cells in an erase state (erase state) to 2^N-1 or 2^N programming states (program state); and execute a fine programming procedure (fine programming procedure) to push all memory cells to 2^N-1 or 2^N verification levels. N is a positive integer.

According to yet another aspect of the present disclosure, a programming method of a non-volatile memory is provided. The programming method of the non-volatile memory includes the following steps. Execute a coarse programming procedure to program each of the memory cells in an erase state to one of 2^N-1 or 2^N program states one. N is a positive integer. Execute a fine programming procedure to integrate all Each of the memory cells is pushed to one of 2^N-1 or 2^N verify levels.

In order to have a better understanding of the above and other aspects of the present disclosure, the following specific embodiments are described in detail in conjunction with the attached drawings as follows:

100,200: non-volatile memory

110: memory array

120: amplifier circuit

130: peripheral circuit

140: Controller

150: page buffer

160: voltage regulator

170: ECC circuit

EV: erase state

S110, S120, S210: steps

PV1, PV2, PV3, PV4, PV5, PV6, PV7, PV8: programming status

VR1, VR2, VR3, VR4, VR5, VR6, VR7, VR8: verification level

FIG. 1 shows a block diagram of a non-volatile memory according to an embodiment.

FIG. 2A illustrates an example of the threshold voltage distribution of a non-volatile memory after performing a rough programming procedure.

FIG. 2B illustrates the threshold voltage distribution diagram of the non-volatile memory after executing the fine programming procedure.

FIG. 3 illustrates the threshold voltage distribution of the non-volatile memory in FIG. 2B after heating, long-term use, or multiple programming/erasing.

FIG. 4 shows a block diagram of a non-volatile memory according to another embodiment.

FIG. 5 shows a flow chart of the programming method of the non-volatile memory according to the embodiment in FIG. 4 .

FIG. 6A illustrates the threshold voltage distribution of the non-volatile memory with 2̂N−1 programmed states according to FIG. 5 after performing the rough programming procedure (N is 3 for example).

FIG. 6B illustrates the threshold voltage distribution diagram of the non-volatile memory implementing the 2^N-1 programming states according to FIG. 5 after executing the fine programming procedure (N is, for example, 3).

FIG. 7 illustrates the threshold voltage distribution (N is 3, for example) of a non-volatile memory with 2^N-1 programmed states according to FIG. 6B after heating, long-term use, or multiple programming/erasing.

FIG. 8A illustrates the threshold voltage distribution diagram of a non-volatile memory implementing 2̂N programming states according to FIG. 5 after performing a rough programming procedure (N is 3, for example).

FIG. 8B illustrates the threshold voltage distribution diagram of the non-volatile memory implementing 2̂N programming states according to FIG. 5 after executing the fine programming procedure (N is 3 for example).

FIG. 9 illustrates the threshold voltage distribution diagram of the non-volatile memory implementing 2^N programmed states according to FIG. 8B after heating, long-term use or multiple programming/erasing (N is eg 3).

FIG. 10 is a flow chart of a programming method of a non-volatile memory according to another embodiment.

Please refer to FIG. 1 , which shows a block diagram of a non-volatile memory 100 according to an embodiment. The non-volatile memory 100 is, for example, a NAND flash memory, a NOR flash memory, a floating gate memory or a SONOS memory. The non-volatile memory 100 can be a multi-level cell (Multi-Level Cell, MLC) memory, a triple-level cell (TLC) memory, a four-level cell (Quad-Level Cell, QLC) memory or a five-layer Unit (Penta-Level Cell, PLC) memory. In addition, the non-volatile memory 100 can be a two-dimensional flash memory or a three-dimensional flash memory.

The non-volatile memory 100 includes, for example, a memory array 110 , an amplifier circuit 120 , a peripheral circuit 130 , a controller 140 , a page buffer 150 , a voltage regulator 160 and an ECC circuit 170 . The memory array 110 includes several memory cells. The amplifier circuit 120 is used to sense the low voltage signal in the memory cell and amplify it so as to correctly interpret the data of 1 or 0. The controller 140 is used to control the circuit to execute the programming method, the reading method and the erasing method. The page buffer 150 is used for temporarily storing data. The voltage regulator 160 is used to provide proper voltage.

The programming method of the non-volatile memory includes a coarse programming procedure and a fine programming procedure. Please refer to Figures 2A~2B. Figure 2A illustrates the threshold voltage distribution diagram of the non-volatile memory after the rough programming procedure is executed, and Figure 2B illustrates the threshold voltage distribution of the non-volatile memory after the fine programming procedure is executed. picture. In Figures 2A-2B, the non-volatile memory is, for example, a triple-level cell (Triple-Level Cell, TLC) three-dimensional NAND flash memory.

As shown in FIG. 2A , during the rough programming process, some memory cells will be programmed to the program state (program state) PV1~PV7, and some memory cells will be maintained in the erase state (erase state) EV. In the coarse programming procedure, since the memory cells only need to be roughly divided into several clusters, larger step voltages are used.

As shown in FIG. 2B, in the fine programming process, the memory cells are carefully pushed forward to the verify levels (verify levels) VR1~VR7 by using smaller step voltages. Therefore, finally, 8 states such as the erasing state EV and the programming states PV1-PV7 can be obtained, and the memory cells located in these 8 states are used for data storage.

Please refer to FIG. 3, which illustrates the threshold voltage distribution of the non-volatile memory in FIG. 2B after heating, long-term use, or multiple programming/erasing. After heating, prolonged use, or multiple program/erase cycles, the erased state EV shifts to the right due to charge gain. On the other hand, the distribution of programming states PV1~PV7 will shift to the left. Therefore, the ECC circuit 170 is needed to avoid bit errors due to overlap between the erase state EV and the program state PV1.

Please refer to FIG. 4 , which shows a block diagram of a non-volatile memory 200 according to another embodiment. In this embodiment, the controller 140 removes the erase state EV during the execution of the programming method, so bit errors between the erase state EV and the program state PV1 can be greatly reduced, so the ECC circuit 170 is no longer It is necessary or possible to reduce the area of the ECC circuit 170 . The operation of the controller 140 will be described through a flowchart as follows.

Please refer to Figures 5~6B. FIG. 5 shows a flow chart of the programming method of the non-volatile memory 200 according to the embodiment shown in FIG. 4 . FIG. 6A illustrates the threshold voltage distribution of the non-volatile memory with 2̂N−1 programmed states according to FIG. 5 after performing the rough programming procedure (N is 3 for example). Figure 6B illustrates the imminent behavior of a non-volatile memory with 2^N-1 programming states implemented according to Figure 5 after performing a fine programming procedure Boundary voltage distribution map (N is 3 for example). The controller 140 is used to at least execute the programming method.

In step S110, the controller 140 executes a rough programming procedure to program all the memory cells in the erased state to 2^N-1 (or 2^N) programming states. N is a positive integer, N>1. In the coarse programming procedure, since the memory cells only need to be roughly divided into several clusters, larger step voltages are used. If the non-volatile memory system is a multi-level cell (MLC) memory, N is 2; if the non-volatile memory system is a triple-level cell (TLC) memory, N is 3; if the non-volatile memory system is a quad-level cell (QLC) memory , then N is 4; if the non-volatile memory system is a five-level cell (PLC) memory, then N is 5.

As shown in FIG. 6A , the non-volatile memory 200 is a triple-level cell memory and N is 3. For example, after performing the rough programming procedure, all the memory cells EV in the erase state EV can be programmed into 7 (2̂3−1) programming states PV1˜PV7. Each of the programming states PV1-PV7 is different from the erasing state EV. The "different" here indicates that the threshold voltage of any programming state PV1-PV7 is different from the threshold voltage of the original erasing state EV. After performing the coarse programming procedure, there is no memory cell in the erased state EV, and the number of memory cells in the erased state EV is zero.

Then, in step S120, the controller 140 executes a fine programming procedure to push all the memory cells to 2^N−1 (or 2^N) verify levels. As shown in Figure 6B, in the fine programming procedure, smaller steps are used The voltage carefully pushes the memory cells forward to the verify level (verify level) VR1~VR7.

After executing the programming method, 2^N-1 (or 2^N) programming states can be obtained, and memory cells located in these programming states are used for data storage. Wherein, the erase state EV has been removed and is not used for data storage. As shown in FIG. 6B, the memory cells in the programming states PV1-PV7 are used for data storage.

Please refer to FIG. 7, which illustrates the threshold voltage distribution diagram of the non-volatile memory 200 after heating, long-term use, or multiple programming/erasing according to FIG. 6B implementing 2^N-1 programming states (N such as is 3). After heating, long-term use, or multiple programming/erasing, the programming states PV1~PV7 will shift to the left. Since the erasing state EV has been removed in the programming method, the bit errors caused by overlapping between the erasing state EV and the programming state PV1 can be greatly reduced, so the ECC circuit (as shown in FIG. 4 shown).

6A-7 are illustrated by taking 2^N-1 programming states as an example (N is 3 for example). Please also refer to Figures 8A~9. FIG. 8A illustrates the threshold voltage distribution diagram of a non-volatile memory implementing 2̂N programming states according to FIG. 5 after performing a rough programming procedure (N is 3, for example). FIG. 8B illustrates the threshold voltage distribution diagram of the non-volatile memory implementing the 2̂N programming states according to FIG. 5 after performing the fine programming procedure (N is 3 for example). FIG. 9 illustrates the threshold voltage distribution diagram of the non-volatile memory 200 implementing 2̂N programmed states according to FIG. 8B after heating, long-term use, or multiple programming/erasing (N is 3, for example).

As shown in FIG. 8A, after performing the rough programming procedure, all the memory cells EV in the erase state EV are programmed into 8 programming states PV1~PV8. Each of the programming states PV1-PV8 is different from the erasing state EV. The "different" here indicates that the threshold voltage of any programming state PV1-PV8 is different from the threshold voltage of the original erasing state EV. After performing the coarse programming procedure, there is no memory cell in the erased state EV, and the number of memory cells in the erased state EV is zero.

As shown in FIG. 8B, in the fine programming process, the memory cells are carefully pushed forward to the verification levels VR1~VR8 by using small step voltages.

As shown in Figure 9, since the erased state EV has been removed in the programming method, the bit errors caused by overlapping between the erased state EV and the programmed state PV1 can be greatly reduced, so it is unnecessary ECC circuit (as shown in Figure 4).

Please refer to FIG. 10 , which shows a flowchart of a programming method of the non-volatile memory 200 according to another embodiment. In step S210, the controller 140 executes a rough programming procedure to program each memory cell in the erased state to one of 2^N-1 (or 2^N) programming states, where N is greater than A positive integer of 1. In this embodiment, each memory cell is programmed to a programmed state. After performing the coarse programming procedure, the memory cells may use less than 2^N-1 (or 2^N) programming states. If the non-volatile memory system is a multi-level cell (MLC) memory, N is 2; if the non-volatile memory system is a triple-level cell (TLC) memory, N is 3; if the non-volatile memory system is a quad-level cell (QLC) memory , then N is 4; if the non-volatile memory system is a five-level cell (PLC) memory, then N is 5. For example, when N is 3, remember The programming states available for the memory cells are, for example, the programming states PV1-PV7. In this step, each memory cell in the erased state EV is programmed to one of the seven programmed states. It is possible that the programming states PV1, PV3-PV7 are used, but the programming state PV2 is not used, so after the rough programming procedure is executed, the used programming states of the memory cells may be less than 7.

Then, in step S220, the controller 140 executes a fine programming procedure to push each memory cell to one of 2^N-1 (or 2^N) verify levels. After executing the fine programming procedure, the memory cells may use fewer than 2^N-1 (or 2^N) programming states. Likewise, in this step, each memory cell in the erase state EV will be programmed to one of the seven programming states. Therefore, after executing the fine programming procedure, the memory cells may use less than 7 programming states.

On the other hand, if the non-volatile memory 200 is a quad-level cell (QLC) memory and N is 4. After executing the rough programming procedure, all memory cells EV in the erased state EV are programmed to 15 (or 16) programming states; or, each memory cell in the erased state is programmed to 15 (or 16) programming states one of them.

In addition, if the non-volatile memory 200 is a five-level cell (PLC) memory and N is 5. After executing the rough programming procedure, all memory cells EV in the erased state EV are programmed to 31 (or 32) programming states; or, each memory cell in the erased state is programmed to 31 (or 32) programming states one of them.

According to the above-mentioned embodiment, the controller 140 removes the erasing state EV during the execution of the programming method, so the bit errors between the erasing state EV and the programming state PV1 are greatly reduced, so the ECC circuit is no longer needed or can be zoom out.

To sum up, although the present disclosure has been disclosed above with embodiments, it is not intended to limit the present disclosure. Those with ordinary knowledge in the technical field to which this disclosure belongs may make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure should be defined by the scope of the appended patent application.

S110, S120: steps

Claims (10)

A programming method of a non-volatile memory, comprising: executing a rough programming procedure (coarse programming procedure) to program all multiple memory cells in an erase state (erase state) to 2^N-1 or 2^N program state (program state), and remove the erase state, where N is a positive integer; and execute a fine programming procedure (fine programming procedure) to push all the memory cells to 2^N-1 or 2^N verification levels (verify levels). The programming method of the non-volatile memory according to claim 1, wherein after the rough programming procedure is executed, the number of the memory cells in the erasing state is 0. The programming method of the non-volatile memory as claimed in claim 1, wherein the threshold voltage of each programming state is different from the threshold voltage of the erasing state. The programming method of the non-volatile memory as described in Claim 1, wherein if the non-volatile memory system is a multi-level cell (Multi-Level Cell, MLC) memory, N is 2, after executing the rough programming program, All of the memory cells in the erasing state are programmed into 3 or 4 of the programming states; If the non-volatile memory system is a triple-level cell (Triple-Level Cell, TLC) memory, and N is 3, after executing the rough programming procedure, all the memory cells in the erasing state are programmed to 7 Or 8 of these programming states; if the non-volatile memory system is a four-level cell (Quad-Level Cell, QLC) memory, N is 4, after executing the rough programming program, all the erased state These memory cells are all programmed to 15 or 16 these programming states; and if the non-volatile memory system is a five-layer unit (Penta-Level Cell, PLC) memory, N is 5, after performing the rough programming program , all the memory cells in the erase state are programmed to 31 or 32 of the programming states. The programming method of the non-volatile memory according to claim 1, wherein after executing the rough programming procedure, the memory cells in the programming state are used for data storage. A non-volatile memory, comprising: a memory array including a plurality of memory cells; and a controller for executing a rough programming procedure to program all the memory cells in an erase state (erase state) to 2^N-1 or 2^N programming states (program state), and remove the erasing state, wherein N is a positive integer; and execute a fine programming procedure (fine programming procedure), so that all these Memory cells are pushed to 2^N-1 or 2^N verify levels. The non-volatile memory according to claim 6, wherein the number of memory cells in the erasing state is zero after the rough programming procedure is executed. The non-volatile memory as claimed in claim 6, wherein the threshold voltage of each programming state is different from the threshold voltage of the erasing state. The non-volatile memory as described in claim item 6, wherein if the non-volatile memory system is a multi-level cell (Multi-Level Cell, MLC) memory, N is 2, and after executing the rough programming program, all located in the These memory cells in the erasing state are all programmed into 3 or 4 of these programming states; if the non-volatile memory system is a triple-level cell (Triple-Level Cell, TLC) memory, N is 3, when executing the After the rough programming procedure, all the memory cells in the erasing state are programmed into 7 or 8 programming states; if the non-volatile memory system is a quad-level cell (Quad-Level Cell, QLC) memory, N is 4, after carrying out this rough programming procedure, all these memory cells that are positioned at this erasing state are all programmed to these programming states of 15 or 16; And if this non-volatile memory system is a five-level unit (Penta -Level Cell, PLC) memory, N is 5, after executing the rough programming procedure, all the memory cells in the erasing state are programmed into 31 or 32 programming states. A programming method of a non-volatile memory, comprising: executing a rough programming procedure (coarse programming procedure), so that each of a plurality of memory cells in an erasing state (erase state) programming to one of 2^N-1 or 2^N programming states (program state), and removing the erase state, wherein N is a positive integer; and executing a fine programming procedure , to push each of the memory cells to one of 2^N-1 or 2^N verify levels.

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