CN112583078B - Battery pack, battery protection chip and electronic product - Google Patents

Battery pack, battery protection chip and electronic product Download PDF

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Publication number
CN112583078B
CN112583078B CN202011503334.2A CN202011503334A CN112583078B CN 112583078 B CN112583078 B CN 112583078B CN 202011503334 A CN202011503334 A CN 202011503334A CN 112583078 B CN112583078 B CN 112583078B
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type mos
charging
voltage
electrically connected
battery
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CN112583078A (en
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宋利军
贺玉婷
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Xi'an Wenxian Semiconductor Technology Co ltd
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Xi'an Wenxian Semiconductor Technology Co ltd
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Priority to PCT/CN2021/136547 priority patent/WO2022127671A1/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/00302—Overcharge protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/00306—Overdischarge protection

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Secondary Cells (AREA)

Abstract

The invention discloses a battery pack, a battery protection chip and an electronic product, wherein the battery protection chip comprises a power supply pin, a grounding pin, an inductor access pin, a current detection pin, a discharge control pin and a charge control pin, the chip also comprises a voltage control circuit, a discharge control circuit and a charge control circuit, one end of the inductor is connected with the input end of the voltage control circuit, the other end of the inductor is electrically connected with the positive electrode end of a battery, the discharge control pin and the charge control pin of the battery protection chip are respectively used for controlling the first NMOS tube to be electrically connected with the negative electrode end of the battery, a second NMOS tube electrically connected with the negative electrode terminal of the external power supply, the voltage control circuit generates stable control voltage to make the conduction state of the two NMOS tubes not affected by the voltage drop of the battery, and effectively avoiding the potential difference between the inside and the outside due to the interruption of the connection of the negative electrode end of the battery.

Description

Battery pack, battery protection chip and electronic product
Technical Field
The invention relates to the technical field of battery protection, in particular to a battery assembly, a battery protection chip and an electronic product.
Background
Rechargeable batteries are widely used in consumer electronics and have been built into important components of electronics, and the quality and use protection of rechargeable batteries often determine the quality of electronic products.
For the battery charging and discharging protection circuit, in the charging and discharging process of the rechargeable battery, the charging or discharging current needs to be detected, if the current is too large, the charging or discharging needs to be automatically cut off, and the switch for controlling the charging and discharging is usually realized by an MOS transistor, and the on-off control of the MOS transistor needs to be realized by the voltage of the battery, but in the initial charging stage or the later discharging stage, the voltage of the battery is usually smaller than the full voltage, for example, the rated voltage is 4.2V for the lithium battery, in the initial charging stage or the later discharging stage, the voltage of the battery is reduced to about 2.5V, under the condition of low voltage, the voltage difference for controlling the conduction of the MOS transistor is also obviously reduced, so that the conduction impedance of the MOS transistor is obviously improved, at this time, the conduction impedance of the external MOS may be one time larger than the voltage of the battery is 4V, and the loss caused by the conduction impedance of the MOS transistor under the condition of large current application is one time larger, the effective service time of the battery is shortened, and meanwhile, heat release is brought, and the internal temperature of the electronic product is increased.
Disclosure of Invention
The invention mainly solves the technical problem of providing a battery charging and discharging protection circuit, a chip and an electronic product, and solves the problem of how to keep the conduction voltage of a switching tube stable under the condition of low voltage of a battery in the charging and discharging protection of the battery, and the increase of heat energy consumption caused by the increase of conduction impedance can not be caused.
To solve the above technical problems, one technical solution adopted by the present invention is to provide a battery assembly, including a battery and a battery protection chip, the battery protection chip comprises a power supply pin, a grounding pin, an inductor access pin, a current detection pin, a discharge control pin and a charge control pin, and also comprises a voltage control circuit, a discharge control circuit and a charge control circuit, the input end of the voltage control circuit is electrically connected with an inductor access pin, the inductor input pin is electrically connected with an inductor, the other end of the inductor is electrically connected with the positive terminal of the battery, the output end of the voltage control circuit is respectively and electrically connected with the input ends of the discharge control circuit and the charge control circuit, the output end of the discharge control circuit is electrically connected with a discharge control pin, and the output end of the charge control circuit is electrically connected with a charge control pin; the power supply pin of the battery protection chip is electrically connected with the positive electrode end of the battery, the negative electrode end of the battery is also electrically connected with the source electrode of the first NMOS tube, the drain electrode of the first NMOS tube is electrically connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is used as the negative electrode connecting end shared by battery discharging and charging, and the positive electrode end of the battery is used as the positive electrode connecting end shared by battery discharging and charging; a discharge control pin of the battery protection chip is electrically connected with a grid electrode of the first NMOS tube, and a charge control pin is electrically connected with a grid electrode of the second NMOS tube; the negative electrode end of the battery is electrically connected with the grounding pin of the battery protection chip, and the source electrode of the second NMOS tube is electrically connected with the current detection pin of the battery protection chip.
Preferably, the voltage control circuit inputs a control voltage to the discharge control circuit, the battery protection chip is used for monitoring the control voltage output by the discharge control circuit through a discharge control pin when the battery is discharged to normally work, and the discharge control circuit outputs a second voltage through the discharge control pin when the battery is monitored to be discharged to abnormally work; the control voltage circuit inputs control voltage to the charging control circuit, the battery protection chip is used for monitoring the normal charging operation of the battery, the charging control circuit outputs the control voltage through the charging control pin, and the charging control circuit outputs third voltage through the charging control pin when monitoring the abnormal charging operation of the battery.
Preferably, a difference value obtained by subtracting the voltage value of the negative terminal of the battery from the voltage value of the control voltage is greater than or equal to a minimum on-state voltage between the gate and the source of the first NMOS transistor and is less than a maximum breakdown voltage between the gate and the source of the first NMOS transistor; the difference value of the voltage value of the control voltage minus the voltage value of the source electrode of the second NMOS tube is larger than or equal to the minimum breakover voltage between the grid electrode and the source electrode of the second NMOS tube and smaller than the maximum breakdown voltage between the grid electrode and the source electrode of the second NMOS tube.
Preferably, the voltage value of the control voltage is a fixed value, or the voltage value of the control voltage is a range value, or the control voltage is an integer multiple of the voltage value of the battery.
Preferably, the second voltage is a voltage of a negative terminal of the battery, and the third voltage is a voltage of a source of the second NMOS transistor.
Preferably, the voltage control circuit comprises a switch tube, one end of the switch tube is electrically connected with the inductor, the other end of the switch tube is grounded, the control end of the switch tube is electrically connected with an adjustable pulse generator, and pulses generated by the pulse generator are used for conducting or switching off control on two ends of the switch tube; the junction of the switch tube and the inductor is also connected with the anode of a diode, the cathode of the diode is electrically connected with a capacitor and then grounded, and the voltage generated by the cathode of the diode is the output voltage of the voltage control circuit.
Preferably, the voltage control circuit comprises a switch tube, one end of the switch tube is electrically connected with the inductor, the other end of the switch tube is grounded, the control end of the switch tube is electrically connected with an adjustable pulse generator, and pulses generated by the pulse generator are used for conducting or switching off control on two ends of the switch tube; the junction of the switch tube and the inductor is also connected with the anode of a diode, the cathode of the diode is electrically connected with a capacitor and then grounded, and the voltage generated by the cathode of the diode is the output voltage of the voltage control circuit; the negative electrode of the diode is also electrically connected with a first feedback resistor and a second feedback resistor which are connected in series and then grounded, and the connection part between the first feedback resistor and the second feedback resistor is electrically connected with the control end of the pulse generator.
Preferably, the control end of the pulse generator is electrically connected to an error operational amplifier, one input end of the error operational amplifier is connected to a reference voltage, the other input end of the error operational amplifier is connected to a feedback voltage from a connection between the first feedback resistor and the second feedback resistor, and the output end of the error operational amplifier is connected to the control end of the pulse generator.
Preferably, the pulse generator is further connected to an oscillator, and the oscillator inputs an oscillation signal as a signal source for generating pulse output by the pulse generator.
Preferably, the voltage control circuit comprises a switch tube, one end of the switch tube is electrically connected with the inductor, the other end of the switch tube is grounded, the control end of the switch tube is electrically connected with an adjustable pulse generator, and pulses generated by the pulse generator are used for conducting or switching off control on two ends of the switch tube; the junction of the switch tube and the inductor is also connected with the anode of a diode, the cathode of the diode is electrically connected with a capacitor and then grounded, and the voltage generated by the cathode of the diode is the output voltage of the voltage control circuit; the negative electrode of the diode is electrically connected with a first feedback resistor and a second feedback resistor which are connected in series and then grounded, the joint between the first feedback resistor and the second feedback resistor is electrically connected with the positive input end of a first comparator and the negative input end of a second comparator respectively, the negative input end of the first comparator is connected with a low reference voltage, the positive input end of the second comparator is connected with a high reference voltage, and the output end of the second comparator and the output end of the first comparator are connected with two control input ends of a pulse generator respectively.
Preferably, the discharge control circuit includes a first discharge not gate, a first discharge P-type MOS transistor, a second discharge P-type MOS transistor, a third discharge P-type MOS transistor, a first discharge N-type MOS transistor, a second discharge N-type MOS transistor, and a third discharge N-type MOS transistor; the input end of the first discharging NOT gate is electrically connected with the grid electrode of the second discharging N-type MOS tube, and the output end of the first discharging NOT gate is electrically connected with the grid electrode of the first discharging N-type MOS tube; the drain electrode of the first discharging P-type MOS tube is electrically connected with the drain electrode of the first discharging N-type MOS tube to serve as a first drain electrode connection point, and the first drain electrode connection point is electrically connected with the grid electrode of the second discharging P-type MOS tube; the drain electrode of the second discharge P-type MOS tube is electrically connected with the drain electrode of the second discharge N-type MOS tube to serve as a second drain electrode connection point, and the second drain electrode connection point is electrically connected with the grid electrode of the first discharge P-type MOS tube; the grid electrode of the third discharge P-type MOS tube is electrically connected with the grid electrode of the third discharge N-type MOS tube to serve as a first grid electrode connection point, and the first grid electrode connection point is electrically connected with the second drain electrode connection point; the drain electrode of the third discharge P-type MOS tube is electrically connected with the drain electrode of the third discharge N-type MOS tube to serve as a third drain electrode connection point, and the third drain electrode connection point is the output end of the discharge control circuit; the source electrode of the first discharge P-type MOS tube, the source electrode of the second discharge P-type MOS tube, and the source electrode of the third discharge P-type MOS tube are electrically connected with the output end of the voltage control circuit and used as the control voltage of the discharge control circuit; and the source electrode of the first discharging N-type MOS tube is electrically connected with the source electrode of the second discharging N-type MOS tube, and the source electrode of the third discharging N-type MOS tube is electrically connected with the grounding pin of the battery protection chip and is used as a second voltage of the discharging control circuit.
Preferably, the charge control circuit comprises a first charge inverter, a first charge P-type MOS transistor, a second charge P-type MOS transistor, a third charge P-type MOS transistor, a fourth charge P-type MOS transistor, a fifth charge P-type MOS transistor, a sixth charge P-type MOS transistor, a first charge N-type MOS transistor, a second charge N-type MOS transistor, a third charge N-type MOS transistor, a fourth charge N-type MOS transistor, a fifth charge N-type MOS transistor, and a sixth charge N-type MOS transistor; the input end of the first charging NOT gate is electrically connected with the grid electrode of the second charging P-type MOS tube, and the output end of the first charging NOT gate is electrically connected with the grid electrode of the first charging P-type MOS tube; the drain electrode of the first charging P-type MOS tube is electrically connected with the drain electrode of the first charging N-type MOS tube to serve as a first charging drain electrode connecting point, and the first charging drain electrode connecting point is electrically connected with the grid electrode of the second charging N-type MOS tube; the drain electrode of the second charging P-type MOS tube is electrically connected with the drain electrode of the second charging N-type MOS tube to serve as a second charging drain electrode connecting point, and the second charging drain electrode connecting point is electrically connected with the grid electrode of the first charging N-type MOS tube; the grid electrode of the third charging P-type MOS tube is electrically connected with the grid electrode of the third charging N-type MOS tube to serve as a first charging grid electrode connecting point, the first charging grid electrode connecting point is electrically connected with the second charging drain electrode connecting point and is also electrically connected with the grid electrode of a fifth charging N-type MOS tube, and the drain electrode of the third charging P-type MOS tube is electrically connected with the drain electrode of the third charging N-type MOS tube to serve as a third charging drain electrode connecting point and is electrically connected with the grid electrode of the fourth charging N-type MOS tube; the source electrode of the first charging P-type MOS tube is electrically connected with the source electrode of the second charging P-type MOS tube and the source electrode of the third charging P-type MOS tube and is electrically connected with a power pin of the battery protection chip; the drain electrode of the fourth charging P-type MOS tube is electrically connected with the drain electrode of the fourth charging N-type MOS tube to serve as a fourth charging drain electrode connection point, and the fourth charging drain electrode connection point is electrically connected with the grid electrode of the fifth charging P-type MOS tube; the drain electrode of the fifth charging P-type MOS tube is electrically connected with the drain electrode of the fifth charging N-type MOS tube to serve as a fifth charging drain electrode connection point, and the fifth charging drain electrode connection point is electrically connected with the grid electrode of the fourth charging P-type MOS tube; a grid electrode of the sixth charging P-type MOS tube is electrically connected with a grid electrode of the sixth charging N-type MOS tube to serve as a second charging grid electrode connecting point, and the second charging grid electrode connecting point is electrically connected with the fifth charging drain electrode connecting point; the drain electrode of the sixth charging P-type MOS tube is electrically connected with the drain electrode of the sixth charging N-type MOS tube to serve as a sixth charging drain electrode connection point which is the output end of the charging control circuit; the source electrode of the fourth charging P-type MOS tube is electrically connected with the source electrode of the fifth charging P-type MOS tube and the source electrode of the sixth charging P-type MOS tube, is electrically connected with the output end of the voltage control circuit and is used as the control voltage of the discharging and charging control circuit; the source electrode of the first charging N-type MOS tube, the source electrode of the second charging N-type MOS tube, the source electrode of the third charging N-type MOS tube, the source electrode of the fourth charging N-type MOS tube, the source electrode of the fifth charging N-type MOS tube and the source electrode of the sixth charging N-type MOS tube are electrically connected, and are all electrically connected with the current detection pin to serve as a third voltage of the charging control circuit.
Preferably, the current detection circuit further comprises a second current limiting resistor electrically connected with the source electrode of the second NMOS transistor, and the other end of the second current limiting resistor is connected to the current detection pin.
The invention also provides a battery protection chip, which is characterized in that the battery protection chip is contained in the battery pack.
The invention also provides an electronic product comprising the battery component.
The invention has the beneficial effects that: the invention discloses a battery pack, a battery protection chip and an electronic product, wherein the battery protection chip comprises a power supply pin, a grounding pin, an inductor access pin, a current detection pin, a discharge control pin and a charge control pin, the chip also comprises a voltage control circuit, a discharge control circuit and a charge control circuit, one end of the inductor is connected with the input end of the voltage control circuit, the other end of the inductor is electrically connected with the positive electrode end of a battery, the discharge control pin and the charge control pin of the battery protection chip are respectively used for controlling the first NMOS tube to be electrically connected with the negative electrode end of the battery, a second NMOS tube electrically connected with the negative electrode terminal of the external power supply, the voltage control circuit generates stable control voltage to make the conduction state of the two NMOS tubes not affected by the voltage drop of the battery, and effectively avoid the potential difference between the inside and the outside caused by the broken connection of the negative end of the battery.
Drawings
FIG. 1 is a block diagram of the components of one embodiment of a battery assembly according to the present invention;
fig. 2 is a voltage control circuit diagram in another embodiment of a battery pack according to the present invention;
fig. 3 is a voltage control circuit diagram in another embodiment of a battery pack according to the present invention;
fig. 4 is a discharge control circuit diagram in another embodiment of a battery pack according to the present invention;
fig. 5 is a circuit diagram of a charge control circuit in another embodiment of a battery pack according to the present invention;
Detailed Description
In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It is to be noted that, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Fig. 1 shows a block diagram of the circuit of an embodiment of the battery pack of the present invention. The battery pack comprises a battery 1 and a battery protection chip 2, wherein the battery protection chip 2 comprises a power supply pin 201, a grounding pin 202, a current detection pin 203, a discharge control pin 204, a charge control pin 205 and an inductor access pin 206, the battery protection chip 2 also comprises a voltage control circuit 21, a discharge control circuit 22 and a charge control circuit 23 inside, the input end of the voltage control circuit 21 is electrically connected with the inductor access pin 206, the inductor input pin 206 is electrically connected with an inductor L1, the other end of the inductor L1 is electrically connected with the positive terminal 101 of the battery 1, the output end of the voltage control circuit 21 is respectively electrically connected with the input ends of the discharge control circuit 22 and the charge control circuit 23, the output end of the discharge control circuit 22 is electrically connected with the discharge control pin 204, and the output end of the charge control circuit 23 is electrically connected with the charge control pin 205;
the power supply pin 201 of the battery protection chip 2 is electrically connected with the positive terminal 101 of the battery 1, the negative terminal 102 of the battery 1 is also electrically connected with the source electrode of the first NMOS transistor FET1, the drain electrode of the first NMOS transistor FET1 is electrically connected with the drain electrode of the second NMOS transistor FET2, the source electrode of the second NMOS transistor FET2 is used as the negative connecting terminal P shared by discharging and charging of the battery 1, and the positive terminal 101 of the battery is used as the positive connecting terminal P + shared by discharging and charging of the battery 1; the discharge control pin 204 of the battery protection chip 2 is electrically connected to the gate of the first NMOS transistor FET1, and the charge control pin 205 is electrically connected to the gate of the second NMOS transistor FET 2;
the negative terminal 102 of the battery is electrically connected to the ground pin 202 of the battery protection chip 2, and the source of the second NMOS transistor FET2 is electrically connected to the current detection pin 203 of the battery protection chip 1.
Preferably, a first current limiting resistor R1 is connected in series between the power pin 201 of the battery protection chip 2 and the positive terminal 101 of the battery 1, and the positive terminal of the battery 1 is also denoted by VDD. Furthermore, the power pin 201 is also connected to a voltage-stabilizing filter capacitor C1, and the other end of the voltage-stabilizing filter capacitor C1 is connected to the negative terminal 102 of the battery 1, which is also referred to as the ground GND of the battery.
Preferably, the ground pin 202 of the battery protection chip 2 is electrically connected to the discharge control circuit 22 as a second voltage of the discharge control circuit 22, i.e., a first reference ground GND, and the current detection pin 203 is electrically connected to the charge control circuit 23 as a third voltage of the charge control circuit 23, i.e., a second reference ground VM. It can be seen that the source of the second NMOS FET2 is used as the negative terminal P-for both battery discharging and charging, and is directly electrically connected to the ground of the external discharging device or charger, with their ground as the ground reference.
Preferably, the source of the second NMOS FET2 is further electrically connected to a second current limiting resistor R2, and the other end of R2 is connected to the current detection pin 203 as the reference ground of the charge control circuit 23. In principle, when the two NMOS transistors are turned on during charging and discharging, the first reference ground and the second reference ground are connected together, and a common ground connection is realized. If the second NMOS transistor FET2 is turned off when the charging current is too large or the first NMOS transistor FET1 is turned off when the discharging current is too large, the first reference ground and the second reference ground are turned off from each other, and therefore, the charging control circuit can ensure that the voltage to the gate and the source of the second NMOS transistor FET2 is always referenced to the second reference ground, not to the first reference ground, even if either of the first NMOS transistor FET1 and the second NMOS transistor FET2 is turned off, with the second reference ground as the reference ground. The voltage of the gate and the source of the first NMOS transistor FET1 is also guaranteed to be always referenced to the first reference ground, rather than the second reference ground, so that a ground voltage difference between the internal battery and the external electric device or charger, which is caused by the first reference ground and the second reference ground not being in common, can be avoided, and the electric safety is facilitated.
Preferably, the voltage control circuit 21 inputs a control voltage to the discharge control circuit 22, and the battery protection chip 2 is configured to monitor that the battery 1 is discharged and normally operates, and the discharge control circuit 22 outputs the control voltage through the discharge control pin 204. Preferably, the difference between the voltage value of the control voltage and the voltage value of the negative terminal of the battery is greater than or equal to the minimum on-voltage between the gate and the source of the first NMOS transistor FET1 and less than the maximum breakdown voltage between the gate and the source of the first NMOS transistor FET1, so that sufficient conduction between the source and the drain of the first NMOS transistor FET1 can be ensured without causing the power consumption problem due to excessive on-resistance. Preferably, the first NMOS transistor FET1 and the second NMOS transistor FET2 have the same characteristics, and when the battery 1 is discharged and normally operates, the control voltage makes the source and the drain of the two MOS transistors in a fully conducting state. Further, when the battery 1 is monitored to operate abnormally, for example, when the current is too large, the discharge control circuit 22 outputs a second voltage through the discharge control pin 204, and the second voltage is applied so that the difference between the voltage value of the second voltage and the voltage value of the negative terminal of the battery is obviously smaller than the minimum on-state voltage between the gate and the source of the first NMOS transistor FET1, and therefore, the first NMOS transistor FET1 is in an off-state. Preferably, the second voltage is a voltage of a negative terminal of the battery, that is, a voltage corresponding to the first reference ground.
Preferably, the voltage control circuit 21 inputs a control voltage to the charging control circuit 23, and the charging control circuit 23 outputs the control voltage through the charging control pin 205 when the battery protection chip 2 is used for monitoring the normal charging operation of the battery 1. Preferably, the difference between the voltage value of the control voltage and the voltage value of the source of the second NMOS transistor FET2 is greater than or equal to the minimum on-voltage between the gate and the source of the second NMOS transistor FET2 and less than the maximum breakdown voltage between the gate and the source of the second NMOS transistor FET 2. Therefore, the source and the drain of the second NMOS transistor FET2 can be fully conducted without causing power consumption due to excessive on-resistance. Preferably, the first NMOS transistor FET1 and the second NMOS transistor FET2 have the same characteristics, and the control voltage makes the source and the drain of the two MOS transistors in a fully conducting state when the battery 1 is charged and normally operates. Further, when the battery 1 is monitored to operate abnormally during charging, the charging control circuit 22 outputs a third voltage through the charging control pin 205, and the third voltage is applied such that a difference between a voltage value of the third voltage and a voltage value of the source of the second NMOS transistor is substantially smaller than a minimum on-voltage between the gate and the source of the second NMOS transistor FET2, so that the second NMOS transistor FET1 is in an off state. Preferably, the third voltage is a voltage of the source of the second NMOS transistor, that is, a voltage corresponding to a second reference ground.
Preferably, on the premise that a difference between a voltage value of the control voltage minus a voltage value of the negative terminal of the battery is greater than or equal to a minimum on-voltage between the gate and the source of the first NMOS transistor FET1 and a difference between a voltage value of the control voltage minus a voltage value of the source of the second NMOS transistor FET2 is greater than or equal to a minimum on-voltage between the gate and the source of the second NMOS transistor FET2, the voltage value of the control voltage is a fixed value, or the voltage value of the control voltage is an interval value, or the control voltage is an integer multiple of the voltage value of the battery.
As shown in fig. 2, a preferred embodiment of the voltage control circuit 21 is described in the present invention. The voltage control circuit 21 includes a switch tube M1, one end of the switch tube M1 is electrically connected to the inductor L1, the other end is grounded, a control end of the switch tube M1 is electrically connected to an adjustable pulse generator, and pulses generated by the pulse generator are used for conducting or switching off the two ends of the switch tube M1.
Preferably, a connection point of the switching tube M1 and the inductor L1 is connected to an anode of the diode D1, a cathode of the diode D1 is electrically connected to a capacitor C1 and then grounded, and a voltage generated by a cathode of the diode D1 is an output voltage of the voltage control circuit 21.
Preferably, by adjusting and controlling the duty ratio of the pulse generated by the pulse generator to be constant, the output voltage of the voltage control circuit 21 and the battery voltage VDD connected to the inductor L1 keep a fixed proportional relationship, for example, the output voltage of the voltage control circuit 21 is twice the battery voltage, or may be other multiple relationships, and only the duty ratio needs to be adjusted and controlled.
In practical applications, since the battery voltage varies, for example, the battery voltage is higher when the battery is fully charged, and the battery voltage decreases as the battery 1 is discharged, and the voltage decreases significantly in the later period of the battery discharge, for example, the lithium battery may decrease from 4.2V to 2.5V, and if the output voltage maintains a double relation of the battery voltage, the output voltage may decrease from 8.4V to 5V. The variation of the output voltage is relatively large, but if the requirements of the discharge control circuit 22 and the charge control circuit 23 for the conduction control of the corresponding MOS transistors can be met, the relationship that the output voltage and the battery voltage keep a fixed multiple can also be used, except that the output voltage is not kept at a stable voltage output, but is kept at a fixed multiple of the battery 1 voltage.
Preferably, the cathode of the diode D1 is further electrically connected to a first feedback resistor R1 and a second feedback resistor R2 which are connected in series, and then grounded, and the connection between the first feedback resistor R1 and the second feedback resistor R2 is electrically connected to the control end of the pulse generator. Here, the junction between the first feedback resistor R1 and the second feedback resistor R2 may divide the output voltage Vo to obtain a feedback voltage Vfb, and the resistances of the first feedback resistor R1 and the second feedback resistor R2 are R1 and R2, respectively, so that Vfb is R2/(R1+ R2) × Vo. And feedback voltage Vfb can be used for the control end of pulse generator, when Vfb voltage reduces, the correspondence can be regulated and controlled pulse duty cycle that pulse generator produced increases, and then regulates and control the length of time proportional relation of switch tube M1's switching on and switching off, increases inductance L1's energy storage for output voltage Vo risees, and then also can make the feedback voltage Vfb risees. Similarly, when the voltage of the feedback voltage Vfb increases, the output voltage Vo, and thus the feedback voltage Vfb, decreases based on the same feedback and regulation principles. Thereby, the output voltage Vo can be stabilized at a relatively fixed voltage value, and thus, is not changed by the variation of the battery voltage.
Preferably, in order to stably output the output voltage Vo at a desired voltage value, the control terminal of the pulse generator may be further electrically connected to an error operational amplifier EA, one input terminal of the error operational amplifier EA is connected to the reference voltage Vref, the other input terminal of the error operational amplifier EA is connected to the feedback voltage Vfb, and the output terminal of the error operational amplifier EA is connected to the control terminal of the pulse generator. When the feedback voltage Vfb is greater than the reference voltage Vref, the error operational amplifier EA outputs a positive voltage, and the voltage value of the positive voltage is proportional to the difference between the feedback voltage Vfb and the reference voltage Vref. The pulse generator correspondingly regulates and controls the duty ratio of output pulses according to the input voltage of the control end, so that the energy storage of the inductor L1 is reduced, and the output voltage is further reduced. Based on the same principle, when the feedback voltage Vfb is lower than the reference voltage Vref, the pulse generator correspondingly regulates and controls the duty ratio of the output pulse according to the input voltage of the control end, so that the stored energy of the inductor L1 is increased, and the output voltage is further improved. Thus, the feedback voltage Vfb is always dynamically varied around the reference voltage VrefAnd the dynamic change has small amplitude change and fast tracking regulation, thereby ensuring the output voltage:
Figure BDA0002844135480000121
therefore, by reasonably setting the proportional relation between the reference voltage value and the two feedback resistors, the output voltage can be kept stably output and does not change with the change of the voltage of the battery 1.
Preferably, the switch tube M1 is an NMOS tube, a gate of the NMOS tube is electrically connected to the output end of the pulse generator, a source of the NMOS tube is grounded, and a drain of the NMOS tube is electrically connected to the inductor L1.
Preferably, the pulse generator is further connected to an oscillator OSC, and the oscillator OSC inputs an oscillation signal as a signal source for generating a pulse output by the pulse generator. The pulse generator may perform frequency doubling or frequency division control on the frequency of the input oscillation signal, so as to change the frequency of the output pulse signal, that is, perform Pulse Frequency Modulation (PFM), or may also perform Pulse Width Modulation (PWM) by changing the duty ratio of the output pulse signal.
Preferably, the larger the duty cycle of the pulse generator, the more energy is stored in the inductor L1, because the inductor L1 has current VDD/(L × D × T), L is the inductance value of the inductor L1, D is the duty cycle of the pulse signal, and T is the frequency cycle of the pulse signal. In a pulse period, the switch tube M1 is on, the inductor L1 stores energy in the range of duty ratio D, and when the switch tube M1 is off, the inductor L1 is partially discharged in the range of 1-D and outputs to the capacitor C1. Therefore, by regulating the duty ratio of the pulse, the stored energy of the inductor L1 and the output voltage to the capacitor C1 can be regulated.
Further preferably, on the basis of fig. 2, fig. 3 is another voltage control circuit 21, and the main difference from fig. 2 is that the error operational amplifier EA in fig. 2 is replaced by two comparators, a connection point of the first feedback resistor R1 and the second feedback resistor R2 is electrically connected to a positive input terminal of the first comparator and a negative input terminal of the second comparator, respectively, a negative input terminal of the first comparator EA1 is connected to the low reference voltage Vref _ L, a positive input terminal of the second comparator EA2 is connected to the high reference voltage Vref _ H, and an output terminal of the second comparator EA1 and an output terminal of the first comparator EA1 are connected to two control input terminals of the pulse generator, respectively.
Preferably, when the feedback voltage Vfb at the connection of the first feedback resistor R1 and the second feedback resistor R2 is less than or equal to the low reference voltage Vref _ L, the first comparator EA1 outputs a low voltage, and the second comparator EA2 outputs a high voltage; when the feedback voltage Vfb is greater than the low reference voltage Vref _ L and is less than the high reference voltage Vref _ H, the first comparator EA1 outputs a high voltage, and the second comparator EA2 outputs a high voltage; when the feedback voltage Vfb is greater than or equal to the high reference voltage Vref _ H, the first comparator EA1 outputs a high voltage, and the second comparator EA2 outputs a low voltage. Therefore, when the pulse generator identifies that the feedback voltage Vfb is less than or equal to the low reference voltage Vref _ L according to the logical combination relationship of the output voltages of the two comparators, the pulse generator regulates and controls the duty ratio of the pulses generated by the pulse generator to increase, further regulates and controls the on-off time proportional relationship of the switching tube M1, increases the stored energy of the inductor L1, increases the output voltage Vo, and further increases the feedback voltage Vfb. When the feedback voltage Vfb is larger than or equal to the high reference voltage Vref _ H, the duty ratio of the pulse generated by the pulse generator is regulated and controlled to be reduced, the on-off time proportional relation of the switching tube M1 is further regulated and controlled, the stored energy of the inductor L1 is reduced, the output voltage Vo is reduced, and the feedback voltage Vfb is further reduced. When the feedback voltage Vfb is between the low reference voltage Vref _ L and the high reference voltage Vref _ H, the duty ratio of the pulse generated by the pulse generator is kept unchanged. Therefore, by the embodiment of fig. 3, the output voltage can be stabilized within an interval range, and the following relationship is satisfied:
Figure BDA0002844135480000131
as shown in fig. 4, a preferred embodiment of the discharge control circuit 22 in the present invention. The discharge control circuit comprises a first discharge NOT gate DF1, a first discharge P-type MOS tube DP1, a second discharge P-type MOS tube DP2, a third discharge P-type MOS tube DP3, a first discharge N-type MOS tube DN1, a second discharge N-type MOS tube DN2 and a third discharge N-type MOS tube DN 3; the input end of the first discharging not gate DF1 is electrically connected with the gate of the second discharging N-type MOS transistor DN2, and the output end of the first discharging not gate DF1 is electrically connected with the gate of the first discharging N-type MOS transistor DN 1; the drain electrode of the first discharge P-type MOS tube DP1 is electrically connected with the drain electrode of the first discharge N-type MOS tube DN1 to be used as a first drain electrode connection point, and the first drain electrode connection point is electrically connected with the grid electrode of the second discharge P-type MOS tube DP 2; the drain electrode of the second discharge P-type MOS transistor DP2 is electrically connected with the drain electrode of the second discharge N-type MOS transistor DN2 to serve as a second drain electrode connection point, and the second drain electrode connection point is electrically connected with the grid electrode of the first discharge P-type MOS transistor DP 1;
the grid electrode of the third discharging P-type MOS tube DP3 is electrically connected with the grid electrode of the third discharging N-type MOS tube DN3 to be used as a first grid electrode connection point, and the first grid electrode connection point is electrically connected with the second drain electrode connection point; the drain electrode of the third discharge P-type MOS tube DP3 is electrically connected with the drain electrode of the third discharge N-type MOS tube DN3 to form a third drain electrode connection point, which is the output end of the discharge control circuit;
the source electrode of the first discharge P-type MOS tube DP1, the source electrode of the second discharge P-type MOS tube DP2 and the source electrode of the third discharge P-type MOS tube DP3 are electrically connected with the output end VP of the voltage control circuit and used as the control voltage of the discharge control circuit; the source electrode of the first discharging N-type MOS tube DN1 and the source electrode of the second discharging N-type MOS tube DN2, and the source electrode of the third discharging N-type MOS tube DN3 are electrically connected with the grounding pin of the battery protection chip and used as the second voltage of the discharging control circuit.
The discharge control circuit can generate an output control voltage from the output terminal VP of the voltage control circuit to control the gate of the first NMOS transistor FET1, and the corresponding voltage value is the control voltage or the second voltage, i.e., the battery negative terminal voltage GND, respectively, thereby implementing on/off control of the first NMOS transistor FET 1.
When the discharge control signal DO _ crtl is at a high level, the second discharge N-type MOS transistor DN2 is turned on, and the first discharge N-type MOS transistor DN1 is turned off through the not gate. The drain of the second discharging N-type MOS transistor DN2 is at low level, the first discharging P-type MOS transistor DP1 is turned on, the second discharging P-type MOS transistor DP2 is turned off, the third discharging P-type MOS transistor DP3 is turned on, and the third discharging N-type MOS transistor DN3 is turned off, so that the output terminal DO of the discharging control circuit outputs the control voltage from the output terminal VP of the voltage control circuit; when the discharge control signal DO _ crtl is at a low level, the second discharge N-type MOS transistor DN2 is turned off, and the first discharge N-type MOS transistor DN1 is turned on through the not gate. The second discharge P-type MOS transistor DP2 is turned on, the first discharge P-type MOS transistor DP1 is turned off, the drain of the second discharge N-type MOS transistor DN2 is at a high level, the third discharge P-type MOS transistor DP3 is turned off, and the third discharge N-type MOS transistor DN3 is turned on, so that the output terminal DO of the discharge control circuit outputs the negative terminal voltage GND of the battery from the ground pin, that is, the second voltage.
As shown in fig. 5, in a preferred embodiment of the charging control circuit of the present invention, the charging control circuit includes a first charging not gate C _ F1, a first charging P-type MOS transistor C _ P1, a second charging P-type MOS transistor C _ P2, a third charging P-type MOS transistor C _ P3, a fourth charging P-type MOS transistor C _ P4, a fifth charging P-type MOS transistor C _ P5, a sixth charging P-type MOS transistor C _ P6, a first charging N-type MOS transistor C _ N1, a second charging N-type MOS transistor C _ N2, a third charging N-type MOS transistor C _ N3, a fourth charging N-type MOS transistor C _ N4, a fifth charging N-type MOS transistor C _ N5, and a sixth charging N-type MOS transistor C _ N6; the input end of the first charging not gate C _ F1 is electrically connected with the gate of a second charging P-type MOS transistor C _ P2, and the output end of the first charging not gate C _ F1 is electrically connected with the gate of the first charging P-type MOS transistor C _ P1;
the drain electrode of the first charging P-type MOS transistor C _ P1 is electrically connected with the drain electrode of the first charging N-type MOS transistor C _ N1 to serve as a first charging drain electrode connection point, and the first charging drain electrode connection point is electrically connected with the grid electrode of the second charging N-type MOS transistor C _ N2; the drain electrode of the second charging P-type MOS transistor C _ P2 is electrically connected with the drain electrode of the second charging N-type MOS transistor C _ N2 to form a second charging drain electrode connection point, and the second charging drain electrode connection point is electrically connected with the grid electrode of the first charging N-type MOS transistor C _ N1; the grid electrode of the third charging P-type MOS transistor C _ P3 is electrically connected with the grid electrode of the third charging N-type MOS transistor C _ N3 to serve as a first charging grid electrode connection point, the first charging grid electrode connection point is electrically connected with the second charging drain electrode connection point and is also electrically connected with the grid electrode of a fifth charging N-type MOS transistor, the drain electrode of the third charging P-type MOS transistor C _ P3 is electrically connected with the drain electrode of the third charging N-type MOS transistor C _ N3 to serve as a third charging drain electrode connection point and is electrically connected with the grid electrode of the fourth charging N-type MOS transistor C _ N4; the source electrode of the first charging P-type MOS tube C _ P1 is electrically connected with the source electrode of the second charging P-type MOS tube C _ P2 and the source electrode of the third charging P-type MOS tube C _ P3, is electrically connected with a power supply pin of the battery protection chip, and is connected to the positive electrode end VDD of the battery;
the drain electrode of the fourth charging P-type MOS transistor C _ P4 is electrically connected with the drain electrode of the fourth charging N-type MOS transistor C _ N4 to form a fourth charging drain electrode connection point, and the fourth charging drain electrode connection point is electrically connected with the gate electrode of the fifth charging P-type MOS transistor C _ P5; the drain electrode of the fifth charging P-type MOS transistor C _ P5 is electrically connected with the drain electrode of the fifth charging N-type MOS transistor C _ N5 to form a fifth charging drain electrode connection point, and the fifth charging drain electrode connection point is electrically connected with the gate electrode of the fourth charging P-type MOS transistor C _ P4; the grid electrode of the sixth charging P-type MOS transistor C _ P6 is electrically connected with the grid electrode of the sixth charging N-type MOS transistor C _ N6 to serve as a second charging grid electrode connection point, and the second charging grid electrode connection point is electrically connected with the fifth charging drain electrode connection point; the drain of the sixth charging P-type MOS transistor C _ P6 is electrically connected to the drain of the sixth charging N-type MOS transistor C _ N6 to serve as a sixth charging drain connection point, which is the output terminal CO of the charging control circuit;
the source electrode of the fourth charging P-type MOS transistor C _ P4 is electrically connected with the source electrode of the fifth charging P-type MOS transistor C _ P5 and the source electrode of the sixth charging P-type MOS transistor C _ P6, is electrically connected with the output end of the voltage control circuit, and is used as a driving power supply of the discharging and charging control circuit; the source of the first charging N-type MOS transistor C _ N1, the source of the second charging N-type MOS transistor C _ N2, the source of the third charging N-type MOS transistor C _ N3, the source of the fourth charging N-type MOS transistor C _ N4, the source of the fifth charging N-type MOS transistor C _ N5, and the source of the sixth charging N-type MOS transistor C _ N6 are electrically connected to a current detection pin, and are used as a reference ground of the charging control circuit.
Based on the circuit in fig. 5, when the charge control signal Co _ crtl of the charge control circuit is inputted with a high level, and is applied to the gate of the second charge P-type MOS transistor C _ P2, and outputs a low level, such as 0V voltage, after passing through the first charge not gate C _ F1, and is applied to the gate of the first charge P-type MOS transistor C _ P1, the first charge P-type MOS transistor C _ P1 is turned on, the second charge P-type MOS transistor C _ P2 is turned off, further, the gate voltage applied to the second charge N-type MOS transistor C _ N2 is the positive voltage VDD of the battery, so the second charge N-type MOS transistor C _ N2 is turned on, the first charge N-type MOS transistor C _ N1 is turned off, the voltage at the connection point of the second charge drain is the external power supply, VM is the third voltage, the third charge P-type MOS transistor C _ P3 is turned on, the third charge N-type MOS transistor C _ N3 and the fifth charge N-type MOS transistor C5 are turned off, the voltage at the third charging drain connection point is the positive voltage VDD of the battery, further, the fourth charging N-type MOS tube C _ N4 is turned on, the voltage at the fourth charging drain connection point where the drain of the fourth charging P-type MOS tube C _ P4 and the drain of the fourth charging N-type MOS tube C _ N4 are connected is the external power ground VM, if 0V, the fifth charging P-type MOS tube C _ P5 is turned on, the gate voltage acting on the fourth charging P-type MOS tube C _ P4, the gate voltage acting on the sixth charging P-type MOS tube C _ P6, and the gate voltage acting on the sixth charging N-type MOS tube C _ N6 are the control voltage VP output by the voltage doubling circuit, so the fourth charging P-type MOS tube C _ P4 and the sixth charging P-type MOS tube C _ P6 are turned off, the sixth charging N-type MOS tube C _ N6 is turned on, and the output terminal voltage DO of the discharging control circuit is equal to the external power ground voltage VM; based on the same principle, when the charge control signal Co _ crtl inputs a low level, for example, 0V voltage, and acts on the gate of the second charge P-type MOS C _ P2, and outputs a high level after passing through the first charge not gate C _ F1, and acts on the gate of the first charge P-type MOS C _ P1, the first charge P-type MOS C _ P1 is turned off, the second charge P-type MOS C _ P2 is turned on, further, the gate voltage acting on the first charge N-type MOS C _ N1 is the positive voltage VDD of the battery, so that the first charge N-type MOS C _ N1 is turned on, the second charge N-type MOS C _ N2 is turned off, the voltage at the second charge drain connection point is the positive voltage VDD of the battery, further, the third charge P-type MOS C _ P3 is turned off, the third charge N-type MOS C _ N3 and the fifth charge N-type MOS C _ N5 are turned on, and the charge drain connection point is the external source voltage VM, as the voltage of 0V, further, the fourth charging N-type MOS transistor C _ N4 is turned off, the fifth charging N-type MOS transistor C _ N5 is turned on, the voltage at the sixth charging gate connection point where the gate voltage of the fourth charging P-type MOS transistor C _ P4 is connected to the gate of the sixth charging P-type MOS transistor C _ P6 and the gate of the sixth charging N-type MOS transistor C _ N4 is the external power ground VM, the fourth charging P-type MOS transistor C _ P4 and the sixth charging P-type MOS transistor C _ P6 are turned on, the sixth charging N-type MOS transistor C _ N6 is turned off, and the output terminal voltage DO of the discharging control circuit is equal to the control voltage VP output by the voltage doubling circuit. Acts on the gate of the fifth charge N-type MOS transistor C _ N5, and outputs a low level, such as 0V voltage, after passing through the first charge NOT gate C _ F1, acts on the gate of the fourth charge N-type MOS transistor C _ N4, the fourth charge N-type MOS transistor C _ N4 is turned off, the fifth charge N-type MOS transistor C _ N5 is turned on, therefore, the voltage at the second drain connection point where the drain of the fifth charging P-type MOS transistor C _ P5 and the drain of the fifth charging N-type MOS transistor C _ N5 are connected is low, for example, 0V, is applied to the gates of the fourth charging P-type MOS transistor C _ P4 and the sixth charging P-type MOS transistor C _ P6 and the gate of the sixth charging N-type MOS transistor C _ N6, the fourth charging P-type MOS transistor C _ P4 and the fifth charging P-type MOS transistor C _ P5 are turned off, therefore, the sixth charging P-type MOS transistor C _ P6 is turned on, the sixth charging N-type MOS transistor C _ N6 is turned off, the voltage DO at the output of the charge control circuit is equal to the control voltage VP at the output of the voltage doubler circuit.
Based on the same principle, when the charge control signal Co _ crtl of the charge control circuit is inputted with a low level, the fourth charge N-type MOS transistor C _ N4 is turned on, the fifth charge N-type MOS transistor C _ N5 is turned off, so that the voltage at the first charge drain connection point where the drain of the fourth charge P-type MOS transistor C _ P4 and the drain of the fourth charge N-type MOS transistor C _ N4 are connected is a low level, for example, 0V, the fifth charge P-type MOS transistor C _ P5 is turned on, the gate voltage applied to the fourth charge P-type MOS transistor C _ P4 and the gate of the sixth charge P-type MOS transistor C _ P6 and the gate voltage of the sixth charge N-type MOS transistor C _ N6 are the control voltage VP outputted from the voltage doubler circuit, so that the fourth charge P-type MOS transistor C _ P4 and the sixth charge P-type MOS transistor C _ P6 are turned off, the sixth charge N-type MOS transistor C _ N6 is turned on, and the charge output terminal of the charge control circuit Co is equal to the external charge control voltage Co, corresponding to the third voltage.
The charging control circuit can generate an output control voltage from the output terminal VP of the voltage control circuit to control the gate of the second NMOS transistor FET2, and the corresponding voltage value is the control voltage or the external power ground VM, respectively, thereby implementing on/off control of the second NMOS transistor FET 2.
Based on the same conception, the invention also provides a battery protection chip, which is contained in the battery component.
Based on the same concept, the invention also provides an electronic product comprising the battery pack.
It can be seen that the present invention discloses a battery pack, a battery protection chip and an electronic product, wherein, the battery protection chip comprises a power supply pin, a grounding pin, an inductor access pin, a current detection pin, a discharge control pin and a charge control pin, and also comprises a voltage control circuit, a discharge control circuit and a charge control circuit inside the chip, wherein one end of the inductor is connected with the input end of the voltage control circuit, the other end of the inductor is electrically connected with the positive terminal of the battery, the discharge control pin and the charge control pin of the battery protection chip are respectively used for controlling the negative terminal of the battery to be electrically connected with a first NMOS tube, a second NMOS tube electrically connected with the negative electrode terminal of the external power supply, the voltage control circuit generates stable control voltage to make the conduction state of the two NMOS tubes not affected by the voltage drop of the battery, and effectively avoid the potential difference between the inside and the outside caused by the broken connection of the negative end of the battery.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structural changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.

Claims (11)

1. A battery pack comprises a battery and a battery protection chip, and is characterized in that the battery protection chip comprises a power supply pin, a grounding pin, an inductor access pin, a current detection pin, a discharge control pin and a charge control pin, the chip also comprises a voltage control circuit, a discharge control circuit and a charge control circuit, the input end of the voltage control circuit is electrically connected with the inductor access pin, the inductor input pin is electrically connected with an inductor, the other end of the inductor is electrically connected with the positive terminal of the battery, the output end of the voltage control circuit is electrically connected with the input ends of the discharge control circuit and the charge control circuit respectively, the output end of the discharge control circuit is electrically connected with the discharge control pin, and the output end of the charge control circuit is electrically connected with the charge control pin;
the power pin of the battery protection chip is electrically connected with the positive terminal of the battery, the negative terminal of the battery is also electrically connected with the source electrode of the first NMOS tube, the drain electrode of the first NMOS tube is electrically connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is used as the negative connecting terminal shared by the discharging and charging of the battery, and the positive terminal of the battery is used as the positive connecting terminal shared by the discharging and charging of the battery; a discharge control pin of the battery protection chip is electrically connected with a grid electrode of the first NMOS tube, and a charge control pin is electrically connected with a grid electrode of the second NMOS tube;
the negative electrode end of the battery is electrically connected with the grounding pin of the battery protection chip, and the source electrode of the second NMOS tube is electrically connected with the current detection pin of the battery protection chip; the control voltage circuit inputs control voltage to the discharge control circuit, the battery protection chip is used for monitoring the control voltage output by the discharge control circuit through the discharge control pin when the battery is discharged to normally work, and the discharge control circuit outputs second voltage through the discharge control pin when the battery is monitored to be discharged to abnormally work; the control voltage circuit inputs control voltage to the charging control circuit, the battery protection chip is used for monitoring the control voltage output by the charging control circuit through a charging control pin when the battery is charged normally, and the charging control circuit outputs third voltage through the charging control pin when the battery is charged abnormally;
the control voltage of the voltage control circuit keeps stable output and does not change along with the change of the battery voltage;
the difference value of the voltage value of the control voltage minus the voltage value of the negative electrode end of the battery is greater than or equal to the minimum conduction voltage between the grid electrode and the source electrode of the first NMOS tube and is less than the maximum breakdown voltage between the grid electrode and the source electrode of the first NMOS tube; the difference value of the voltage value of the control voltage minus the voltage value of the source electrode of the second NMOS tube is greater than or equal to the minimum breakover voltage between the grid electrode and the source electrode of the second NMOS tube and is less than the maximum breakdown voltage between the grid electrode and the source electrode of the second NMOS tube;
the voltage value of the control voltage is a fixed value, the voltage control circuit comprises a switch tube corresponding to the voltage control circuit, one end of the switch tube is electrically connected with the inductor, the other end of the switch tube is grounded, the control end of the switch tube is electrically connected with an adjustable pulse generator, and pulses generated by the pulse generator are used for conducting or switching off control on two ends of the switch tube;
the junction of the switch tube and the inductor is also connected with the anode of a diode, the cathode of the diode is electrically connected with a capacitor and then grounded, and the voltage generated by the cathode of the diode is the output voltage of the voltage control circuit;
the control end of the pulse generator correspondingly regulates and controls the duty ratio of output pulses of the pulse generator through the feedback voltage of the output voltage of the voltage control circuit, so that the energy storage of the inductor is increased or reduced, and the control voltage is further increased or reduced.
2. The battery assembly of claim 1, wherein the second voltage is a voltage at a negative terminal of the battery, and the third voltage is a voltage at a source of the second NMOS transistor.
3. The battery assembly of claim 1,
the negative electrode of the diode is also electrically connected with a first feedback resistor and a second feedback resistor which are connected in series and then grounded, and the connection position between the first feedback resistor and the second feedback resistor is electrically connected with the control end of the pulse generator.
4. The battery pack of claim 3, wherein the control terminal of the pulse generator is electrically connected to an error operational amplifier, one input terminal of the error operational amplifier is connected to a reference voltage, the other input terminal of the error operational amplifier is connected to a feedback voltage from a connection point between the first feedback resistor and the second feedback resistor, and the output terminal of the error operational amplifier is connected to the control terminal of the pulse generator.
5. The battery pack of claim 4, wherein the pulse generator is further coupled to an oscillator, the oscillator inputting an oscillating signal as a signal source for the pulse generator to generate the pulse output.
6. The battery assembly according to claim 1, wherein the voltage value of the control voltage is an interval value, the voltage control circuit includes a switching tube, one end of the switching tube is electrically connected to the inductor, the other end of the switching tube is grounded, a control end of the switching tube is electrically connected to an adjustable pulse generator, and a pulse generated by the pulse generator is used for controlling the connection or disconnection of the two ends of the switching tube;
the junction of the switch tube and the inductor is also connected with the anode of a diode, the cathode of the diode is electrically connected with a capacitor and then grounded, and the voltage generated by the cathode of the diode is the output voltage of the voltage control circuit;
the negative electrode of the diode is also electrically connected with a first feedback resistor and a second feedback resistor which are connected in series and then grounded, the joint between the first feedback resistor and the second feedback resistor is respectively and electrically connected with the positive input end of a first comparator and the negative input end of a second comparator, the negative input end of the first comparator is connected with a low reference voltage, the positive input end of the second comparator is connected with a high reference voltage, and the output end of the second comparator and the output end of the first comparator are respectively connected with two control input ends of a pulse generator.
7. The battery pack according to any one of claims 1 to 6, wherein the discharge control circuit comprises a first discharge not gate, a first discharge P-type MOS transistor, a second discharge P-type MOS transistor, a third discharge P-type MOS transistor, a first discharge N-type MOS transistor, a second discharge N-type MOS transistor, and a third discharge N-type MOS transistor; the input end of the first discharging NOT gate is electrically connected with the grid electrode of the second discharging N-type MOS tube, and the output end of the first discharging NOT gate is electrically connected with the grid electrode of the first discharging N-type MOS tube; the drain electrode of the first discharging P-type MOS tube is electrically connected with the drain electrode of the first discharging N-type MOS tube to serve as a first drain electrode connection point, and the first drain electrode connection point is electrically connected with the grid electrode of the second discharging P-type MOS tube; the drain electrode of the second discharge P-type MOS tube is electrically connected with the drain electrode of the second discharge N-type MOS tube to serve as a second drain electrode connection point, and the second drain electrode connection point is electrically connected with the grid electrode of the first discharge P-type MOS tube;
a grid electrode of the third discharging P-type MOS tube is electrically connected with a grid electrode of the third discharging N-type MOS tube to serve as a first grid electrode connection point, and the first grid electrode connection point is electrically connected with the second drain electrode connection point; the drain electrode of the third discharge P-type MOS tube is electrically connected with the drain electrode of the third discharge N-type MOS tube to serve as a third drain electrode connection point which is the output end of the discharge control circuit;
the source electrode of the first discharge P-type MOS tube, the source electrode of the second discharge P-type MOS tube and the source electrode of the third discharge P-type MOS tube are electrically connected with the output end of the voltage control circuit and used as the control voltage of the discharge control circuit; and the source electrode of the first discharging N-type MOS tube is electrically connected with the source electrode of the second discharging N-type MOS tube, and the source electrode of the third discharging N-type MOS tube is electrically connected with the grounding pin of the battery protection chip and is used as a second voltage of the discharging control circuit.
8. The battery pack according to any of claims 1-6, wherein the charge control circuit comprises a first charge not gate, a first charge P-type MOS transistor, a second charge P-type MOS transistor, a third charge P-type MOS transistor, a fourth charge P-type MOS transistor, a fifth charge P-type MOS transistor, a sixth charge P-type MOS transistor, a first charge N-type MOS transistor, a second charge N-type MOS transistor, a third charge N-type MOS transistor, a fourth charge N-type MOS transistor, a fifth charge N-type MOS transistor, and a sixth charge N-type MOS transistor; the input end of the first charging NOT gate is electrically connected with the grid electrode of the second charging P-type MOS tube, and the output end of the first charging NOT gate is electrically connected with the grid electrode of the first charging P-type MOS tube;
the drain electrode of the first charging P-type MOS tube is electrically connected with the drain electrode of the first charging N-type MOS tube to serve as a first charging drain electrode connecting point, and the first charging drain electrode connecting point is electrically connected with the grid electrode of the second charging N-type MOS tube; the drain electrode of the second charging P-type MOS tube is electrically connected with the drain electrode of the second charging N-type MOS tube to serve as a second charging drain electrode connecting point, and the second charging drain electrode connecting point is electrically connected with the grid electrode of the first charging N-type MOS tube; the grid electrode of the third charging P-type MOS tube is electrically connected with the grid electrode of the third charging N-type MOS tube to serve as a first charging grid electrode connecting point, the first charging grid electrode connecting point is electrically connected with the second charging drain electrode connecting point and is also electrically connected with the grid electrode of a fifth charging N-type MOS tube, and the drain electrode of the third charging P-type MOS tube is electrically connected with the drain electrode of the third charging N-type MOS tube to serve as a third charging drain electrode connecting point and is electrically connected with the grid electrode of the fourth charging N-type MOS tube; the source electrode of the first charging P-type MOS tube is electrically connected with the source electrode of the second charging P-type MOS tube and the source electrode of the third charging P-type MOS tube and is electrically connected with a power pin of the battery protection chip;
the drain electrode of the fourth charging P-type MOS tube is electrically connected with the drain electrode of the fourth charging N-type MOS tube to serve as a fourth charging drain electrode connection point, and the fourth charging drain electrode connection point is electrically connected with the grid electrode of the fifth charging P-type MOS tube; the drain electrode of the fifth charging P-type MOS tube is electrically connected with the drain electrode of the fifth charging N-type MOS tube to serve as a fifth charging drain electrode connection point, and the fifth charging drain electrode connection point is electrically connected with the grid electrode of the fourth charging P-type MOS tube; a grid electrode of the sixth charging P-type MOS tube is electrically connected with a grid electrode of the sixth charging N-type MOS tube to serve as a second charging grid electrode connecting point, and the second charging grid electrode connecting point is electrically connected with the fifth charging drain electrode connecting point; the drain electrode of the sixth charging P-type MOS tube is electrically connected with the drain electrode of the sixth charging N-type MOS tube to serve as a sixth charging drain electrode connection point which is the output end of the charging control circuit;
the source electrode of the fourth charging P-type MOS tube is electrically connected with the source electrode of the fifth charging P-type MOS tube and the source electrode of the sixth charging P-type MOS tube, and is electrically connected with the output end of the voltage control circuit to be used as the control voltage of the charging control circuit; the source electrode of the first charging N-type MOS tube, the source electrode of the second charging N-type MOS tube, the source electrode of the third charging N-type MOS tube, the source electrode of the fourth charging N-type MOS tube, the source electrode of the fifth charging N-type MOS tube and the source electrode of the sixth charging N-type MOS tube are electrically connected, and are all electrically connected with the current detection pin to serve as a third voltage of the charging control circuit.
9. The battery pack according to any one of claims 1 to 6, further comprising a current detection circuit, wherein the current detection circuit comprises a second current limiting resistor electrically connected to the source of the second NMOS transistor, and the other end of the second current limiting resistor is connected to the current detection pin.
10. A battery protection chip, wherein the battery protection chip is a battery protection chip contained in a battery pack according to any one of claims 1 to 9.
11. An electronic product, characterized in that it comprises a battery pack according to any one of claims 1 to 10.
CN202011503334.2A 2020-12-17 2020-12-17 Battery pack, battery protection chip and electronic product Active CN112583078B (en)

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