CN112582433B - Display panel and display device - Google Patents
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- CN112582433B CN112582433B CN202011567535.9A CN202011567535A CN112582433B CN 112582433 B CN112582433 B CN 112582433B CN 202011567535 A CN202011567535 A CN 202011567535A CN 112582433 B CN112582433 B CN 112582433B
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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Abstract
The embodiment of the invention discloses a display panel and a display device, which comprise a substrate, wherein the substrate comprises a hollow part, a first non-display area, a display area and a second non-display area; the first non-display area surrounds the hollow part, the display area surrounds the first non-display area, and the second non-display area surrounds the display area; the wiring area is positioned in the first non-display area and surrounds the hollow part; a plurality of signal lines arranged in a first direction, the plurality of signal lines including at least one first signal line partially overlapping the first non-display area; the first signal line comprises a first sub-signal line and a second sub-signal line which are positioned at two sides of the hollow part along the second direction, and the first sub-signal line and the second sub-signal line are positioned in the display area; and the signal lead is positioned in the first non-display area, is connected with the first sub-signal line and the second sub-signal line of the same first signal line, and is positioned on one side, close to the hollow part, of the wiring area at least in part. Therefore, the crack detection efficiency of the display panel can be effectively improved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
Along with the development of market, the consumer requires more and more severer to the display effect of display screen, and comprehensive screen technique through the design of super narrow frame even no frame, pursues higher screen to account for than, and under the unchangeable condition of fuselage, display area maximize, the display effect is more amazing. Based on the structural design of full face screen, need punch in order to install camera, earphone, inductor etc. in the panel display region.
And the display area is punched in the display panel manufacturing process, cracks are possibly generated around the holes due to heat influence or mechanical impact, the cracks expand to the inside of the display screen after the electronic product is used for a period of time, a circuit is damaged, and the display of the display screen is abnormal, and meanwhile, impurities such as external water vapor, dust and the like easily enter the display screen from the cracks, so that the reliability of the display screen is low.
Disclosure of Invention
In view of this, the present invention provides a display panel and a display device, which can effectively improve crack detection efficiency of the display panel and improve product quality.
In one aspect, the present invention provides a display panel comprising:
the display device comprises a substrate, a first display area, a second display area and a display area, wherein the substrate comprises a hollow part, the first non-display area, the display area and the second non-display area; the first non-display area surrounds the hollow-out part, the display area surrounds the first non-display area, and the second non-display area surrounds the display area; a wiring area located in the first non-display area and surrounding the hollow portion; a plurality of signal lines arranged in a first direction, the plurality of signal lines including at least one first signal line partially overlapping the first non-display area; the first signal line comprises a first sub-signal line and a second sub-signal line which are positioned at two sides of the hollow part along a second direction, the first sub-signal line and the second sub-signal line are positioned in the display area, and the first direction is crossed with the second direction; and the signal lead is positioned in the first non-display area, is connected with a first sub-signal line and a second sub-signal line of the same first signal line, and is positioned on one side, close to the hollow part, of the wiring area at least in part.
In another aspect, the present invention also provides a display device, including:
the display panel according to the first aspect.
Compared with the prior art, the display panel and the display device provided by the invention have the following beneficial effects that: the signal transmission of the first signal line is realized by arranging a signal lead and connecting a first sub-signal line and a second sub-signal line of the same first signal line; meanwhile, at least part of the signal leads are arranged on one side, close to the hollow portion, of the wiring area, whether cracks exist around the hollow portion or not can be detected through the display condition of the sub-pixels connected with the first signal lines, and therefore an independent crack detection line does not need to be arranged, the signal lines are simplified when real-time detection is achieved, and display quality is guaranteed.
Drawings
Fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention;
FIG. 2 is a partial schematic view of the area Q1 of FIG. 1;
FIG. 3 is another schematic view of a portion of the area Q1 of FIG. 1;
FIG. 4 is a schematic plane structure diagram of another display panel according to an embodiment of the present invention;
FIG. 5 is a schematic view of a further partial structure of the region Q1 in FIG. 1;
FIG. 6 is a schematic view of a further partial structure of the region Q1 in FIG. 1;
FIG. 7 is a schematic view of a further partial structure of the region Q1 of FIG. 1;
FIG. 8 is a schematic cross-sectional view of section CC' of FIG. 7;
FIG. 9 is a schematic cross-sectional view of section CC' of FIG. 7;
FIG. 10 is a schematic cross-sectional view of section CC' of FIG. 7;
FIG. 11 is a schematic cross-sectional view of section CC' of FIG. 7;
FIG. 12 is a schematic cross-sectional view of section CC' of FIG. 7;
FIG. 13 is a schematic cross-sectional view of section CC' of FIG. 7;
fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict. Also, the shapes and sizes of the various elements in the drawings are not to scale and are merely intended to illustrate the present invention.
In order to better understand the technical solutions of the present invention, the following detailed descriptions of the technical solutions of the present invention are provided with the accompanying drawings and specific embodiments, and it should be understood that the specific features in the embodiments and examples of the present invention are detailed descriptions of the technical solutions of the present invention, and are not limitations of the technical solutions of the present invention, and the technical features in the embodiments and examples of the present invention may be combined with each other without conflict.
Referring to fig. 1 and fig. 2 in combination, fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention, and fig. 2 is a schematic partial structure view of a region Q1 in fig. 1. The present invention provides a display panel including: a substrate (not shown) including a hollow portion LA, a first non-display area NA1, a display area AA, and a second non-display area NA 2; the first non-display area NA1 surrounds the hollow portion LA, the display area AA surrounds the first non-display area NA1, and the second non-display area NA2 surrounds the display area AA; a wiring area NW located in the first non-display area NA1 and surrounding the hollow LA; a plurality of signal lines 10 arranged in the first direction a, the plurality of signal lines 10 including at least one first signal line 11, the first signal line 11 partially overlapping the first non-display area NA 1; the first signal line 11 includes a first sub-signal line 111 and a second sub-signal line 112 located at two sides of the hollow portion LA along the second direction b, the first sub-signal line 111 and the second sub-signal line 112 are located in the display area AA, and the first direction a intersects with the second direction b; the signal lead Y is located in the first non-display area NA1, the signal lead Y connects the first sub-signal line 111 and the second sub-signal line 112 of the same first signal line 11, and at least a portion of the signal lead Y is located on a side of the wiring area NW close to the hollow portion LA.
Specifically, the display area AA of the display panel is mainly used for displaying a picture, a part of the display panel other than the display area AA is a non-display area, the non-display area does not display the picture, and structures such as a circuit and a circuit board for driving and/or detecting picture display may be generally arranged. In this embodiment, the non-display area includes first non-display area NA1 and second non-display area NA2, and first non-display area NA1 surrounds the setting of fretwork portion LA, and second non-display area NA2 surrounds the setting of display area AA, and display area AA surrounds first non-display area NA1 and sets up, thereby can install devices such as camera in fretwork portion LA, be favorable to improving display panel's screen to account for than, it designs to change into narrow frame more easily.
It should be noted that, on the basis of satisfying the above structural relationship, the shape and the number of the hollowed-out portions LA may be designed according to actual use requirements. In fig. 2, the shape of the hollow-out portion LA is exemplarily provided in a circular shape, which is only a specific example of the present application and is not a limitation of the present application. In actual installation, the shape of the hollow-out portion LA is optionally a polygon (such as a rectangle) or an ellipse. Similarly, the shape of the first non-display area NA1 may also be a polygon, a circle, an ellipse, or the like.
The first direction a may be an arrangement direction of scanning lines (not shown in fig. 1 and 2) in the display panel, or may also be an arrangement direction of data lines (not shown in fig. 1 and 2), which is not limited in this embodiment. For convenience of explanation, the first direction a is taken as a row direction, and the second direction b is taken as a column direction.
It is understood that the hollow portion LA is a through hole penetrating through the display panel. Due to the existence of the hollow portion LA, the related routing originally passing through the position of the hollow portion LA needs to be wound around the hollow portion LA in order to realize the uninterrupted signal transmission, thereby forming the routing area NW. In order to realize a narrow frame of the display panel, the relevant wirings are closely arranged in the wiring region NW.
The display panel is usually provided with a plurality of sub-pixels arranged along a first direction a and a second direction b, and the first signal lines 11 can be electrically connected with the pixel circuits of the sub-pixels in the same column, so as to provide signals required by related display for the display of the sub-pixels in the same column. The first signal line 11 partially overlaps the first non-display area NA1, and the first signal line 11 includes a first sub-signal line 111 and a second sub-signal line 112 located at two sides of the hollow portion LA along the second direction b, meaning that the first signal line 11 needs to have a partial line segment located in the first non-display area NA1 due to the hollow portion LA; in other words, the signal transmission of the first signal line 11 needs to pass through the first non-display area NA 1.
The signal lead Y connects the first sub-signal line 111 and the second sub-signal line 112 of the same first signal line 11, that is, the first sub-signal line 111 and the second sub-signal line 112 corresponding to the same column of sub-pixels are connected by the signal Y at two sides of the hollow portion LA along the second direction, thereby realizing signal transmission.
The display area is perforated during the manufacturing process of the display panel, and cracks may be generated around the holes due to thermal influence or mechanical impact, and the cracks may affect the normal display of the display panel. In the present invention, at least a portion of the signal lead Y is disposed at a side of the wiring area NW close to the via-out portion LA, and the portion of the signal lead may be as close to the cutting line of the via-out portion LA as possible, so that when a crack occurs around the via-out portion LA, the signal lead Y at the side of the wiring area NW close to the via-out portion LA will be broken, and if a circuit (e.g., a driving chip IC) providing a related signal source for the first signal line 11 is located at a lower end (e.g., a lower end in fig. 1 and 2) of the via-out portion LA, the first sub-signal line 111 and the second sub-signal line 112 corresponding to the same column of sub-pixels cannot be electrically connected, so that the related signal can only be loaded onto the second sub-signal line 112, and cannot be loaded onto the first sub-signal line 111. Thereby, the sub-pixel corresponding to the second sub-signal line 112 can be lit/brighter, and the sub-pixel corresponding to the first sub-signal line 111 cannot be lit/brighter, at which time the sub-pixel corresponding to the signal line 10 that does not overlap the hollow portion LA can be lit/brighter; alternatively, the sub-pixel corresponding to the second sub-signal line 112 may not be lit/brighter, and the sub-pixel corresponding to the first sub-signal line 111 may be lit/brighter, and at this time, the sub-pixel corresponding to the signal line 10 that does not overlap the hollow portion LA may not be lit/brighter. That is, when the line is cracked around the hollow portion LA, when the same image needs to be displayed, the sub-pixel located at the upper side of the hollow portion LA is brighter or darker than the sub-pixels located in other remaining areas (e.g., the lower side, the left side, and the right side areas) of the hollow portion LA, that is, the display conditions are different, and an abnormality occurs.
For example, the display panel is an Organic Light Emitting Diode (OLED) display panel, the signal line 10 is an initialization signal line (Vref), when a line around the hollow portion LA is cracked, the sub-pixel located on the upper side of the hollow portion LA cannot be initialized compared with other remaining areas, when a first frame of picture is displayed, the difference of the whole display panel may not be obvious, but when a next frame needs to be displayed in a dark state, since the N1 node (taking the pixel circuit as 7T1C, and the N1 node as an example of being connected to the gate of the driving transistor) of the pixel circuit corresponding to the sub-pixel on the upper side of the hollow portion LA cannot be initialized, the sub-pixel cannot emit a darker Light than the previous frame, and the N1 node of the pixel circuit of the sub-pixel in the remaining areas can be initialized normally, the sub-pixel circuit can emit a darker Light than the previous frame; the display result finally presented is that the area on the upper side of the hollow-out portion LA is brighter than the other areas. It can be understood that, if the next frame needs to be displayed in a bright state, the area on the upper side of the hollow portion LA is darker than other areas. Therefore, whether cracks occur around the hollow part LA can be directly judged by observing whether the sub-pixels on the upper side of the hollow part LA are abnormal.
The display panel provided by the embodiment at least has the following technical effects:
by arranging a signal lead, a first sub-signal line 111 and a second sub-signal line 112 of the same first signal line 11 are connected, so that signal transmission of the first signal line 11 is realized; meanwhile, at least part of the signal lead Y is arranged on one side, close to the hollow part LA, of the wiring area NW, whether cracks exist around the hollow part LA can be detected through the display condition of the sub-pixels connected with the first signal line 11, and therefore an independent crack detection line does not need to be arranged, real-time detection is achieved, signal line arrangement is facilitated to be simplified, and display quality is guaranteed.
In some alternative embodiments, with continued reference to fig. 1 and 2, the signal line 10 is a supply voltage signal line (PVDD). The display panel is usually provided with a plurality of power voltage signal lines extending along the column direction, the sub-pixels usually include light emitting elements and driving circuits for driving the light emitting elements to emit light, and the power voltage signal lines can provide power voltage signals for the driving circuits of the sub-pixels, which is helpful for realizing the display function of the OLED display panel.
The signal line 10 is a power voltage signal line, when a line crack is formed around the hollow-out portion LA, if the crack is generated before the image is displayed, the sub-pixel located on the upper side of the hollow-out portion LA can still perform initialization and data signal writing compared with other remaining areas, but cannot receive a power voltage signal in a light-emitting stage, and therefore cannot be lit; while the sub-pixels of the remaining regions can still be lit normally. If the crack is generated in the process of displaying the image, the sub-pixel on the upper side of the hollow portion LA cannot receive the power voltage signal when displaying the next frame of image, and is darker or brighter than other areas. Therefore, whether cracks appear around the hollow part LA can be directly judged by observing whether the sub-pixels on the upper side of the hollow part LA display abnormal conditions.
In some alternative embodiments, the signal leads Y may correspond to the first signal lines 11 one to one, that is, one signal lead is connected to one first sub-signal line 111 and one second sub-signal line 112. In this case, since it is necessary to provide a large number of signal leads in the first non-display region, the detection accuracy can be improved when detecting cracks.
In some alternative embodiments, referring to fig. 1 to 6, fig. 3 is a schematic partial structure diagram of a region Q1 in fig. 1, fig. 4 is a schematic plan structure diagram of another display panel provided in an embodiment of the present invention, fig. 5 is a schematic partial structure diagram of a region Q1 in fig. 1, and fig. 6 is a schematic partial structure diagram of a region Q1 in fig. 1. The signal lead Y is connected to the first sub-signal line 111 and the second sub-signal line 112 of the plurality of first signal lines 11.
Specifically, in fig. 2, one signal lead Y corresponds to two first signal lines 11, that is, one signal lead Y is connected to two first sub-signal lines 111 and two second sub-signal lines 112; in fig. 3 to 6, one signal lead line Y corresponds to four first signal lines 11, that is, one signal lead line Y is connected to four first sub-signal lines 111 and four second sub-signal lines 112. Through corresponding the connection of a signal lead Y and the first sub-signal line 111 and the second sub-signal line 112 of many first signal lines 11, can reduce the quantity of the signal lead Y of first non-display area NA1 when utilizing first signal line 11 to realize the crack detection to realize narrow frame, increase the screen and account for than, improve user experience.
In some alternative embodiments, referring to fig. 3 to 6, the hollowed-out portion LA is configured to be a circle having a symmetry axis (not shown in the figures) parallel to the second direction b, and the first sub-signal lines 111 and the second sub-signal lines 112 of all the first signal lines 11 located at the left side of the symmetry axis are connected by one signal lead Y; the first sub-signal line 111 and the second sub-signal line 112 of all the first signal lines 11 located on the right side of the symmetry axis are connected by one signal lead Y. Therefore, when a crack appears on the left side of the hollow part LA, the sub-pixels in the area on the upper left side of the hollow part LA cannot be normally displayed and are abnormal by taking the symmetry axis as a boundary; when the right side of the hollow part LA has cracks, the sub-pixels in the area on the upper right side of the hollow part LA cannot be normally displayed, and abnormality occurs. Thus, the position where the crack occurred can be roughly determined. In addition, a signal lead Y is respectively arranged on the left side and the right side of the hollow part LA close to the wiring area NW, the number of the signal leads Y arranged between the hollow part LA and the wiring area NW can be reduced, the narrow frame of the display panel is favorably realized, and the screen occupation ratio is increased. In addition, a small number of signal lines Y are arranged, so that the overlapping area of the signal leads Y and the wiring area NW can be reduced, signal interference is avoided, signal stability is improved, and the display effect is improved.
In some alternative embodiments, referring to fig. 4, the second non-display area NA2 includes a first sub non-display area NA21 and a second sub non-display area NA22 located at both sides of the display area AA along the second direction b, the first sub non-display area NA21 being provided with a plurality of pads 30; the plurality of signal lines 10 include a plurality of second signal lines 12, the second signal lines 12 not overlapping the first non-display area NA 1; in the first sub non-display area NA21, the at least one first signal line 11 and the at least one second signal line 12 are shorted by the first connection line L1; in the second sub non-display area NA22, all the first signal lines 11 are spaced apart from each other and from any one of the second signal lines 12, and at least two of the second signal lines 12 are shorted by a second connection line L2.
The display panel includes a substrate 20, the second non-display area NA2 includes a first sub non-display area NA21 and a second sub non-display area NA22, the first sub non-display area NA21 is provided with a plurality of pads, the pads may correspond to signal input pins or signal output pins of an IC, that is, the first sub non-display area NA21 is an IC bonding area or an area close to the IC, and the second sub non-display area NA22 is an area far away from the IC. That is, the first sub-signal line 111 is located in the display area AA of the side of the hollow portion LA away from the IC, and the second sub-signal line 112 is located in the display area AA of the side of the hollow portion LA close to the IC.
The present embodiment will be described by taking the signal line 10 as a power supply voltage signal line as an example.
Because the power voltage signal line provides a power voltage signal for each sub-pixel in the display area AA, the power voltage signal line is generally set to be long, and due to the internal resistance, the attenuation of the power voltage signal may be caused, so that a voltage drop is generated, and the display quality of a display picture is affected; therefore, by shorting all of the first and second signal lines 11 and 12 within the first sub non-display area NA21 through the first connection line L1 (i.e., the second sub-signal line 112 and the second signal line 12 within the first sub non-display area NA21 through the first connection line L1), and shorting at least two of the second signal lines 12 within the second sub non-display area NA22 through the second connection line L2, it is possible to reduce a voltage drop and improve display quality of the display panel.
In the second sub non-display area NA22, all the first signal lines 11 are spaced from each other and spaced from any one of the second signal lines 12, that is, one end of all the first sub-signal lines 111 in the second sub non-display area NA22 is no longer connected to each other through a connection line, and one end of any one of the first sub-signal lines 111 in the second sub-non-display area NA22 is also not connected to the second signal line 12, so that when a crack occurs around the hollow portion LA, the first sub-signal line 111 cannot receive a power supply voltage signal, and therefore, a sub-pixel on the upper side of the hollow portion LA has an abnormal display. Therefore, whether cracks appear around the hollow part LA can be directly judged by observing whether the sub-pixels on the upper side of the hollow part LA display abnormal conditions.
In the second sub non-display area NA22, at least two second signal lines 12 are shorted by a second connection line L2, which can further reduce voltage drop and improve the display quality of the display panel.
In some alternative embodiments, referring to fig. 5 and 6, the signal lead Y includes a first sub-lead Y1, a second sub-lead Y2, and a first sub-winding Y3 connecting the first sub-lead Y1 and the second sub-lead Y2, the first sub-lead Y1 and the second sub-lead Y2 both at least partially overlap the wiring region NW, and the first sub-winding Y3 is located at a side of the wiring region NW near the via LA; the first sub-winding Y3 snakes around the hollowed-out portion LA.
The first sub-lead Y1 and the second sub-lead Y2 at least partially overlap the wiring area NW, that is, the signal line Y at least partially overlaps the wiring area NW when extending from a side of the wiring area NW away from the via LA to a side of the wiring area NW close to the via LA.
Referring to fig. 5, the first sub-winding Y3 shows approximately 3 half turns in the left area of the routing area NW in the area LA, and the first sub-winding Y3 shows approximately 3 half turns in the right area of the routing area NW in the area LA. Referring to fig. 6, the first sub-winding Y3 shows approximately 5 half turns in the left area of the routing area NW in the area LA, and the first sub-winding Y3 shows approximately 5 half turns in the right area of the routing area NW in the area LA. The first sub-winding Y3 of the signal lead Y is exemplified by a winding of 3 half turns or 5 half turns, and the first sub-winding Y3 is formed in a serpentine shape (a meandering shape or a zigzag shape) by a plurality of windings of half turns.
By routing the first sub-winding Y3 in a serpentine shape around the hollow LA, that is, by providing the first sub-winding Y3 as a bent portion, the signal lead Y can be more wound between the wiring area NW and the hollow LA, so that the crack around the hollow LA is more easily detected.
In some alternative embodiments, referring to fig. 1 and 7, fig. 7 is a schematic view of a partial structure of a region Q1 in fig. 1.
The display panel further includes a plurality of data lines 40 arranged in a first direction a; the data line 40 passing through the wiring area NW includes a first sub data line 41, a second sub data line 42 and a data lead 43, the first sub data line 41 and the second sub data line 42 are located in the display area AA, and the data lead 43 is located in the wiring area NW; the first sub data line 41 and the second sub data line 42 of the same data line 40 are connected by corresponding data leads 43. A plurality of scan lines 50 arranged in a second direction; the scan line 50 passing through the wiring area NW includes a first sub-scan line 51, a second sub-scan line 52, and a scan lead 53, the first sub-scan line 51 and the second sub-scan line 52 are located in the display area AA, and the scan lead 53 is located in the wiring area NW; the first sub-scanning line 51 and the second sub-scanning line 52 of the same scanning line 50 are connected by corresponding scanning wirings 53.
Due to the existence of the hollow portion LA, the data line 40 is divided into a first sub data line 41 and a second sub data line 42 in the display area AA, and a data lead line 43 in the first non-display area NA 1. To minimize the size of the first non-display NA1 and the crosstalk between different signal lines 40, for example, it is necessary to properly route the data leads 43 located in the first non-display area NA 1. Similarly, the scan lines 50 are also laid out, and the scan lines 53 in the first non-display area NA1 are also required to be laid out. Specifically, as shown in fig. 7, a wiring area NW surrounding the hollow portion LA is provided at a position where the first non-display area NA1 is close to the display area AA, and the data lead lines 43 of the data lines 40 and the scan lead lines 53 of the scan lines 50 may all be wired in this area. Therefore, each area of the display panel can be fully utilized, and the purpose that each device with larger size can be normally installed and used on the premise that the display panel is high in screen occupation ratio is achieved.
In some alternative embodiments, referring to fig. 1, 7-11, fig. 8 is a schematic cross-sectional view of section CC 'in fig. 7, and fig. 9 is a schematic cross-sectional view of section CC' in fig. 7. Fig. 10 is a schematic cross-sectional view of the section CC 'in fig. 7, and fig. 11 is a schematic cross-sectional view of the section CC' in fig. 7.
The display panel further includes a driving circuit including a thin film transistor 130 and a storage capacitor Cs; the storage capacitor Cs includes a first plate 141 and a second plate 142; the thin film transistor 130 includes a channel 131, a gate 132, a first pole 133, and a second pole 134; in a direction away from the substrate 20, the display panel further includes an active layer 13a, a first metal layer 13b, a second metal layer 13c, a third metal layer 13d, and a fourth metal layer 13 e; wherein, the first metal layer 13b includes the gate 132 of the thin film transistor 130 and the first plate 141 of the storage capacitor Cs; the second metal layer 13c includes a second plate 142 of the storage capacitor Cs; the third metal layer 13d includes a first pole 133 and a second pole 134 of the thin film transistor 130; the first sub data line 41 and the second sub data line 42 (not shown) are located in the third metal layer 13 d; the first sub-scanning line 51 and the second sub-scanning line 52 (not shown) are located at the first metal layer 13 b.
It will be appreciated that the display panel further comprises an anode layer at the side of the drive circuitry facing away from the substrate 20, a light emitting layer at the side of the anode layer facing away from the substrate 20, and a cathode layer at the side of the light emitting layer facing away from the substrate 20. The anode layer, the light emitting layer and the cathode layer are not shown in fig. 8 and 9. In addition, the display panel further includes insulating layers between the active layer 13a and the first metal layer 13b, and between adjacent metal layers.
In the embodiment of the invention, in the display area AA, the data lines 40 and the signal lines 10 are arranged along the first direction a. Therefore, in the display area AA, the first sub data line 41, the second sub data line 42, the first sub signal line 111, the second sub signal line 112, the second signal line 12 which is not overlapped with the first non-display area NA1, and the remaining data lines 40 are all disposed on the third metal layer 13d, so that the display panel can be formed through the same manufacturing process, which is beneficial to simplifying the manufacturing process of the display panel and reducing the cost. In addition, the scan lines 50 are arranged in the second direction b within the display area AA. Therefore, in the display area AA, the first sub-scan line 51, the second sub-scan line 52, and the remaining scan lines 50 that do not overlap the first non-display area NA1 are disposed in the first metal layer 13b, thereby avoiding their short-circuiting with the data lines 40 and the signal lines 10.
In some alternative embodiments, referring to fig. 10 and 11, the display panel further includes a first conductive line 121 on the fourth metal layer 13e, and the first conductive line 121 corresponds to the signal line 10 and is electrically connected through a via. Therefore, the resistance of the signal line 10 can be reduced, the power voltage is not easy to obviously attenuate, and the voltage drop is improved, so that the OLED display panel has more uniform display brightness.
In some alternative embodiments, in conjunction with fig. 1 and 7, and with reference to fig. 8 and 10, the data leads 43 are located in the second metal layer 13c, and/or the third metal layer 13 d; the scanning wiring 53 is located in the first metal layer 13 b; the signal leads Y are located in the fourth metal layer 13 e.
It is understood that, in fig. 8 and 9, only one data lead 43 is illustrated, and the data lead 43 is located on the third metal layer 13d, so that the first sub data line 41, the second sub data line 42, the first sub signal line 111, the second sub signal line 112, and the like can be formed through the same manufacturing process, thereby simplifying the manufacturing process of the display panel. In some alternative embodiments, the data lead may be located in the second metal layer 13c, and thus, the data lead may be made of the same material and processed in the same layer as the second plate 142 of the storage capacitor Cs, so as to simplify the process. Of course, when the number of the data leads 43 is large, a part of the data leads 43 may be disposed on the second metal layer 13c, and a part of the data leads 43 may be disposed on the third metal layer 13d, so that while a narrow frame is implemented, signal interference (such as coupling) between different data leads 43 may be reduced, and the display effect of the display panel may be improved.
Specifically, in this embodiment, the data lead 43, the scanning lead 53, and the signal lead Y are disposed on different metal films, so that short circuit between different signal lines can be avoided, and the narrow frame of the display panel can be easily implemented.
In some alternative embodiments, in conjunction with fig. 1 and 7, and with reference to fig. 9 and 11, the data leads 43 are located in the third metal layer 13d, and/or the fourth metal layer 13 e; the scanning wiring 53 is located in the first metal layer 13 b; the signal leads Y are located in the second metal layer 13 c.
In this embodiment, through setting up data lead 43, scanning lead 53, signal lead Y at the metal film layer of difference, can avoid appearing the short circuit between the different signal lines, simultaneously, be favorable to realizing display panel's narrow frame.
The first metal layer 13b and the second metal layer 13c are generally made of the same material, and are both molybdenum; the third metal layer 13d and the fourth metal layer 13e are generally made of the same material, and are titanium-aluminum-titanium. When the number of the data leads 43 is large, part of the data leads 43 can be arranged on the third metal layer 13d, and part of the data leads 43 are arranged on the fourth metal layer 13e, so that the narrow frame is realized, the signal interference between different data leads 43 is reduced, and meanwhile, the data signals are transmitted through signal lines made of the same material, thereby being beneficial to improving the voltage drop and improving the display effect.
In some alternative embodiments, referring to fig. 1, 7, 12 and 13, fig. 12 is a schematic view of a cross-sectional structure of the CC 'section in fig. 7, and fig. 13 is a schematic view of a cross-sectional structure of the CC' section in fig. 7. The display panel further comprises a first packaging area NF, the first packaging area NF surrounds the hollow part LA, and the wiring area NW surrounds the first packaging area NF; the signal lead Y is located on one side of the first packaging area NF, which is far away from the hollow part LA.
It is to be understood that like reference numerals designate like or similar structures and that no further description of the invention is deemed necessary.
Note that, in order to reflect the positional relationship between the signal lead Y and the first package region NF. Fig. 12 and 13 are simplified and do not show the data lines and the scanning lines.
Through setting up the encapsulation district, can avoid inside steam, oxygen etc. in the environment get into display panel to ensure the performance of each inside device of display panel, improve display panel's life. Meanwhile, compared with the signal lead Y disposed on one side of the first encapsulation area NF close to the hollow portion LA, the encapsulation effect of the display panel may be affected, and even the encapsulation fails, resulting in poor display. Therefore, the signal lead Y is located at a side of the first encapsulation area NF away from the hollow portion LA, so that whether cracks exist around the hollow portion LA or not can be detected according to the display condition of the sub-pixels connected with the first sub-signal line 111 by using the signal lead Y to transmit signals, the encapsulation effect of the display panel can be ensured, and the display quality can be improved.
In some alternative embodiments, referring to fig. 1, 7 and 12, the display panel further includes an upper substrate 80, and the first encapsulation region NF includes a cushion metal 60 and an encapsulation adhesive 70. The upper substrate 80 may be a cover plate to protect the display panel, or a touch panel to provide the display panel with a touch function.
In fig. 12, only the pad metal 60 and the signal lead Y are located in the second metal layer 13c (i.e., in the same layer as the second plate of the storage capacitor) as an example. The pad metal 60 may be located in the first metal layer (i.e., on the same layer as the scan line 50 located in the display area AA), or may be located in the third metal layer (i.e., on the same layer as the data line 40 located in the display area AA) or the fourth metal layer (i.e., on the same layer as the first conductive line located in the display area AA), and a person skilled in the art may set the specific film layer of the pad metal 60 according to actual situations.
The packaging adhesive 70 can be glass adhesive (frit), when the display panel is packaged, a laser sintering mode is needed, the cushion metal 60 is arranged, the cushion metal can be used for reflecting laser irradiated on the cushion metal, and the laser utilization rate is improved. Meanwhile, the pad layer metal 60 may be patterned according to the distribution of the laser energy, for example, an opening or a through hole is provided, which is not particularly limited in the present invention.
In the embodiment of the invention, the rigid display panel can be packaged by arranging the cushion layer metal 60 and the packaging adhesive 70, so that the water and oxygen invasion resistance of the rigid display panel is improved, and the service life and the display effect of the display panel are improved.
In some alternative embodiments, referring to fig. 1, 7 and 13, the display panel further includes a thin film encapsulation layer 90, and the first encapsulation region NF includes at least one first retaining wall 91, and the first retaining wall 91 surrounds the hollow portion LA.
It should be noted that fig. 13 only illustrates that the first package region NF includes two first retaining walls 91.
In an embodiment of the present invention, the thin film encapsulation layer 90 may include a plurality of organic layers and inorganic layers alternately formed, thereby improving the water and oxygen intrusion resistance of the flexible display panel. First barricade 91 sets up around fretwork portion LA, can block in the water oxygen entering display panel in the fretwork portion LA, improves display panel's life-span and display effect.
It should be noted that, in the embodiments of the display panel provided by the present invention, the technical features can be freely combined without conflict, and the present invention is not exhaustive.
An embodiment of the present invention further provides a display device, as shown in fig. 14, fig. 14 is a schematic structural diagram of the display device provided in the embodiment of the present invention, and the display device includes the display panel. Also, the optical device 100, which may be a camera or a receiver, is also included. The specific structure of the display panel has been described in detail in the above embodiments, and is not described herein again. Of course, the display device shown in fig. 14 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.
The display panel and the display device provided by the invention have the following beneficial effects that: the signal transmission of the first signal wire is realized by arranging a signal lead and connecting a first sub-signal wire and a second sub-signal wire of the same first signal wire; meanwhile, at least part of the signal leads are arranged on one side, close to the hollow portion, of the wiring area, whether cracks exist around the hollow portion or not can be detected through the display condition of the sub-pixels connected with the first signal lines, and therefore an independent crack detection line does not need to be arranged, the signal lines are simplified when real-time detection is achieved, and display quality is guaranteed.
The back display panel and the display device provided by the embodiment of the invention are described in detail above, and the principle and the embodiment of the invention are explained by applying a specific example, and the description of the embodiment is only used to help understanding the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (12)
1. A display panel, comprising:
the display device comprises a substrate, a first display area, a second display area and a display area, wherein the substrate comprises a hollow part, the first non-display area, the display area and the second non-display area; the first non-display area surrounds the hollow-out part, the display area surrounds the first non-display area, and the second non-display area surrounds the display area;
a wiring area located in the first non-display area and surrounding the hollow portion;
a plurality of signal lines arranged in a first direction, the plurality of signal lines including a plurality of first signal lines partially overlapping the first non-display area; the first signal line comprises a first sub-signal line and a second sub-signal line which are positioned at two sides of the hollow part along a second direction, the first sub-signal line and the second sub-signal line are positioned in the display area, and the first direction is crossed with the second direction;
the signal lead is positioned in the first non-display area, the signal lead is connected with a first sub-signal line and a second sub-signal line of the same first signal line, and at least part of the signal lead is positioned on one side, close to the hollow part, of the wiring area;
the signal lead is connected with the first sub-signal line and the second sub-signal line of the plurality of first signal lines;
the second non-display area comprises a first sub non-display area and a second sub non-display area which are positioned at two sides of the display area along the second direction, and the first sub non-display area is provided with a plurality of bonding pads;
the plurality of signal lines comprise a plurality of second signal lines, and the second signal lines are not overlapped with the first non-display area;
in the first sub non-display area, at least one first signal line and at least one second signal line are in short circuit through a first connecting line; in the second sub non-display area, all the first signal lines are spaced from each other and spaced from any one of the second signal lines, and at least two of the second signal lines are short-circuited through a second connecting line.
2. The display panel according to claim 1,
the signal line is a power supply voltage signal line.
3. The display panel according to claim 1,
the signal lead comprises a first sub-lead, a second sub-lead and a first sub-winding for connecting the first sub-lead and the second sub-lead, the first sub-lead and the second sub-lead are at least partially overlapped with the wiring area, and the first sub-winding is positioned on one side of the wiring area close to the hollow part;
the first sub-winding wire is wound around the hollow part in a snake shape.
4. The display panel according to claim 1,
the data line is arranged along the first direction;
the data lines passing through the wiring area comprise a first sub data line, a second sub data line and a data lead, the first sub data line and the second sub data line are located in the display area, and the data lead is located in the wiring area; and the first sub data line and the second sub data line of the same data line are connected through the corresponding data lead wires.
5. The display panel according to claim 4, further comprising:
a plurality of scanning lines arranged along the second direction;
the scanning lines passing through the wiring area comprise a first scanning sub-line, a second scanning sub-line and a scanning lead, the first scanning sub-line and the second scanning sub-line are located in the display area, and the scanning lead is located in the wiring area; the first sub-scanning line and the second sub-scanning line of the same scanning line are connected through the corresponding scanning lead.
6. The display panel according to claim 5, characterized by further comprising:
a driving circuit including a thin film transistor and a storage capacitor; the storage capacitor comprises a first polar plate and a second polar plate; the thin film transistor comprises a channel, a grid electrode, a first pole and a second pole;
the display panel further comprises an active layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer along the direction far away from the substrate; the first metal layer comprises a grid electrode of the thin film transistor and a first plate electrode of the storage capacitor; the second metal layer comprises a second plate of the storage capacitor; the third metal layer comprises a first pole and a second pole of the thin film transistor;
the first sub data line and the second sub data line are positioned on the third metal layer;
the first sub-scanning line and the second sub-scanning line are located on the first metal layer.
7. The display panel according to claim 6,
the data lead is located in the second metal layer and/or the third metal layer;
the scanning lead is positioned on the first metal layer;
the signal lead is located on the fourth metal layer.
8. The display panel according to claim 6,
the data lead is located in the third metal layer and/or the fourth metal layer;
the scanning lead is positioned on the first metal layer;
the signal lead is located on the second metal layer.
9. The display panel according to claim 1, characterized by further comprising:
a first encapsulation area surrounding the hollow portion, the wiring area surrounding the first encapsulation area;
the signal lead is positioned on one side, far away from the hollow part, of the first packaging area.
10. The display panel according to claim 9,
the first packaging area comprises cushion layer metal and packaging glue.
11. The display panel according to claim 9,
the first packaging area comprises at least one first retaining wall, and the first retaining wall surrounds the hollow-out part.
12. A display device characterized by comprising the display panel according to any one of claims 1 to 11.
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| US20230127776A1 (en) * | 2021-08-31 | 2023-04-27 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and display device |
| CN113778267B (en) * | 2021-09-13 | 2024-04-16 | 上海天马微电子有限公司 | Display panel and display device |
| WO2023226023A1 (en) * | 2022-05-27 | 2023-11-30 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
| CN115294878B (en) * | 2022-09-06 | 2024-10-15 | 武汉天马微电子有限公司上海分公司 | Display panel and display device |
| CN115802795B (en) * | 2023-01-05 | 2024-09-03 | 厦门天马显示科技有限公司 | Display panel and display device |
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| KR102572345B1 (en) * | 2018-11-15 | 2023-08-29 | 삼성디스플레이 주식회사 | Display device and inspecting method thereof |
| KR20200094873A (en) * | 2019-01-30 | 2020-08-10 | 삼성디스플레이 주식회사 | Display device |
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| WO2018121322A1 (en) * | 2016-12-27 | 2018-07-05 | 昆山工研院新型平板显示技术中心有限公司 | Flexible display device and manufacturing method therefor |
| CN109752421A (en) * | 2019-01-31 | 2019-05-14 | 厦门天马微电子有限公司 | Display panel and display device |
| CN110727373A (en) * | 2019-09-30 | 2020-01-24 | 武汉华星光电半导体显示技术有限公司 | Display device |
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