CN112582268A - Semiconductor device and forming method - Google Patents
Semiconductor device and forming method Download PDFInfo
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- CN112582268A CN112582268A CN201910940543.4A CN201910940543A CN112582268A CN 112582268 A CN112582268 A CN 112582268A CN 201910940543 A CN201910940543 A CN 201910940543A CN 112582268 A CN112582268 A CN 112582268A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The embodiment of the invention provides a semiconductor device and a forming method thereof. In the embodiment of the invention, the first epitaxial layer with lower doping concentration and the second epitaxial layer and the third epitaxial layer with higher doping concentration than the first epitaxial layer are sequentially formed. The concentration of the doped ions from the side wall of the channel region to the source and drain regions of the region of the third epitaxial layer is gradually increased, the ion diffusion rate can be controlled, and transient enhanced diffusion caused by large concentration difference is avoided. Further, the short channel effect can be suppressed, and the performance of the semiconductor device can be improved.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the continuous development of semiconductor manufacturing processes, the integration level of semiconductor devices is higher and higher, and the feature size of semiconductor devices is also gradually reduced. However, the performance of semiconductor devices is also in need of improvement.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor device and a method for forming the same, so as to improve the performance of the semiconductor device.
In a first aspect, an embodiment of the present invention provides a method for forming a semiconductor device, where the method includes:
providing a front-end device layer, wherein the front-end device layer comprises a plurality of discrete fin parts and a grid electrode structure crossing the fin parts, and the region of the fin parts, which is positioned below the grid electrode structure, is a channel region;
etching the fin parts on two sides of the grid structure by taking the grid structure as a mask so as to form a concave region on the fin parts and expose the side wall of the channel region;
and forming a source drain region in the recessed region, wherein the source drain region comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are sequentially overlapped, and the doping concentration of the doping ions of the first epitaxial layer is less than that of the doping ions of the second epitaxial layer and the third epitaxial layer.
Furthermore, the doping concentrations of the doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are sequentially increased, and the first epitaxial layer covers the side wall of the channel region and the bottom of the recessed region.
Furthermore, the doping concentration of the first epitaxial layer is E18-E19/cubic centimeter, the doping concentration of the second epitaxial layer is E20-E21/cubic centimeter, and the doping concentration of the third epitaxial layer is E21-E22/cubic centimeter.
Further, the semiconductor device is a P-type transistor, and the doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer include at least one of boron ions, gallium ions and indium ions.
Further, the semiconductor device is an N-type transistor, and the doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer include at least one of phosphorus ions or arsenic ions.
Furthermore, the semiconductor device is a P-type transistor, the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon germanium layers, and the germanium content of the first epitaxial layer, the germanium content of the second epitaxial layer and the germanium content of the third epitaxial layer are sequentially increased.
Further, the mole fraction of germanium in the first epitaxial layer is 10% -20%; the molar fraction of germanium in the second epitaxial layer is 20% -50%; the molar fraction of germanium in the third epitaxial layer is 30% -50%.
Further, the semiconductor device is an N-type transistor, the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon carbon layers, and the carbon content of the first epitaxial layer, the carbon content of the second epitaxial layer and the carbon content of the third epitaxial layer are sequentially increased.
Further, the semiconductor device is an N-type transistor, and the mole fraction of carbon in the first epitaxial layer is 10% -20%; the mole fraction of carbon in the second epitaxial layer is 20% -50%; the mole fraction of carbon in the third epitaxial layer is 30% -50%.
Further, the gate structure includes a dummy gate and an isolation layer covering a sidewall of the dummy gate, and the forming of the source and drain regions specifically includes:
thinning the isolation layer;
forming the first epitaxial layer on the bottom surface of the recessed region and the side wall of the channel region by using the dummy gate and the thinned isolation layer as masks and adopting a first epitaxial process;
forming the second epitaxial layer on the first epitaxial layer;
forming the third epitaxial layer on the second epitaxial layer.
Further, the forming of the second epitaxial layer on the first epitaxial layer is specifically;
forming a second epitaxial material layer on the first epitaxial layer by adopting a second epitaxial process;
performing ion implantation on the second epitaxial material layer by adopting a first ion implantation process;
and annealing the second epitaxial material layer to form a second epitaxial layer.
Further, the forming of the third epitaxial layer on the second epitaxial layer is specifically;
forming a third epitaxial material layer on the second epitaxial layer by adopting a third epitaxial process;
forming a side wall covering the side wall of the thinned isolation layer;
and carrying out ion implantation on the third epitaxial material layer by using the pseudo gate, the thinned isolation layer and the side wall as masks and adopting a second ion implantation process to form a third epitaxial layer.
Further, the first ion implantation process specifically includes: the implanted ions are one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions, the implantation energy is 0.5K-2K, and the doping concentration is 2E14-5E 14.
Further, the first ion implantation process specifically includes: the implanted ions comprise ions of a type opposite to the dopant ions of the source and drain regions.
Further, the thickness of the first epitaxial layer is 3-7 nm; the thickness of the second epitaxial layer is 5-17 nanometers; the upper surface of the third epitaxial layer is substantially flush with the upper surface of the fin portion.
In a second aspect, an embodiment of the present invention provides a semiconductor device, including:
the front-end device layer comprises a plurality of discrete fin parts and a grid electrode structure crossing the fin parts, the region of the fin parts, which is positioned below the grid electrode structure, is a channel region, and the fin parts on two sides of the grid electrode structure are provided with recessed regions;
and the source and drain regions are positioned in the depressed regions and comprise a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are sequentially overlapped, wherein the doping concentration of the doping ions of the first epitaxial layer is less than that of the doping ions of the second epitaxial layer and the third epitaxial layer, and the first epitaxial layer covers the side wall of the channel region and the bottom of the depressed regions.
Further, the doping concentration of the doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer is increased in sequence.
Furthermore, the semiconductor device is a P-type transistor, the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon germanium layers, and the germanium content of the first epitaxial layer, the germanium content of the second epitaxial layer and the germanium content of the third epitaxial layer are sequentially increased.
Further, the semiconductor device is an N-type transistor, the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon carbon layers, and the carbon content of the first epitaxial layer, the carbon content of the second epitaxial layer and the carbon content of the third epitaxial layer are sequentially increased.
Further, the thickness of the first epitaxial layer is 3-7 nm; the thickness of the second epitaxial layer is 5-17 nanometers; the upper surface of the third epitaxial layer is substantially flush with the upper surface of the fin portion.
In the embodiment of the invention, the first epitaxial layer with lower doping concentration and the second epitaxial layer and the third epitaxial layer with higher doping concentration than the first epitaxial layer are sequentially formed. The concentration of the doped ions from the side wall of the channel region to the source and drain regions of the region of the third epitaxial layer is gradually increased, the ion diffusion rate can be controlled, and transient enhanced diffusion caused by large concentration difference is avoided. Further, the short channel effect can be suppressed, and the performance of the semiconductor device can be improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 to 4 are schematic views of structures formed at respective steps of a method of forming a semiconductor device of a comparative example;
fig. 5 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention;
fig. 6-12 are schematic views of structures formed at various steps of a method of forming a semiconductor device according to an embodiment of the present invention;
fig. 13 is a schematic structural view of a semiconductor device of an embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout this specification the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description herein, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description herein, it is to be understood that the term "layer" is used in its broadest sense to include a film, a cap layer, or the like, and a layer may include a plurality of sub-layers.
In the description herein, it is to be understood that reference throughout the specification to conventional etching techniques known in the semiconductor manufacturing art for selectively removing polysilicon, silicon nitride, silicon dioxide, metals, photoresists, polyimides, or similar materials includes, for example, wet Chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, precleaning, spray cleaning, Chemical Mechanical Polishing (CMP), and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and reference to particular deposition techniques should not be limited to that described. In some examples, two such techniques may be interchanged. For example, stripping the photoresist may include soaking the sample in a wet chemical bath or alternatively spraying a wet chemical directly onto the sample.
The term "cross over" refers to that the dummy gate structure crosses over the fin, which means that the dummy gate structure covers part of the top surface and part of the sidewall surface of the fin, and the dummy gate structure and the fin have a crossed position relationship, and the height of the dummy gate structure is greater than that of the fin.
Semiconductor devices are electronic devices that have electrical conductivity between a good electrical conductor and an insulator, and that use the special electrical properties of semiconductor materials to perform specific functions, and can be used to generate, control, receive, convert, amplify signals, and perform energy conversion. Conventional semiconductor devices include Fin-field Effect transistors (Fin-FETs). FinFETs include different types of transistors, P-type FinFETs and N-type FinFETs.
As the gate length of a transistor is continuously reduced, Oxidation Enhanced Diffusion (OED) becomes a key factor affecting the Diffusion of boron ions and phosphorus ions, and due to the Oxidation Enhanced Diffusion effect, a Transient Enhanced Diffusion (Transient Enhanced Diffusion TED) effect is caused, and the Transient Enhanced Diffusion effect not only causes Short Channel Effects (SCE) of the transistor, but also affects the Channel mobility, junction capacitance and junction leakage current of the transistor. Short channel effects are some of the effects that occur in metal oxide field effect transistors when the conduction channel length of the transistor is reduced to the order of tens of nanometers, or even a few nanometers. These effects include mainly a decrease in threshold voltage with decreasing channel length, a decrease in drain induced barrier, carrier surface scattering, velocity saturation, ionization and hot electron effects. Therefore, a new method for forming a semiconductor device is urgently needed to suppress the transient enhanced diffusion effect in the manufacturing process of the semiconductor device, so as to effectively suppress the short channel effect and improve the performance of the semiconductor device.
Referring to fig. 1 to 4, a method of forming a comparative example semiconductor device includes the steps of:
and step S1, providing a front-end device layer. The front-end device layer comprises a plurality of discrete fin parts and a grid electrode structure crossing the fin parts, and the area, below the grid electrode structure, of the fin parts is a channel area.
And S2, etching the fin parts by taking the grid electrode structure as a mask, and etching the fin parts on two sides of the grid electrode structure so as to form a sunken region on the fin parts and expose the side wall of the channel region.
And step S3, forming source and drain regions on the fin parts on the two sides of the channel region.
Fig. 1 is a schematic diagram of a front-end device layer of a semiconductor device of a comparative example. Fig. 2 is a schematic cross-sectional view along line AA' of fig. 1. Referring to fig. 1 and 2, in step S1, a front-end device layer 1 is provided. The front-end device layer 1 comprises a plurality of discrete fins 2 and a gate structure 3 crossing the fins 2.
The gate structure 3 includes: an isolation layer 3a and a dummy gate 3 b. The dummy gate 3b comprises a gate dielectric layer, a dummy gate layer and a cap layer which are sequentially stacked.
Shallow Trench Isolation (STI) 4 is formed between adjacent fins 11.
Referring to fig. 3, in step S2, the fin 11 on both sides of the gate structure is etched using the gate structure 3 as a mask, so as to form a recess 5 on the fin 11.
Referring to fig. 4, in step S3, source and drain regions 6 are formed in the recess regions 5.
However, the semiconductor device formed by the method for forming the semiconductor device of the comparative example still has transient enhanced diffusion effect and higher leakage current.
In view of the above, embodiments of the present invention provide a method for forming a semiconductor device to improve performance of the semiconductor device. In the embodiments of the present invention, the formation of the finfet is taken as an example, and further, the method of the embodiments of the present invention may be used for forming the finfet with a 14nm process node and below the 14nm process node, for example, for forming a 7nm or 14nm finfet. Furthermore, the method of forming the fin field effect transistor according to the method of the embodiment of the present invention may also be used for forming other Semiconductor devices such as a Complementary Metal Oxide Semiconductor (CMOS), a NAND Flash Memory (NAND Flash Memory), a Static Random Access Memory (SRAM), and the like.
Fig. 5 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention. As shown in fig. 5, the method for forming a semiconductor device according to the embodiment of the present invention includes the steps of:
step S100, providing a front-end device layer, where the front-end device layer includes a plurality of discrete fin portions and a gate structure crossing the fin portions, and a region of the fin portions below the gate structure is a channel region.
And S200, with the grid electrode structure as a mask, etching the fin parts on two sides of the grid electrode structure to form a concave region on the fin parts, and exposing the side wall of the channel region.
Fig. 6 to 12 are schematic views of structures formed at respective steps of a method of forming a semiconductor device according to an embodiment of the present invention.
Fig. 6 is a perspective view of the front-end device layer. Fig. 7 is a schematic cross-sectional view of the front-end device layer along line AA'. Referring to fig. 6 and 7, in step S100, a front-end device layer 10 is provided, where the front-end device layer 10 includes a plurality of discrete fins 11 and a gate structure 12 crossing the fins 11, and a region of the fins 11 under the gate structure is a channel region C.
Specifically, the front-end device layer 10 provided in step S100 may include a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, front-end device layer 10 may also include a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-silicon-germanium (S-SiGeOI), a silicon-on-insulator-silicon-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, a compound front-end device layer, or an alloy front-end device layer. The compound front end device layer comprises silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium phosphide, the alloy front end device layer comprises SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof, the SOI substrate comprises a semiconductor layer (e.g., a silicon layer, a silicon germanium layer, a silicon carbon layer, or a germanium layer) disposed on an insulating material layer having active and passive devices therein, the insulating material layer protecting the active and passive devices disposed on the semiconductor layer. And a plurality of epitaxial interface layers or strain layers and other structures can be formed on the surface of the front-end device layer so as to improve the electrical performance of the semiconductor device.
The plurality of fins 11 are parallel or substantially parallel.
The gate structure 12 includes: an isolation layer 12a and a dummy gate 12 b. The dummy gate 12b includes a gate dielectric layer, a dummy gate layer, and a cap layer stacked in sequence.
The material of the isolation layer 12a may be silicon dioxide (SiO)2) Silicon oxynitride (SiON), silicon nitride (Si)3N4) Or silicon oxycarbide (SiOC). In the present embodiment, the material of the isolation layer 12a is silicon nitride.
In an alternative implementation, the front-end device layer 10 further includes a shallow trench isolation structure 13 therein. The shallow trench isolation structure 13 fills the bottom in the adjacent fin 11. The shallow trench isolation structures 13 are used for electrical isolation between adjacent fins 11. The shallow trench isolation structure 13 may avoid implantation of dopant ions into the front-end device layer 10 in a subsequent ion implantation process. The material of the shallow trench isolation structure 13 may be silicon dioxide (SiO)2) Silicon oxynitride (SiON) or silicon oxycarbide (SiOC). The material of the shallow trench may also be a low-K dielectric material (dielectric constant is greater than or equal to 2.5 and less than 3.9) or an ultra-low-K dielectric material (dielectric constant is less than 2.5), and in this embodiment, the material of the shallow trench isolation structure 13 is silicon dioxide.
Referring to fig. 8, in step S200, the fin portions 11 on both sides of the gate structure are etched using the gate structure 12 as a mask. To form a recess 20 on the fin 11, exposing the sidewalls of the channel region C.
The etching process can be dry etching or wet etching and the like. In this embodiment, dry etching is used to etch the fin portion 11, and the dry etching may be performed according to a selected materialThe etching gas is selected according to the material, and trifluoromethane (CHF) is selected3) Sulfur hexafluoride (SF)6) Carbon tetrafluoride (CF)4) Carbon tetrafluoride (CF)4) Oxygen (O)2) And carbon tetrafluoride (CF)4) Hydrogen (H)2) Etc. as an etching gas. In an embodiment of the present invention, CHF is used3As an etching gas, the etching pressure may be 5-300 mTorr.
Optionally, after the fin portion is etched, impurity ions on the surface of the fin portion are removed by a cleaning process. And drying the intermediate structure formed in the step after the wet cleaning process is adopted.
Referring to fig. 9 to 11, in step S300, a source-drain region 30 is formed in the recessed region 20, where the source-drain region 30 includes a first epitaxial layer 30a, a second epitaxial layer 30b, and a third epitaxial layer 30c stacked in sequence, where doping concentrations of doping ions of the first epitaxial layer 30a, the second epitaxial layer 30b, and the third epitaxial layer 30c are sequentially increased, and the first epitaxial layer 30a covers a sidewall of the channel region and a bottom of the recessed region.
Specifically, the thickness of the first epitaxial layer 30a is 3 nm to 7 nm; the thickness of the second epitaxial layer 30b is 5-17 nm; the upper surface of the third epitaxial layer 30c is substantially flush with the upper surface of the fin.
Specifically, the doping concentration of the first epitaxial layer 30a is E18-E19/cc, the doping concentration of the second epitaxial layer 30b is E20-E21/cc, and the doping concentration of the third epitaxial layer 30c is E21-E22/cc.
Further, the doping ions of the first epitaxial layer 30a, the second epitaxial layer 30b and the third epitaxial layer 30c include one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions.
In an optional implementation manner, the semiconductor device is a P-type transistor, and the first epitaxial layer 30a, the second epitaxial layer 30b, and the third epitaxial layer 30c are all silicon germanium layers, wherein the germanium content of the first epitaxial layer 30a, the second epitaxial layer 30b, and the third epitaxial layer 30c increases in sequence.
Specifically, the germanium content in the first epitaxial layer 30a is 10% -20%; the content of germanium in the second epitaxial layer 30b is 20% -50%; the germanium content in the third epitaxial layer 30c is 30% -50%.
In another optional implementation manner, the semiconductor device is an N-type transistor, and the first epitaxial layer 30a, the second epitaxial layer 30b, and the third epitaxial layer 30c are all silicon carbon layers, wherein the carbon content of the first epitaxial layer 30a, the second epitaxial layer 30b, and the third epitaxial layer 30c increases in sequence.
Specifically, the semiconductor device is an N-type transistor, and the carbon content in the first epitaxial layer 30a is 10% -20%; the carbon content in the second epitaxial layer 30b is 20% -50%; the germanium content in the third epitaxial layer 30c is 30% -50%.
In an optional implementation manner, the gate structure includes a dummy gate and an isolation layer covering a sidewall of the dummy gate, and the forming of the source and drain regions specifically includes:
and S310, thinning the isolation layer.
And S320, forming the first epitaxial layer on the bottom surface of the depressed area and the side wall of the channel area by using the dummy gate and the thinned isolation layer as masks and adopting a first epitaxial process.
Step S330, forming the second epitaxial layer on the first epitaxial layer.
Step S340, forming the third epitaxial layer on the second epitaxial layer.
Referring to fig. 9, in step S310, the isolation layer is thinned.
Specifically, the thickness of the isolation layer 12a is thinned to 4nm to 7 nm. The thickness is a dimension of the spacer layer 12a in the horizontal direction in the cross section shown in fig. 11. By thinning the isolation layer 12a, a source drain region can be formed in the recessed region 20 subsequently, and formation of a gap at the position of the side wall of the channel region due to the over-thickness of the isolation layer 12a is avoided.
Specifically, the isolation layer 12a may be thinned by an etching process. The etching process may be dry etching, and specifically may be an etching process with a high selection ratio for the fin portion 11.
In an alternative implementation, the etching gas used may be fluoromethane (CH)3F) Difluoromethane (CH)2F2) And trifluoromethane (CHF)3) And oxygen is mixed and used as an auxiliary gas in the etching gas. The flow rate of the etching gas is in the range of 20 standard milliliters per minute and the etching time is in the range of 20 seconds to 100 seconds.
Referring to fig. 9, in step S320, the dummy gate 12b and the thinned isolation layer 12a are used as masks, and a first epitaxial process is used to form the first epitaxial layer 30a on the bottom surface of the recess region and the sidewall of the channel region.
In an alternative implementation, the thickness of the first epitaxial layer 30a is 5 nanometers.
For an N-type semiconductor device, silicon (Si) may be epitaxially grown in the recess region 20. For P-type semiconductor devices, silicon germanium (SiGe) may be epitaxially grown in recessed region 20. The epitaxial growth may form raised source and drain regions in a subsequent process to facilitate the introduction of stress to the device. In-situ doping, such as phosphorus (P) or boron (B) doping, may be performed during the epitaxial growth.
An epitaxial growth process is adopted to form an epitaxial layer, so that the width of a subsequently formed source drain region is larger than that of the fin portion, the series resistance can be reduced, and the driving current is improved; meanwhile, the position of the source and drain regions can be raised, so that parasitic junction capacitance is reduced, and the performance of the semiconductor device is improved.
Specifically, the epitaxial growth process may be selected from a vapor Phase Epitaxy process (Vpor-Phase epitixy, VPE), a Liquid Phase Epitaxy process (Liquid-Phase epitixy), a Molecular Beam Epitaxy process (MBE), and an Ion Beam Epitaxy process (IBE), etc
In an alternative implementation, the first epitaxial layer 30a is epitaxially grown in an atmosphere with Si, SiGe, SiC and other precursors at a pressure of 5TORR-500 TORR. Specifically, the precursor may include SiH2Cl2(as a silicon precursor), germane (GeH)4) And methylsilane (CH 3-SiH)3) Deposition occurs in the case of (1). At the same time, the user can select the desired position,the in-situ doping can be carried out during the epitaxial growth, and boron diborane (B) can be introduced2H6) Phosphine (PH)3) And Arsine (ASH)3) And the like.
In an alternative implementation, the semiconductor device is a P-type transistor, the first epitaxial layer 30a is silicon germanium, and the proportion of germanium is 15%. The doping concentration of boron in the first epitaxial layer 30a is 5E 18/cc.
In this step, the first epitaxial layer 30a is made to have a first stress by controlling the proportion of germanium and the concentration of dopant ions in the first epitaxial layer 30 a. The silicon-germanium epitaxial layer can introduce compressive stress, so that the molecular arrangement in a channel region is tighter, and the mobility of holes is improved.
Referring to fig. 10, in step S330, the second epitaxial layer 30b is formed on the first epitaxial layer 30 a.
Specifically, forming the second epitaxial layer 30b includes the steps of:
step S331, forming a second epitaxial material layer on the first epitaxial layer by using a second epitaxial process.
Specifically, the second epitaxial process is different from the first epitaxial process in that the ratio of germanium in the reaction gas is increased and the concentration of dopant ions is increased.
Step S332, performing ion implantation on the second epitaxial layer by using a first ion implantation process.
Specifically, the implanted ions are one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions, the implantation energy is 0.5K-2K, and the doping concentration is 2E14-5E 14.
Further, ions of opposite ion type, as in-situ doped, are implanted into the second epitaxial layer 30 b. Specifically, in the P-type transistor, phosphorus ions are implanted in the second epitaxial layer 30 b; in the N-type transistor, boron ions are implanted in the second epitaxial layer 30 b.
It can be determined by simulation calculation that the smaller the dose of ion implantation, the less damage to the epitaxial layer. Therefore, a lower dose of ion implantation is performed in the second epitaxial material layer to fill the gap in the second epitaxial material layer, which may hinder the diffusion of ions. Controlling the rate of ion diffusion. Implanted ions of opposite type can further impede the diffusion of ions in the epitaxial layer. The low energy can avoid damage to the second epitaxial material layer during ion implantation.
And S333, annealing the second epitaxial material layer to form a second epitaxial layer.
Specifically, the annealing may be Rapid Thermal Annealing (RTA), and specifically may include Laser annealing (LSA), Spike Rapid Thermal annealing (Spike annealing, SA), or Flash Lamp annealing (Flash Lamp annealing, FLA).
The temperature range of the annealing may be 800 ℃ to 1200 ℃.
Annealing may relax the second epitaxial layer 30b, reducing the defect density and junction leakage current of the second epitaxial layer 30 b.
In an alternative implementation, the second epitaxial layer 30b is silicon germanium with a 30% proportion of germanium. The doping concentration of boron in the first epitaxial layer 30a is 5E 120/cc.
In this step, the ratio of germanium and the doping concentration of the dopant ions in the second epitaxial layer are both greater than those in the first epitaxial layer. The concentration of the doping ions in the region from the channel region to the second epitaxial layer is gradually increased, and transient enhanced diffusion caused by overlarge concentration difference between the doping ions in the epitaxial layer and the doping ions in the channel region can be avoided. Meanwhile, the proportion of germanium in the first epitaxial layer and the second epitaxial layer is increased in a gradient mode, and the phenomenon that the epitaxial layers are curled or broken due to overlarge stress is avoided.
Referring to fig. 11, in step S340, the third epitaxial layer 30c is formed on the second epitaxial layer 30 b.
Specifically, forming the third epitaxial layer 30c includes the steps of:
step S341, a third epitaxial material layer is formed on the second epitaxial layer 30b by using a third epitaxial process.
Specifically, the third epitaxial process is different from the second epitaxial process in that the ratio of germanium in the reaction gas is increased and the concentration of dopant ions is increased.
And step S342, forming a sidewall covering the sidewall of the thinned isolation layer.
The side walls 40 are used as masks in a subsequent ion implantation process to prevent ions from being implanted into the channel region and the dummy gate. The thickness of the sidewall 40 may be 5 nm to 20 nm.
The material of the sidewall spacer 40 may be a low-K dielectric material (the dielectric constant is greater than or equal to 2.5 and less than 3.9) or an ultra-low-K dielectric material (the dielectric constant is less than 2.5), and in this embodiment, the material of the sidewall spacer 20 is silicon dioxide.
Specifically, the sidewall 40 may be formed by a Chemical Vapor Deposition (CVD) method, such as Low Temperature Chemical Vapor Deposition (LTCVD), Plasma Chemical Vapor Deposition (PCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and Fluid Chemical Vapor Deposition (FCVD).
And S343, carrying out ion implantation on the third epitaxial material layer by adopting a second ion implantation process by taking the pseudo gate, the thinned isolation layer and the side wall as masks to form a third epitaxial layer.
Specifically, the ion implantation process comprises one or more of phosphorus ion, arsenic ion, boron ion, indium ion, gallium ion and antimony ion, the implantation angle of the ion implantation is 0-5 deg., and the implantation dosage is E14atom/cm2-5E15atom/cm2The implantation energy is 6Kev-50 Kev.
By using the dummy gate 12b, the thinned isolation layer 12a and the side walls 40 as masks, ion implantation into the channel region C and the dummy gate 12b can be avoided. Meanwhile, the region implanted with ions can be spaced from the channel region C to prevent the ions in the source/drain region 40 from diffusing into the channel region.
In this step, a first epitaxial layer having a lower doping concentration and a second epitaxial layer and a third epitaxial layer having a higher doping concentration than the first epitaxial layer are sequentially formed. The concentration of the doped ions from the side wall of the channel region to the source and drain regions of the region of the third epitaxial layer is gradually increased, the ion diffusion rate can be controlled, and transient enhanced diffusion caused by large concentration difference is avoided. Further, the short channel effect can be suppressed, and the performance of the semiconductor device can be improved.
Meanwhile, the first epitaxial layer is not subjected to ion implantation, and the energy of ion implantation of the second epitaxial layer is low, so that the number of defects formed in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer by ion implantation is gradually increased. That is, the first epitaxial layer near the channel region has few defects, and the rate of ion diffusion can be further controlled.
The proportion of the components in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer also changes gradually, for example, in a P-type transistor, the materials of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are silicon germanium, the proportion of the germanium in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer is increased gradually, and the phenomenon that the epitaxial layers are curled or broken due to overlarge stress can be avoided.
Referring to fig. 12, in the subsequent process, the method further includes: and annealing the first epitaxial layer, the second epitaxial layer and the third epitaxial layer. And forming an etching stop layer 60 covering the fin portion 11, the source drain region 30 and the side wall of the side wall 40. A dielectric layer 70 is formed on the etch stop layer 60. The dummy gate is replaced with a metal gate. And forming a conductive through hole which is in gate connection with the source drain region and the metal gate. An interconnect structure electrically connected to the conductive via. And packaging the formed semiconductor structure. To form a completed semiconductor device.
In the embodiment of the invention, the first epitaxial layer with lower doping concentration and the second epitaxial layer and the third epitaxial layer with higher doping concentration than the first epitaxial layer are sequentially formed. The concentration of the doped ions from the side wall of the channel region to the source and drain regions of the region of the third epitaxial layer is gradually increased, the ion diffusion rate can be controlled, and transient enhanced diffusion caused by large concentration difference is avoided. Further, the short channel effect can be suppressed, and the performance of the semiconductor device can be improved.
In another aspect, an embodiment of the present invention further provides a semiconductor device, where the semiconductor device includes: a front-end device layer and a source drain region.
The front-end device layer comprises a plurality of discrete fin parts and a grid electrode structure stretching across the fin parts, the area, below the grid electrode structure, of the fin parts is a channel region, and the fin parts on two sides of the grid electrode structure are provided with recessed regions.
The source-drain region is located in the depressed region and comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are sequentially overlapped, wherein the doping concentration of doping ions of the first epitaxial layer is smaller than that of the doping ions of the second epitaxial layer and the third epitaxial layer, and the first epitaxial layer covers the side wall of the channel region and the bottom of the depressed region.
Fig. 13 is a schematic structural view of a semiconductor device of an embodiment of the present invention. Referring to fig. 13, a semiconductor device according to an embodiment of the present invention includes: front-end device layer 10 'and source drain regions 30'.
The front-end device layer 10 ' comprises a plurality of discrete fins 11 ' and a gate structure 12 ' crossing the fins 11 ', wherein a region of the fins 11 ' below the gate structure 12 ' is a channel region C ', and recessed regions are formed on the fins 11 ' on two sides of the gate structure 12 '.
The plurality of fins 11' are parallel or substantially parallel.
In an alternative implementation, the front-end device layer 10 'further includes a shallow trench isolation structure 13'. The shallow trench isolation structure 13 'fills the bottom in the adjacent fin 11'. The shallow trench isolation structures 13 'are used for electrical isolation between adjacent fins 11'.
The gate structure 12' includes: an isolation layer 12a 'and a dummy gate 12 b'. The dummy gate 12 b' includes a gate dielectric layer, a dummy gate layer and a cap layer stacked in sequence.
In an alternative implementation, the sidewalls of the gate structure 12 'are covered with sidewalls 40'.
The source-drain region 30 'is located in the recessed region 20', the source-drain region 30 'includes a first epitaxial layer 30 a', a first epitaxial layer 30b 'and a third epitaxial layer 30 c' which are sequentially stacked, wherein the doping concentration of the doping ions of the first epitaxial layer 30a 'is less than the doping concentration of the doping ions of the first epitaxial layer 30 b' and the third epitaxial layer 30c ', and the first epitaxial layer 30 a' covers the side wall of the channel region and the bottom of the recessed region.
Specifically, the doping concentrations of the dopant ions of the first epitaxial layer 30a ', the first epitaxial layer 30b ', and the third epitaxial layer 30c ' are sequentially increased.
Specifically, the doping concentration of the first epitaxial layer 30a ' is E18-E19/cc, the doping concentration of the first epitaxial layer 30b ' is E20-E21/cc, and the doping concentration of the third epitaxial layer 30c ' is E21-E22/cc.
Specifically, the doping ions of the first epitaxial layer 30a ', the first epitaxial layer 30b ' and the third epitaxial layer 30c ' include one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions.
Specifically, the semiconductor device is a P-type transistor, and the first epitaxial layer 30a ', the first epitaxial layer 30 b' and the third epitaxial layer 30c 'are all silicon germanium layers, wherein the germanium content of the first epitaxial layer 30 a', the first epitaxial layer 30b 'and the third epitaxial layer 30 c' is increased in sequence.
Specifically, the germanium content in the first epitaxial layer 30 a' is 10% -20%; the germanium content in the first epitaxial layer 30 b' is 20% -50%; the germanium content in the third epitaxial layer 30 c' is 30% -50%.
Specifically, the semiconductor device is an N-type transistor, and the first epitaxial layer 30a ', the first epitaxial layer 30 b' and the third epitaxial layer 30c 'are all silicon carbon layers, wherein the carbon content of the first epitaxial layer 30 a', the first epitaxial layer 30b 'and the third epitaxial layer 30 c' is increased in sequence.
Specifically, the carbon content in the first epitaxial layer 30 a' is 10% to 20%; the carbon content in the first epitaxial layer 30 b' is 20% -50%; the germanium content in the third epitaxial layer 30 c' is 30% -50%.
Specifically, the thickness of the first epitaxial layer 30 a' is 3 nm to 7 nm; the thickness of the first epitaxial layer 30 b' is 5-17 nm; the upper surface of the third epitaxial layer 30c 'is substantially flush with the upper surface of the fin 11'.
In the embodiment of the invention, the source and drain regions comprise a first epitaxial layer, a second epitaxial layer and a third epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer and the third epitaxial layer have higher doping concentration than the first epitaxial layer. The concentration of the doped ions from the side wall of the channel region to the source and drain regions of the region of the third epitaxial layer is gradually increased, the ion diffusion rate can be controlled, and transient enhanced diffusion caused by large concentration difference is avoided. Further, the short channel effect can be suppressed, and the performance of the semiconductor device can be improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (20)
1. A method of forming a semiconductor device, the method comprising:
providing a front-end device layer, wherein the front-end device layer comprises a plurality of discrete fin parts and a grid electrode structure crossing the fin parts, and the region of the fin parts, which is positioned below the grid electrode structure, is a channel region;
etching the fin parts on two sides of the grid structure by taking the grid structure as a mask so as to form a concave region on the fin parts and expose the side wall of the channel region;
and forming a source drain region in the recessed region, wherein the source drain region comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are sequentially overlapped, and the doping concentration of the doping ions of the first epitaxial layer is less than that of the doping ions of the second epitaxial layer and the third epitaxial layer.
2. The method of claim 1, wherein doping concentrations of doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are sequentially increased, and the first epitaxial layer covers a sidewall of the channel region and a bottom of the recess region.
3. The method of claim 1, wherein the first epitaxial layer has a doping concentration of E18-E19/cc, the second epitaxial layer has a doping concentration of E20-E21/cc, and the third epitaxial layer has a doping concentration of E21-E22/cc.
4. The method of claim 1, wherein the semiconductor device is a P-type transistor, and the dopant ions of the first, second, and third epitaxial layers comprise at least one of boron, gallium, and indium ions.
5. The method of claim 1, wherein the semiconductor device is an N-type transistor, and the dopant ions of the first, second, and third epitaxial layers comprise at least one of phosphorous ions or arsenic ions.
6. The method of claim 1, wherein the semiconductor device is a P-type transistor, and the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are silicon germanium layers, wherein the germanium content of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer increases in sequence.
7. The method for forming the semiconductor device according to claim 6, wherein a mole fraction of germanium in the first epitaxial layer is 10% -20%; the molar fraction of germanium in the second epitaxial layer is 20% -50%; the molar fraction of germanium in the third epitaxial layer is 30% -50%.
8. The method according to claim 1, wherein the semiconductor device is an N-type transistor, the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are silicon-carbon layers, and the carbon content of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer increases in sequence.
9. The method for forming the semiconductor device according to claim 8, wherein the semiconductor device is an N-type transistor, and the mole fraction of carbon in the first epitaxial layer is 10% to 20%; the mole fraction of carbon in the second epitaxial layer is 20% -50%; the mole fraction of carbon in the third epitaxial layer is 30% -50%.
10. The method for forming the semiconductor device according to claim 1, wherein the gate structure includes a dummy gate and an isolation layer covering a sidewall of the dummy gate, and the forming of the source and drain regions specifically includes:
thinning the isolation layer;
forming the first epitaxial layer on the bottom surface of the recessed region and the side wall of the channel region by using the dummy gate and the thinned isolation layer as masks and adopting a first epitaxial process;
forming the second epitaxial layer on the first epitaxial layer;
forming the third epitaxial layer on the second epitaxial layer.
11. The method for forming a semiconductor device according to claim 10, wherein the forming of the second epitaxial layer on the first epitaxial layer is specifically;
forming a second epitaxial material layer on the first epitaxial layer by adopting a second epitaxial process;
performing ion implantation on the second epitaxial material layer by adopting a first ion implantation process;
and annealing the second epitaxial material layer to form a second epitaxial layer.
12. The method for forming a semiconductor device according to claim 10, wherein the forming of the third epitaxial layer on the second epitaxial layer is specifically;
forming a third epitaxial material layer on the second epitaxial layer by adopting a third epitaxial process;
forming a side wall covering the side wall of the thinned isolation layer;
and carrying out ion implantation on the third epitaxial material layer by using the pseudo gate, the thinned isolation layer and the side wall as masks and adopting a second ion implantation process to form a third epitaxial layer.
13. The method for forming the semiconductor device according to claim 11, wherein the first ion implantation process is specifically: the implanted ions are one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions, the implantation energy is 0.5K-2K, and the doping concentration is 2E14-5E 14.
14. The method for forming the semiconductor device according to claim 10, wherein the first ion implantation process is specifically: the implanted ions comprise ions of a type opposite to the dopant ions of the source and drain regions.
15. The method for forming a semiconductor device according to claim 1, wherein a thickness of the first epitaxial layer is 3 nm to 7 nm; the thickness of the second epitaxial layer is 5-17 nanometers; the upper surface of the third epitaxial layer is substantially flush with the upper surface of the fin portion.
16. A semiconductor device, characterized in that the semiconductor device comprises:
the front-end device layer comprises a plurality of discrete fin parts and a grid electrode structure crossing the fin parts, the region of the fin parts, which is positioned below the grid electrode structure, is a channel region, and the fin parts on two sides of the grid electrode structure are provided with recessed regions;
and the source and drain regions are positioned in the depressed regions and comprise a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are sequentially overlapped, wherein the doping concentration of the doping ions of the first epitaxial layer is less than that of the doping ions of the second epitaxial layer and the third epitaxial layer, and the first epitaxial layer covers the side wall of the channel region and the bottom of the depressed regions.
17. The semiconductor device according to claim 16, wherein doping concentrations of the dopant ions of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are sequentially increased.
18. The semiconductor device of claim 16, wherein the semiconductor device is a P-type transistor, and wherein the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are silicon germanium layers, wherein the germanium content of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer increases in sequence.
19. The semiconductor device according to claim 16, wherein the semiconductor device is an N-type transistor, and the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are silicon-carbon layers, wherein the carbon content of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer increases in sequence.
20. The semiconductor device of claim 16, wherein the first epitaxial layer has a thickness of 3-7 nm; the thickness of the second epitaxial layer is 5-17 nanometers; the upper surface of the third epitaxial layer is substantially flush with the upper surface of the fin portion.
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