WO2023102906A1

WO2023102906A1 - Semiconductor device and manufacturing method therefor, and terminal device

Info

Publication number: WO2023102906A1
Application number: PCT/CN2021/137144
Authority: WO
Inventors: 邓嘉男; 林军; 马旭; 还亚炜; 谭鸿哲; 徐雁玲
Original assignee: 华为技术有限公司
Priority date: 2021-12-10
Filing date: 2021-12-10
Publication date: 2023-06-15
Also published as: CN116583958A

Abstract

The present application provides a semiconductor device and a manufacturing method therefor, and an electronic device, relates to the technical field of semiconductors, and can improve the short channel effect of a transistor. The semiconductor device comprises a substrate. A channel region, a source region, and a drain region are arranged on the substrate. The source region and the drain region are located on two sides of the channel region, respectively. The substrate is a Si substrate or a SiGe substrate. The substrate is provided with grooves in both the source region and the drain region. A first epitaxial layer and a second epitaxial layer are arranged in the groove, and the second epitaxial layer is close to the bottom of the groove relative to the first epitaxial layer. The first epitaxial layer and the second epitaxial layer are both P-type doped SiGe. The component ratio of Ge in the first epitaxial layer and the concentration of the P-type doped element are fixed values. The component ratio of Ge in the second epitaxial layer and the concentration of the P-type doped element are gradually reduced in the direction away from the first epitaxial layer.

Description

Semiconductor device, manufacturing method thereof, and electronic device

technical field

The present application relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and electronic equipment.

Background technique

With the continuous shrinking of the manufacturing process of semiconductor transistors, due to the existence of short channel effects, the performance improvement of transistors has been severely challenged. Silicon germanium epitaxial technology is used to increase the channel pressure stress of PMOS (positive channel metal oxide semiconductor, P-channel metal oxide semiconductor field effect transistor) by introducing stress into the source and drain of the transistor, thereby increasing the hole mobility. Improving the short channel effect has always been the focus and hotspot of industry research.

Contents of the invention

Embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and an electronic device, which can improve the short channel effect of a transistor.

The present application provides a semiconductor device, including a substrate; a channel region, a source region, and a drain region are arranged on the substrate; the source region and the drain region are respectively located on both sides of the channel region. The substrate is a Si substrate or a SiGe substrate. The substrate is provided with grooves in both the source region and the drain region. A first epitaxial layer and a second epitaxial layer are arranged in the groove, and the second epitaxial layer is closer to the bottom of the groove than the first epitaxial layer. Both the first epitaxial layer and the second epitaxial layer use P-type doped SiGe. The composition ratio of Ge and the concentration of the P-type doping element in the first epitaxial layer are fixed values. The composition ratio of Ge in the second epitaxial layer and the concentration of the P-type dopant element gradually decrease along the direction away from the first epitaxial layer.

In the semiconductor device provided by the embodiment of the present application, the first epitaxial layer and the second epitaxial layer are arranged in the grooves located in the source region and the drain region, and both the first epitaxial layer and the second epitaxial layer are P-type doped SiGe layer. Wherein, by setting the composition ratio of Ge in the first epitaxial layer on both sides of the channel and the doping concentration of the P-type dopant element to a fixed value, it is possible to make the second epitaxial layer on both sides of the channel of the transistor at different positions in the semiconductor device The composition of the epitaxial layer is the same, thereby reducing the variation of device performance caused by the loading effect. On the other hand, by setting the second epitaxial layer below the first epitaxial layer, the composition ratio of Ge and the doping concentration of P-type dopant elements gradually decrease from top to bottom, which can make the The depletion effect of the substrate away from the channel is weakened (that is, the width of the depletion region is reduced), so that the punch through of the transistor in the on state can be reduced, the short channel effect can be improved, and the leakage induced potential can be reduced. Barrier lowering effect and device leakage.

In some possible implementation manners, when the semiconductor device adopts a planar field effect transistor, the cross-section of the sidewall of the groove is Σ-shaped.

In some possible implementation manners, when the semiconductor device adopts a fin field effect transistor, the cross section of the above groove may be U-shaped.

In some possible implementations, the upper surface of the first epitaxial layer is not lower than the opening of the groove, so that different transistors can be formed with a first epitaxial layer with a fixed composition on the side of the entire channel, reducing the Device performance changes.

In some possible implementations, the composition ratio of Ge in the first epitaxial layer is n1, and the concentration of P-type doping elements is m1; in the direction away from the first epitaxial layer, the composition of Ge in the second epitaxial layer The ratio is reduced from n1 to n2, and the concentration of the P-type dopant element is reduced from m1 to m2; wherein, n2<n1, m2<m1; in this way, the manufacturing process can be simplified.

In some possible implementations, a third epitaxial layer and a fourth epitaxial layer are also arranged in the groove; both the third epitaxial layer and the fourth epitaxial layer use P-type doped SiGe; the fourth epitaxial layer covers the Bottom; the third epitaxial layer is located between the second epitaxial layer and the fourth epitaxial layer, and the third epitaxial layer wraps the surface of the second epitaxial layer located in the groove. Among them, through the setting of the third epitaxial layer, it is possible to avoid the direct contact between the second epitaxial layer with high Ge composition and the fourth epitaxial layer with low Ge composition, so as to improve the growth quality of the second epitaxial layer and avoid the generation of the second epitaxial layer. Dislocation and stress relief. The fourth epitaxial layer prevents the P-type dopant atoms in the SiGe layer above it from diffusing into the channel and the substrate, thereby suppressing the short channel effect of the transistor and reducing parasitic capacitance and noise.

In some possible implementation manners, the composition ratio of Ge in the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer and the concentration of the P-type doping element decrease in sequence.

In some possible implementation manners, a third epitaxial layer is also arranged in the groove; the third epitaxial layer adopts P-type doped SiGe; the third epitaxial layer is filled between the groove and the second epitaxial layer, and the third epitaxial layer The epitaxial layer wraps the surface of the second epitaxial layer located in the groove. The setting of the third epitaxial layer avoids direct contact between the second epitaxial layer with high Ge composition and the fourth epitaxial layer with low Ge composition, so as to improve the growth quality of the second epitaxial layer and avoid dislocation and stress in the second epitaxial layer At the same time, the setting of the third epitaxial layer can prevent the P-type dopant atoms in the SiGe layer above it from diffusing into the channel and the substrate, thereby suppressing the short-channel effect of the transistor and reducing parasitic capacitance and noise .

In some possible implementation manners, the composition ratio of Ge in the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer and the concentration of the P-type dopant element decrease sequentially.

In some possible implementations, the composition ratio of Ge in the first epitaxial layer is 5% to 75%, and the concentration of P-type doping elements is 1E18 to 5E21/cm ³ ; the composition ratio of Ge in the second epitaxial layer is 5%-75%, and the concentration of P-type doping elements is 1E18-5E21/cm ³ .

In some possible implementation manners, the thickness of the first epitaxial layer is 1 nm˜70 nm; the thickness of the second epitaxial layer is 1 nm˜70 nm.

In some possible implementation manners, a contact cap layer is provided on the surface of the first epitaxial layer; the contact cap layer is made of Si or SiGe. In this way, the contact cap layer can react with the film layer of nickel (Ni) or titanium (Ti) used in the subsequent manufacturing process of the semiconductor device to form low-resistance NiSi or TiSi, thereby reducing the parasitic contact resistance of the device.

The embodiment of the present application also provides a method for manufacturing a semiconductor device, including: providing a substrate, and fabricating a dummy gate structure on the surface of the substrate; wherein, the substrate is a Si substrate or a SiGe substrate. Grooves are respectively formed by etching the source region and the drain region located on both sides of the dummy gate structure on the surface of the substrate. A plurality of P-type doped SiGe layers are epitaxially grown in the groove; wherein, the P-type doped SiGe layers include a second epitaxial layer and a first epitaxial layer which are epitaxially grown in sequence; Ge in the first epitaxial layer The composition ratio and the concentration of P-type doping elements are fixed values; the composition ratio of Ge in the second epitaxial layer and the concentration of P-type doping elements gradually decrease along the direction away from the first epitaxial layer.

Using the manufacturing method provided in the embodiment of the present application, the first epitaxial layer and the second epitaxial layer are epitaxially grown sequentially in the grooves located in the source region and the drain region, and both the first epitaxial layer and the second epitaxial layer are P-type doped SiGe layer. Wherein, the composition ratio of Ge and the doping concentration of P-type dopant elements in the first epitaxial layer epitaxially grown on both sides of the channel are fixed values, which can reduce device performance changes caused by loading effects. On the other hand, in the second epitaxial layer grown epitaxially under the first epitaxial layer, the composition ratio of Ge and the doping concentration of P-type doping elements gradually decrease from top to bottom, which can make the second epitaxial layer The depletion effect on the substrate away from the channel is weakened (that is, the width of the depletion region is reduced), so that the punch through of the transistor in the on state can be reduced, the short channel effect can be improved, and the leakage induced Barrier lowering effect and device leakage.

In some possible implementation manners, forming grooves by etching the source region and the drain region located on both sides of the pseudo-gate structure on the substrate surface may include: using dry etching to form grooves on the substrate surface located on both sides of the pseudo-gate structure. The source region and the drain region on the side respectively form spherical grooves; wet etching is used to further etch the spherical grooves to form Σ-shaped grooves.

In some possible implementation manners, forming grooves by etching the source region and the drain region on both sides of the dummy gate structure on the substrate surface may include: using dry etching to form grooves on the substrate surface The source region and the drain region on both sides of the structure respectively form U-shaped grooves.

In some possible implementation manners, before sequentially growing the second epitaxial layer and the first epitaxial layer in the groove, the method for manufacturing the semiconductor device may further include: sequentially epitaxially growing the fourth epitaxial layer, the first epitaxial layer at the bottom of the groove, The third epitaxial layer; wherein, the fourth epitaxial layer covers the bottom of the groove; the third epitaxial layer covers the surface of the fourth epitaxial layer and covers the sidewall of the groove; the fourth epitaxial layer, the third epitaxial layer, the second epitaxial layer layer, the composition ratio of Ge in the first epitaxial layer and the concentration of P-type doping elements increase sequentially; after the second epitaxial layer and the first epitaxial layer are epitaxially grown in the groove in sequence, the manufacturing method of the semiconductor device may also include: Si or SiGe is used to epitaxially grow a contact cap layer on the surface of the first epitaxial layer.

The embodiment of the present application also provides an electronic device, including a printed circuit board and a semiconductor device as provided in any one of the foregoing possible implementation manners; the semiconductor device is electrically connected to the printed circuit board.

Description of drawings

FIG. 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

Fig. 2 is a schematic cross-sectional view of Fig. 1 along XX' direction;

Fig. 3 is the sectional schematic diagram along YY ' direction of Fig. 1;

FIG. 4 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

Fig. 5 is a schematic cross-sectional view of Fig. 4 along XX' direction;

Fig. 6 is a schematic sectional view of Fig. 4 along the YY ' direction;

FIG. 7 is a flow chart of a manufacturing method of a semiconductor device provided in an embodiment of the present application;

FIG. 8 is a schematic diagram of a manufacturing process of a semiconductor device provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of a manufacturing process of a semiconductor device provided in an embodiment of the present application;

FIG. 10 is a schematic diagram of a manufacturing process of a semiconductor device provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly described below in conjunction with the accompanying drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, and Not all examples. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

The terms "first" and "second" in the description, embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be interpreted as indicating or implying relative importance, nor can they be interpreted as indicating or imply order. Words such as "connected" and "connected" are used to express intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, of a sequence of steps or elements. A method, system, product or device is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to the process, method, product or device. "Up", "Down", "Left", "Right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts, and they are used for description and clarification relative to , which may change accordingly according to changes in the orientation in which components are placed in the drawings.

It should be understood that in this application, "at least one (item)" means one or more, and "multiple" means two or more. "And/or" is used to describe the association relationship of associated objects, indicating that there can be three types of relationships, for example, "A and/or B" can mean: only A exists, only B exists, and A and B exist at the same time , where A and B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one item (piece) of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c ", where a, b, c can be single or multiple.

An embodiment of the present application provides an electronic device, which includes a printed circuit board (printed circuit board, PCB) and a semiconductor device connected to the printed circuit board, and the semiconductor device is provided with a transistor. The present application does not limit the arrangement form of the semiconductor device. Schematically, the semiconductor device may be a device such as a memory, a processor, or a sensor.

The present application does not limit the installation form of the above-mentioned electronic equipment. Schematically, the electronic device may be a mobile phone, a tablet computer, a notebook, a vehicle computer, a smart watch, a smart bracelet and other electronic products.

In the electronic device provided by the embodiment of the present application, the source and drain of the transistor inside the semiconductor device adopt a new type of epitaxial layered design structure, which can reduce the impact of the epitaxial load effect on the performance of the device, and at the same time improve the short-circuit of the transistor. Channel effect, reduce leakage, etc., thereby improving device performance. The transistors provided in the semiconductor device provided in the embodiments of the present application will be described in detail below.

It can be understood that, according to different channel semiconductor materials of transistors, transistors can generally be classified into P-type transistors (ie, PMOS) and N-type transistors (ie, NMOS). The following embodiments of this application are all described using PMOS as an example.

Referring to Figure 1, Figure 2 (a schematic cross-sectional view of Figure 1 along the XX' direction), and Figure 3 (a schematic cross-sectional view of Figure 1 along the YY' direction), an embodiment of the present application provides a semiconductor device, which includes a device Transistors on a substrate 10. Wherein, the substrate 10 includes a source region A1, a channel region A2, and a drain region A3, and the source region A1 and the drain region A3 are respectively located on both sides of the channel region A2; the positions of the source, the channel, and the drain of the transistor are respectively It corresponds to the source region A1, the channel region A2, and the drain region A3.

The above-mentioned substrate 10 is usually made of semiconductor material, such as silicon (Si), silicon germanium (SiGe), etc., which is not limited in this application. Schematically, in some possible implementation manners, the substrate 10 may be bulk silicon or silicon on insulator (silicon on insulator, SOI). The following embodiments are all schematically illustrated by taking a bulk silicon wafer as the substrate 10 as an example.

As shown in FIG. 2 , the substrate 10 is respectively provided with grooves T in the source region A1 and the drain region A3, and multiple SiGe layers doped with P type are epitaxially grown in the two grooves T to form the source S , Drain D. The channel C of the transistor is formed in the part of the surface layer of the substrate 10 located in the channel region A2 , that is, the channel C is formed in the surface layer part of the substrate 10 located between the source S and the drain D.

In addition, the substrate 10 is provided with a gate structure G above the channel region A2, so as to control the channel C through the gate structure G to realize the control of the transistor. Schematically, the gate structure G may include a gate, a gate dielectric layer between the gate and the substrate, a spacer layer and a hard mask layer on the sides of the gate, and the present application does not limit this.

For the aforementioned P-type doped SiGe layers (including 11 and 12 ), the P-type doping element can generally be a trivalent (group) impurity element, such as boron, gallium, and the like.

It should be noted that, for a planar field effect transistor under the 28nm process node, as shown in FIG. Shape, the cross section of the side wall of the groove is "Σ" shape, and the groove may be referred to as "Σ" type groove hereinafter. However, the present application is not limited thereto. For transistors of other process nodes and other structures, the groove T may also have other shapes; for example, for a fin field effect transistor (fin field effect transistor, FinFET), The cross-section of the above-mentioned groove T may be a "U" shape, for details, please refer to the relevant description below.

In addition, as shown in FIG. 2, in the semiconductor device provided by the embodiment of the present application, the multiple SiGe layers formed in the groove T located in the source region A1 and the drain region A3 include: a first epitaxial layer 11 and a second epitaxial layer Layer 12. Wherein, the first epitaxial layer 11 can also be referred to as a stress providing layer, and the upper surface of the first epitaxial layer 11 is not lower than the opening of the groove T, so as to ensure that the first epitaxial layer 11 in the source S and the drain D is distributed in Both sides of the channel C provide compressive stress to the channel C to increase carrier mobility in the channel C and increase the driving current of the transistor. The second epitaxial layer 12 can also be called a performance adjustment layer. The second epitaxial layer 12 is located below the first epitaxial layer 11, that is, the second epitaxial layer 12 is closer to the bottom of the groove T than the first epitaxial layer 11, so that The width of the depletion region of the substrate 10 away from the channel C is adjusted through the second epitaxial layer 12 , thereby adjusting leakage and short channel effects of the device.

It should be understood here that the composition ratio of Ge in the first epitaxial layer 11 directly determines the lattice constant of the first epitaxial layer 11 , and further determines the stress applied to the channel through the first epitaxial layer 11 .

In the embodiment of the present application, the composition ratio of Ge in the first epitaxial layer 11 and the doping concentration of P-type dopant elements (such as boron) are fixed values, that is, Ge and P-type doping in the first epitaxial layer 11 The concentration of the element is a fixed value. In this way, on both sides of the channel of transistors at different positions (and different sizes) in the semiconductor device, the composition ratio of Ge in the first epitaxial layer 11 and the concentration of the P-type doping element All consistent, thereby reducing the device performance variation (variation) caused by the loading effect (loading effect).

Of course, in order to reduce the loading effect in the semiconductor device to a greater extent, in some possible implementations, the upper surface of the first epitaxial layer 11 can be set to protrude from the opening of the groove T, so that different transistors are on the side of the entire channel Both are formed with a first epitaxial layer 11 with a fixed composition, which reduces device performance variation to a greater extent.

In the embodiment of the present application, the composition ratio of Ge in the second epitaxial layer 12 and the concentration of the P-type dopant element gradually decrease from top to bottom (that is, in a direction away from the first epitaxial layer 11 ), That is to say, the composition ratio of Ge in the second epitaxial layer 12 and the concentration of the P-type dopant element gradually decrease along the direction away from the channel C, so that the second epitaxial layer 12 can affect the substrate far away from the channel C. The depletion effect is weakened (that is, the width of the depletion region is reduced), which in turn can reduce the punch through of the transistor in the on state, improve the short channel effect, reduce the leakage-induced barrier lowering effect and the leakage of the device .

In some possible implementations, the composition ratio of Ge and the P-type doping element in the upper surface of the second epitaxial layer 12 can be set not to exceed the composition ratio of Ge and the P-type doping element in the first epitaxial layer 11 respectively. concentration.

Schematically, in some embodiments, the composition ratio of Ge and the concentration of P-type dopant elements in the upper surface of the second epitaxial layer 12 are the same as those in the first epitaxial layer 11, and along the thickness direction from top to bottom, The composition ratio of Ge decreases gradually, and the concentration of P-type doping elements decreases gradually. For example, if the composition ratio of Ge in the first epitaxial layer 11 is n1, and the concentration of the P-type doping element is m1, then the composition ratio of Ge in the second epitaxial layer 12 decreases gradually from n1 to the bottom along the thickness direction. As small as n2, the concentration of P-type doping elements gradually decreases from m1 to m2; of course, n2<n1, m2<m1.

To sum up, in the semiconductor device provided by the embodiment of the present application, a plurality of P-type doped SiGe layers (including the first epitaxial layer 11 and the second epitaxial layer 11 and the second epitaxial layer 12). Wherein, by setting the composition ratio of Ge in the first epitaxial layer 11 located on both sides of the channel C and the doping concentration of the P-type dopant element as fixed values, it is possible to make the channels of transistors at different positions in the semiconductor device two The composition of the first epitaxial layer 11 on the side is the same, thereby reducing the device performance variation caused by the loading effect. On the other hand, by setting the second epitaxial layer 12 below the first epitaxial layer 11, the composition ratio of Ge and the doping concentration of the P-type dopant element gradually decrease from top to bottom, so that the second epitaxial The depletion effect of the layer on the substrate away from the channel C is weakened (that is, the width of the depletion region is reduced), so that the punch through of the transistor in the on state can be reduced, the short channel effect can be improved, and the short channel effect can be reduced. Leakage-induced barrier lowering effect and device leakage.

On this basis, as shown in FIG. 2 , in some possible implementations, the multiple SiGe layers epitaxially grown in the groove T further include a third epitaxial layer 13 and a fourth epitaxial layer 14 .

The above-mentioned third epitaxial layer 13 can also be called a buffer layer, the third epitaxial layer 13 is located between the second epitaxial layer 12 and the fourth epitaxial layer 14, and the third epitaxial layer 13 wraps the second epitaxial layer 12 and is located in the groove T s surface. Schematically, the composition ratio of Ge in the third epitaxial layer 13 and the concentration of the P-type dopant element are between the second epitaxial layer 12 and the fourth epitaxial layer 14, that is, through the setting of the third epitaxial layer 13, it is possible to Avoid direct contact between the second epitaxial layer 12 with high Ge composition and the fourth epitaxial layer 14 with low Ge composition, so as to improve the growth quality of the second epitaxial layer 12 and avoid dislocation and stress release in the second epitaxial layer 12 .

The above-mentioned fourth epitaxial layer 14 can also be referred to as a diffusion barrier layer. The fourth epitaxial layer 14 covers the bottom of the groove T and the corners of the side walls of the groove T. The composition ratio of Ge in the fourth epitaxial layer 14 and the P-type doped The concentration of the heteroelement is lower than that of the third epitaxial layer 13, and the fourth epitaxial layer 14 blocks the diffusion of the P-type dopant atoms in the SiGe layer (11, 12, 13) above it to the channel C and the substrate 10, and then Suppress the short channel effect of transistors, reduce parasitic capacitance and noise.

In the above-mentioned third epitaxial layer 13 and fourth epitaxial layer 14, the composition ratio of Ge and the concentration of P-type doping elements may be fixed, or may gradually decrease from top to bottom along the thickness direction. There is no limitation, and it can be set according to actual needs.

In addition, in some other possible implementation manners, the above-mentioned buffer layer and diffusion barrier layer can be combined into one epitaxial layer, that is, an epitaxial layer (which can be called a third epitaxial layer) under the second epitaxial layer 12, The epitaxial layer is filled between the T groove and the second epitaxial layer 12, and the epitaxial layer wraps the surface of the second epitaxial layer 12 located in the groove T, the composition ratio of Ge in the epitaxial layer and the P-type doping element The concentration of Ge is lower than the composition ratio of Ge and the concentration of P-type doping elements in the second epitaxial layer 12, and the functions of buffer layer and diffusion barrier layer are simultaneously realized through this epitaxial layer.

It can be known from the foregoing that, in the plurality of SiGe layers epitaxially grown in the groove T, the composition ratio of Ge and the concentration of P-type doping elements gradually decrease from top to bottom. In practice, the composition ratio of Ge and the concentration of P-type doping elements in the multiple SiGe layers (11, 12, 13, 14) can be set as required.

Schematically, in some possible implementation manners, the composition ratio of Ge in the first epitaxial layer 11 may be 5%-75%, and the concentration of P-type doping elements may be 1E18-5E21/cm ³ . For example, the composition ratio of Ge in the first epitaxial layer 11 can be 55%, 60%, 65%, 70%, etc., and the concentration of P-type doping elements can be 7E19/cm ³ , 5E20/cm ³ , 7E20/cm 3 ³ , 1E21/cm ³ , 5E21/cm ³ , etc.

Schematically, in some possible implementation manners, the thickness of the first epitaxial layer 11 may be 1 nm˜70 nm. For example, in some embodiments, the thickness of the first epitaxial layer 11 may be 40 nm, 45 nm, 50 nm, 55 nm, 60 nm and so on.

Similarly, the composition ratio of Ge in the second epitaxial layer 12 can be 5%-75%, and the concentration of P-type doping elements can be 1E18-5E21/cm ³ . The thickness of the second epitaxial layer 12 may be 1 nm˜70 nm.

Similarly, the composition ratio of Ge in the third epitaxial layer 13 and the fourth epitaxial layer 14 can be 1%-40%, the concentration of the P-type doping element can be 1E16-1E19/cm ³ , the third epitaxial layer 13, The thickness of the fourth epitaxial layer 14 may be 1 nm˜70 nm.

Schematically, in some embodiments, in the first epitaxial layer 11 , the composition ratio of Ge may be 60%, the concentration of P-type doping elements may be 7E20/cm ³ , and the thickness thereof may be 40nm˜50nm. In the second epitaxial layer 12, the composition ratio of Ge gradually decreases from 60% to 50%, the concentration of P-type doping elements can gradually decrease from 7E20/cm ³ to 1E20/cm ³ , and its thickness can be 40nm-50nm. In the third epitaxial layer 13 , the composition ratio of Ge is 35%, the concentration of the P-type doping element can be 5E19/cm ³ , and the thickness can be 20nm˜30nm. In the fourth epitaxial layer 14 , the composition ratio of Ge is 25%, the concentration of P-type doping elements can be 1E19/cm ³ , and the thickness can be 20nm˜30nm.

In addition, in order to reduce the parasitic contact resistance of the semiconductor device, in some possible implementations, as shown in FIG. 2 and FIG. P-type doped silicon (Si) or silicon germanium (SiGe) can be used. In this way, the contact cap layer 20 can react with the film layer of nickel (Ni) or titanium (Ti) used in the subsequent manufacturing process of the semiconductor device to form low-resistance NiSi or TiSi, thereby reducing the parasitic contact resistance of the device.

Schematically, in some embodiments, the contact cap layer 20 may use P-type doped SiGe. Wherein, along the film thickness direction, the composition ratio of Ge and the concentration of P-type doping elements (such as boron) gradually decrease from top to bottom. Schematically, in some possible implementation manners, the composition ratio of Ge may be 0-30%, and the concentration of P-type doping elements may be 0-3E21/cm ³ . For example, in some embodiments, the composition ratio of Ge can be reduced from 30% to 0 from top to bottom, and the concentration of P-type dopant elements can be reduced from 3E21/cm ³ to 0 from top to bottom.

The foregoing embodiments are all described by taking planar field effect transistors as an example. For FinFET, refer to FIG. 4, FIG. 5 (the schematic cross-sectional view of FIG. As shown in the schematic diagram), the main difference from the aforementioned planar field effect transistor is that the cross-section of the substrate 10 in the groove T formed in the source region A1 and the drain region A3 is "U"-shaped, and in the "U"-shaped groove A plurality of SiGe layers are formed, and the arrangement of the plurality of SiGe layers is basically the same as that of the plurality of SiGe layers (11, 12, 13, 14) in the "Σ" type groove of the aforementioned planar field effect transistor; the arrangement of the FinFET can be Refer to the relevant content of the aforementioned planar field effect transistor, which will not be repeated here.

The embodiment of the present application also provides a manufacturing method of the aforementioned semiconductor device. As shown in FIG. 7, the manufacturing method may include:

Step 01, as shown in FIG. 8 , provide a substrate 10, and fabricate a dummy gate structure G' on the surface of the substrate 10; wherein, the substrate 10 is a Si substrate or a SiGe substrate.

Schematically, in some embodiments, the above step 01 may include:

Referring to (a) in FIG. 8 , a bulk silicon wafer substrate 10 is provided, and the surface of the substrate 10 can be lightly doped with N-type as required, and the doping concentration can be 1E13/cm ³ to 1E17/cm ³ ; Of course, doping may not be performed.

Then, as shown in (b) in FIG. 8 , a dummy gate, a silicon oxide layer and a silicon nitride layer on the surface of the dummy gate, and an oxide layer on the side of the dummy gate are fabricated on the surface of the substrate 10 by using the previous process; of course , a gate dielectric layer and the like are usually formed between the dummy gate and the substrate 10 .

Next, as shown in (c) of FIG. 8 , lightly doped ion implantation and halo implantation can be performed in the source region A1 and the drain region A3 . Schematically, the implantation dose ranges from 1E9/cm ³ to 1E13/cm ³ , the implantation energy ranges from 1eV to 100keV; the implantation source species is one or more of B, BF ₂ , As, P, C, Ge, etc. species; the ion activated annealing temperature can generally be between 900° C. and 1200° C., and the time can be between 1 microsecond and 1000 seconds.

Next, as shown in (d) and (e) in FIG. The layer M1 is etched, and only the hard mask layer M1 located on the sidewall of the dummy gate structure G′ remains. Wherein, the hard mask layer M1 can use at least one material among SiN, SiON, and _SiO2 , and the lateral thickness of the hard mask layer M1 can be between 2nm and 20nm; the temperature range for depositing the hard mask layer M1 can be 100 between °C and 800 °C; the hard mask layer M1 may be etched by reactive ion etching (RIE).

Step 02, as shown in FIG. 9 or FIG. 10 , grooves T are respectively formed by etching the source region A1 and the drain region A3 located on both sides of the dummy gate structure G' on the surface of the substrate 10 .

For planar field effect transistors, in some possible implementations, the above step 02 may include: referring to FIG. The source region A1 and the drain region A3 respectively form a spherical groove T'; then, referring to Figure 9 (b), the spherical groove T' is further etched by wet etching to form a "Σ" groove T .

Schematically, in some embodiments, the source region A1 and the drain region A3 of the substrate 10 can be dry-etched using the mask of the hard mask layer M1 to form a spherical groove T'; the etching gas can be One or more of HBr, CF ₄ , O ₂ , C ₄ F ₈ and other gases. Then, wet etching is performed on the source region A1 and the drain region A3 by using the mask of the hard mask layer M1 again, and the etching solution may be one of liquids such as TMAH (tetramethylammonium hydroxide, tetramethylammonium hydroxide), ammonia water, etc. one or more species. Since the corrosion rate of the slope (or 111 crystal plane) in the spherical groove T' is the slowest, the sidewall morphology of the etched groove becomes "Σ" type, that is, "Σ" type is formed Groove T.

For the use of FinFETs in semiconductor devices, in some possible implementations, as shown in FIG. 10 , the above step 02 may include: dry etching the source regions on both sides of the pseudo-gate structure G' on the surface of the substrate 10 A1 and the drain region A3 respectively form a "U"-shaped groove T. Schematically, the etching gas may be one or more of HBr, CF ₄ , O ₂ , C ₄ F ₈ and other gases.

Step 03, as shown in FIG. 2 or FIG. 5 , epitaxially grow multiple P-type doped SiGe layers in the groove T; wherein, the P-type doped multiple SiGe layers include a second epitaxial layer that is epitaxially grown in sequence 12. The first epitaxial layer 11; the composition ratio of Ge and the concentration of P-type doping elements in the first epitaxial layer are fixed values; the composition ratio of Ge and the concentration of P-type doping elements in the second epitaxial layer 12 are gradually decreases along the direction away from the first epitaxial layer 11.

Using the manufacturing method provided in the embodiment of the present application, by sequentially epitaxially growing the first epitaxial layer 11 and the second epitaxial layer 12 in the groove T located in the source region A1 and the drain region A3, the first epitaxial layer 11 and the second epitaxial layer 12 are P-type doped SiGe layer. Wherein, the composition ratio of Ge and the doping concentration of P-type doping elements in the first epitaxial layer 11 epitaxially grown on both sides of the channel C are fixed values, which can reduce the device performance caused by the loading effect. Variety. On the other hand, in the second epitaxial layer 12 epitaxially grown under the first epitaxial layer 11, the composition ratio of Ge and the doping concentration of P-type doping elements gradually decrease from top to bottom, which can make the second epitaxial layer 12 The depletion effect of the epitaxial layer 12 on the substrate away from the channel C is weakened (that is, the width of the depletion region is reduced), so that the punch through of the transistor in the on state can be reduced, and the short channel effect can be improved. Reduce the leakage-induced barrier lowering effect and device leakage.

In addition, as shown in FIG. 2 or FIG. 5 , before epitaxially growing the aforementioned second epitaxial layer 12 , the manufacturing method may further include: sequentially epitaxially growing a fourth epitaxial layer 14 and a third epitaxial layer 13 at the bottom of the groove T. Wherein, the fourth epitaxial layer 14 covers the bottom of the groove T; the third epitaxial layer 13 covers the surface of the fourth epitaxial layer 14 and covers the sidewall of the groove T; the fourth epitaxial layer 14, the third epitaxial layer 13, the The composition ratio of Ge in the second epitaxial layer 12 and the first epitaxial layer 11 and the concentration of P-type doping elements increase sequentially.

After the aforementioned first epitaxial layer 11 is epitaxially grown, the manufacturing method may further include: epitaxially growing a contact cap layer 20 on the surface of the first epitaxial layer 11 by using Si or SiGe.

Schematically, in some embodiments, the fourth epitaxial layer 14, the third epitaxial layer 13, the second epitaxial layer 12, and the first epitaxial layer 11 are epitaxially grown sequentially in the groove T through step 03; The surface growth of layer 11 is in contact with capping layer 20 . Wherein, the fourth epitaxial layer 14 , the third epitaxial layer 13 , the second epitaxial layer 12 , the first epitaxial layer 11 , and the contact cap layer 20 all use P-type doped SiGe. In the first epitaxial layer 11 , the composition ratio of Ge can be 60%, the concentration of P-type doping elements can be 7E20/cm ³ , and the thickness can be 40nm˜50nm. In the second epitaxial layer 12, the composition ratio of Ge gradually decreases from 60% to 50% (from top to bottom), and the concentration of P-type doping elements can gradually drop from 7E20/cm ³ to 1E20/cm ³ (from top to bottom). to the bottom), its thickness can be 40nm ~ 50nm. In the third epitaxial layer 13 , the composition ratio of Ge is 35%, the concentration of the P-type doping element can be 5E19/cm ³ , and the thickness can be 20nm˜30nm. In the fourth epitaxial layer 14 , the composition ratio of Ge is 25%, the concentration of P-type doping elements can be 1E19/cm ³ , and the thickness can be 20nm˜30nm. In the contact cap layer 20, the composition ratio of Ge is reduced from 30% to 0 (from top to bottom), and the concentration of P-type doping elements can be ^gradually reduced from 3E21/cm to 0 (from top to bottom), and its thickness It may be 40 nm to 50 nm. Wherein, the epitaxial growth temperature of each epitaxial layer (11, 12, 13, 14, 20) is between 300°C and 1100°C, the pressure is between 0.1Torr and 1000Torr, and the H ₂ /SiH ₄ /DCS/B ₂ H ₆ The flow rate of /GeH ₄ gas is between 1 sccm and 50000 sccm.

For other related content in the manufacturing method of the above-mentioned semiconductor device, reference may be made to the corresponding part in the above-mentioned semiconductor device, which will not be repeated here.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A semiconductor device, characterized in that it includes a substrate;

A channel region, a source region, and a drain region are arranged on the substrate; the source region and the drain region are respectively located on both sides of the channel region;

The substrate is a Si substrate or a SiGe substrate;

The substrate is provided with grooves in both the source region and the drain region;

A first epitaxial layer and a second epitaxial layer are disposed in the groove, and the second epitaxial layer is closer to the groove bottom of the groove than the first epitaxial layer;

Both the first epitaxial layer and the second epitaxial layer use P-type doped SiGe;

The composition ratio of Ge in the first epitaxial layer and the concentration of P-type doping elements are fixed values;

The composition ratio of Ge and the concentration of P-type doping elements in the second epitaxial layer gradually decrease along the direction away from the first epitaxial layer.
The semiconductor device according to claim 1, wherein,

The cross section of the groove is U-shaped;

Alternatively, the cross section of the side wall of the groove is Σ-shaped.
The semiconductor device according to claim 1 or 2, wherein the upper surface of the first epitaxial layer is not lower than the opening of the groove.
The semiconductor device according to any one of claims 1-3, characterized in that,

The composition ratio of Ge in the first epitaxial layer is n1, and the concentration of P-type doping elements is m1;

Along the direction away from the first epitaxial layer, the composition ratio of Ge in the second epitaxial layer decreases from n1 to n2, and the concentration of P-type doping elements decreases from m1 to m2; wherein, n2< n1, m2<m1.
The semiconductor device according to any one of claims 1-4, characterized in that,

A third epitaxial layer and a fourth epitaxial layer are also arranged in the groove; both the third epitaxial layer and the fourth epitaxial layer are P-type doped SiGe;

the fourth epitaxial layer covers the bottom of the groove;

The third epitaxial layer is located between the second epitaxial layer and the fourth epitaxial layer, and the third epitaxial layer wraps the surface of the second epitaxial layer located in the groove.
The semiconductor device according to claim 5, wherein,

The composition ratio of Ge and the concentration of P-type doping elements in the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer decrease sequentially.
The semiconductor device according to any one of claims 1-4, characterized in that,

A third epitaxial layer is also arranged in the groove; the third epitaxial layer adopts P-type doped SiGe;

The third epitaxial layer is filled between the groove and the second epitaxial layer, and the third epitaxial layer wraps the surface of the second epitaxial layer in the groove.
The semiconductor device according to claim 7, wherein,

The composition ratio of Ge and the concentration of P-type doping elements in the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer decrease sequentially.
The semiconductor device according to any one of claims 1-8, characterized in that,

The composition ratio of Ge in the first epitaxial layer is 5%-75%, and the concentration of P-type doping elements is 1E18-5E21/cm 3 ;

The composition ratio of Ge in the second epitaxial layer is 5%-75%, and the concentration of P-type doping elements is 1E18-5E21/cm 3 .
The semiconductor device according to any one of claims 1-9, characterized in that,

The thickness of the first epitaxial layer is 1 nm to 70 nm;

The thickness of the second epitaxial layer is 1nm-70nm.
The semiconductor device according to any one of claims 1-10, characterized in that,

A contact cap layer is provided on the surface of the first epitaxial layer;

The contact cap layer adopts Si or SiGe.
A method for manufacturing a semiconductor device, comprising:

providing a substrate, and fabricating a pseudo-gate structure on the surface of the substrate; wherein the substrate is a Si substrate or a SiGe substrate;

Forming grooves respectively by etching source regions and drain regions located on both sides of the dummy gate structure on the surface of the substrate;

Multiple P-type doped SiGe layers are epitaxially grown in the groove; wherein, the P-type doped multiple SiGe layers include a second epitaxial layer and a first epitaxial layer that are epitaxially grown in sequence; the first epitaxial layer The composition ratio of Ge in an epitaxial layer and the concentration of P-type doping elements are fixed values; the composition ratio of Ge in the second epitaxial layer and the concentration of P-type doping elements are farther away from the first epitaxial layer gradually decreases in the direction of .
The manufacturing method of a semiconductor device according to claim 12, wherein,

The forming grooves by etching the source region and the drain region on the substrate surface on both sides of the dummy gate structure respectively includes:

using dry etching to form spherical grooves in the source region and the drain region located on both sides of the dummy gate structure on the surface of the substrate;

The spherical groove is further etched by wet etching to form a Σ-shaped groove.
The manufacturing method of a semiconductor device according to claim 12, wherein,

The forming grooves by etching the source region and the drain region on the substrate surface on both sides of the dummy gate structure respectively includes:

U-shaped grooves are respectively formed on the source region and the drain region located on both sides of the dummy gate structure on the surface of the substrate by dry etching.
The manufacturing method of a semiconductor device according to claim 12, wherein,

Before the sequential epitaxial growth of the second epitaxial layer and the first epitaxial layer in the groove, the manufacturing method further includes:

A fourth epitaxial layer and a third epitaxial layer are epitaxially grown in sequence at the bottom of the groove; wherein, the fourth epitaxial layer covers the bottom of the groove; the third epitaxial layer covers the surface of the fourth epitaxial layer, and covers The sidewall of the groove; the composition ratio of Ge in the fourth epitaxial layer, the third epitaxial layer, the second epitaxial layer, and the first epitaxial layer and the concentration of P-type doping elements in sequence Increase;

After the epitaxial growth of the second epitaxial layer and the first epitaxial layer in the groove in sequence, the manufacturing method further includes:

Si or SiGe is used to epitaxially grow a contact cap layer on the surface of the first epitaxial layer.
An electronic device, characterized by comprising a printed circuit board and the semiconductor device according to any one of claims 1-11; the semiconductor device is electrically connected to the printed circuit board.