CN112579178B - Debugging system for boot program, and host and method thereof - Google Patents
Debugging system for boot program, and host and method thereof Download PDFInfo
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- CN112579178B CN112579178B CN201910933568.1A CN201910933568A CN112579178B CN 112579178 B CN112579178 B CN 112579178B CN 201910933568 A CN201910933568 A CN 201910933568A CN 112579178 B CN112579178 B CN 112579178B
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
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Abstract
The invention provides a debugging system of a boot program, which comprises a host and a display. The host computer comprises a display information output end electrically connected with the display, a switcher and a programmable logic unit. The switch is electrically connected between the display information output end and the programmable logic unit. The programmable logic unit generates an updated operation record text file according to a power-on process. When the programmable logic unit controls the switcher to enter a debugging mode, the switcher outputs the updating operation record text file transmitted by the programmable logic unit to the display information output end. The display receives the update job record text file from the display information output terminal and displays the update job record text file.
Description
[ technical field ] A method for producing a semiconductor device
The present invention relates to a system for debugging programs, and more particularly, to a system for debugging a boot program, a host and a method thereof, which can perform debugging without connecting to other external hardware devices.
[ background of the invention ]
Referring to fig. 1, in the prior art, during the booting process of a host, a Complex Programmable Logic Device (CPLD) 111 of a host 11 executes a Power supply startup control procedure according to a predetermined Power sequence (generally called Power sequence) to manage the startup timing of a plurality of Power supply elements in a Power module of the host, however, if the CPLD 111 executes the Power supply startup control procedure, a Finite-state machine (FSM) in the CPLD 111 is not executed normally due to an abnormal behavior of any one of the plurality of Power supply elements, then a debugging process is required to be performed on the Power supply startup control procedure.
In the conventional debugging method, an additional dedicated host function test Board (BFT Board)12 is usually connected to the host 12, and the host function test Board 12 includes another CPLD 111 and a connection unit 121 to connect the host 11 and an additional monitoring device 13, such as a personal computer, respectively, for debugging and repairing, which not only needs to connect the host function test Board 12 to the host 13 and the monitoring device 13, but also causes inconvenience due to the space occupied by the additional hardware devices.
[ summary of the invention ]
The present invention is directed to a system and method for debugging a boot program without requiring additional hardware devices.
In order to solve the above technical problem, a boot program debugging method is executed by a boot program debugging system, the boot program debugging system comprising a host including a programmable logic unit, a baseboard management controller, a switch electrically connected to the programmable logic unit and the baseboard management controller, respectively, and a display information output terminal electrically connected to the switch, the boot program debugging method comprising the steps of:
(A) the programmable logic unit receives a startup power sequence code, executes a power starting process according to the startup power sequence code, and judges whether the power starting process is normally executed;
(B) when the programmable logic unit judges that the power supply starting process is abnormal, the switcher is controlled to operate in a debugging mode, and in the debugging mode, the switcher is controlled to enable the programmable logic unit to be electrically connected with the display information output end;
(C) the programmable logic unit generates a detection signal value for indicating one of a plurality of state machine codes corresponding to a currently ongoing stage and one of the state machine codes corresponding to the currently ongoing stage in the power starting process according to the power starting process;
(D) the programmable logic unit converts at least one of the one state machine code corresponding to the current on-going stage and the detection signal value corresponding to the one state machine code into character information in a text file format to generate at least one variable character information;
(E) the programmable logic unit prestores a constant operation record character file information, and writes the at least one variable character information into a corresponding variable character field in the constant operation record character file to obtain display information of an updated operation record character file;
(F) the programmable logic unit transmits a debugging display signal corresponding to the updated operation record text file to the switcher for outputting through the display information output end.
Another technical problem to be solved by the present invention is to provide a boot debugging system for executing the boot debugging method. The debugging system of the boot program comprises a host and a display. The host computer comprises a display information output end, a switcher, a substrate management controller and a programmable logic unit. The switch comprises a first switch input end, a second switch input end and a switch electrically connected with the display information output end, and the switch is controlled to select one of the first switch input end and the second switch input end to be electrically connected with the display information output end. The substrate management controller is electrically connected with the second switching input end of the switcher, the programmable logic unit is electrically connected with the first switching input end of the switcher, prestores constant operation record character file information, receives a starting power sequence code, executes a power starting process according to the starting power sequence code and generates variable character information. The programmable logic unit writes the variable character information into a corresponding variable character field in the constant operation record character file information to obtain and transmit display information of an updated operation record character file, and when the programmable logic unit judges that the power supply starting process is not normally executed, the programmable logic unit controls the switcher to enter a debugging mode so that the switcher is controlled to be electrically connected with the first switching input end and the display information output end to output a debugging display signal which is transmitted by the programmable logic unit and is related to the display information of the updated operation record character file through the display information output end. The display is electrically connected with the display information output end of the switcher, and when the switcher enters a debugging mode, the display receives a debugging display signal of display information related to the updating operation record character file from the display information output end and displays the updating operation record character file.
Compared with the prior art, the debugging system of the boot program, the host and the method thereof generate the display information of the updating operation record character file by receiving the boot power supply sequence code through the programmable logic unit of the host and controlling the switcher to electrically connect the first switching input end and the display information input end, lighten the display and enable the display to display the updating operation record character file, thereby achieving the purposes of needing no additional external hardware, knowing the relevant information of the error of the power supply starting process by only looking up the updating operation record character file, effectively improving the debugging efficiency, reducing the hardware cost required for debugging and really achieving the purposes of the debugging system.
[ description of the drawings ]
FIG. 1 is a block diagram illustrating a conventional debugging system for a boot process.
FIG. 2 is a block diagram illustrating a preferred embodiment of the debug system of the present invention.
FIG. 3 is a flowchart illustrating a self-debugging process of the debugging method of the boot program according to the present invention.
[ detailed description ] embodiments
Referring to fig. 2, a preferred embodiment of the debugging system of the boot program of the present invention comprises a host 2 and a monitor 3 electrically connected to the host 2, wherein the monitor 3 has a display information input terminal for connecting to the host 2, the host 2 can be a server host or a host of a personal computer, and the monitor 3 can be a screen of a personal computer or a screen of a notebook computer, but not limited thereto, in this embodiment, the host 2 is a server host, and the monitor 3 is a screen of a personal computer.
The host 2 includes a display information output terminal for connecting with a display 3, a switch 21 having a first switch input terminal, a second switch input terminal, and a switch output terminal electrically connected to the display information output terminal, a programmable logic unit 22 electrically connected to the first switch input terminal of the switch, and a Baseboard Management Controller (BMC) 23 electrically connected to the second switch input terminal of the switch, the display information input terminal of the display 3 is electrically connected to the switch output terminal of the switch 21 via the display information output terminal, the switch 21 can be a two-in one-out multiplexer (multiplexer) or a two-out Jumper (Jumper), the programmable logic unit 22 can be a programmable logic gate array (FPGA), or a Complex programmable logic device (Complex programmable logic device, CPLD), but not limited to this, in the embodiment, the switch 21 is an alternative jumper, and the programmable logic unit 22 is a complex programmable logic device.
The programmable logic unit 22 is programmed to have a power sequence processor 221 and a display information processing module 222 electrically connected to the power sequence processor 221.
The power sequence processor 221 receives and processes the plurality of externally inputted boot sequence codes in sequence, to start a finite-state machine (FSM) corresponding to the boot-up sequence codes to execute a power-on procedure, and outputs a plurality of state machine codes associated with the finite state machines and at least one detection signal value corresponding to each state machine code, wherein the finite state machines respectively correspond to a state task group, the state task group includes at least one state task, and each state task corresponds to the detection signal value, the boot sequence codes respectively indicate one of power-on stages in a power-on sequence executed according to a power-on sequence, and each boot sequence code is composed of a plurality of power transformation elements, in which the power transformation elements are sequentially arranged according to a boot state signal. When one of the finite state machines associated with the power-up process is not normally executed and stops executing one of the status tasks corresponding to one of the detection signal values in the status task group corresponding to the finite state machine corresponding to the received boot sequence code, which causes a system crash and cannot then start executing a Basic input/output system (BIOS) program to perform a power-up self-test process, the programmable logic unit 22 controls the operation mode of the switch 21 to switch from a predetermined normal use mode to a debug mode according to the non-normally executed finite state machine, wherein in the debug mode, the switch 21 electrically connects the first switch input terminal to the switch output terminal and does not conduct the second switch input terminal and the switch output terminal, and in the normal use mode, the switch 21 electrically connects the second switch input terminal to the switch output terminal and does not conduct the first switch input terminal and the switch output terminal, and in detail, in the normal use mode, the switch 21 connects a second switch input terminal connected to the bmc 23 and the switch output terminal connected to the display information output terminal, so as to transmit a normal display signal outputted from the baseboard management controller 23 to the display information output terminal via the switch 21, further output by the display information output terminal, when the display 3 is electrically connected with the display information output terminal through the display information input terminal, the normal state display signal outputted by the display information output terminal is transmitted to the display through the display information input terminal, and the display 3 displays an image according to the received normal state display signal; in the debug mode, the switch 21 connects the first switch input terminal connected to the programmable logic unit 22 and the switch output terminal connected to the display information output terminal, so as to transmit a debug display signal output by the programmable logic unit 22 to the display information output terminal through the switch 21, and further output through the display information output terminal, at this time, when the display 3 is electrically connected to the display information output terminal through the display information input terminal, the debug display signal output through the display information output terminal is transmitted to the display 3 through the display information input terminal, and the display 3 displays an image according to the received debug display signal; that is, when the operation mode of the switch 21 is the normal operation mode, the display signal output terminal for connecting the monitor 3 outputs the normal display signal outputted by the bmc 23, and when the operation mode of the switch 21 is the debug mode, the display signal output terminal outputs the debug display signal outputted by the programmable logic unit 22.
The display information processing module 222 has a variable information updater 225, a constant information generator 226 electrically connected to the variable information updater 225, and a display information output 227 electrically connected to the constant information generator 226, wherein the variable information updater 225 is electrically connected to the power sequence processor 221 to receive and temporarily store the plurality of state machine codes respectively corresponding to the finite state machines and the at least one detection signal value corresponding to each state machine code according to the start sequence of the finite state machines. In addition, the variable information updater 225 receives hardware signal values from server internal hardware (e.g., BMC, PCH, other circuits on the motherboard, etc.) from hardware components that operate in association with the power up process, such as a reset-related signal (BMC _ SRST _ N) of the BMC 23, a fast-storage-related signal (RST _ RSMRST _ N, RST _ BMC _ EXTRST _ N), and a power-output-stable-related signal (PGD _ PCH _ DSW _ PWROK _ R).
In particular, the order of the boot power sequence codes transmitted by the Central Processing Units (CPUs) of the same manufacturer and version is generally fixed.
The variable information updater 225 has a variable storage element 228 storing a character information look-up table, and looks up the character information look-up table in order (i.e. in accordance with the control state sequence of the finite state machine) according to the plurality of state machine codes, the receiving sequence of the at least one detection signal value corresponding to each state machine code, and the plurality of hardware signal values, to obtain a variable character information, each variable character information including character information of a state machine code in a text file format obtained by table lookup conversion of a state machine code and its filling address information, character information of a detection signal value in a text file format obtained by table lookup conversion of the detection signal value and its filling address information, and character information of a hardware signal value obtained by table lookup conversion of the plurality of hardware signal values and its filling address information. Wherein each filling address information includes a display start coordinate and a display resolution. Here, further, as for the hardware signal value, the variable information updater 225 performs conversion only when the hardware signal value which is to appear when the operation is normal is received, and EX:
the (PGD _ PCH _ DSW _ PWROK _ R) signal line is preset to pass the LOW logic to CPLD, which is asserted as the hardware signal value (PGD _ PCH _ DSW _ PWROK _ R) is received when the HIGH signal is asserted to the programmable logic unit 22 during normal operation. For the detection signal value, the detection signal corresponding to each finite state machine code may be normal (pass) or abnormal (fail), so the power-on program displays pass (P) or fail (F).
It is worth mentioning that the character information look-up table is pre-stored in the variable storage device 228 according to the boot power sequence codes. In other words, the character information look-up table pre-established according to the fixed boot power serial codes has a fixed plurality of variable character information recorded therein.
The constant information generator 226 has a constant storage device 229 for pre-storing a constant job record text file information, and the constant information generator 226 sequentially receives the character information of the state machine code, the character information of the detection signal value, and the character information of the hardware signal value from the variable information updater 225 and fills the corresponding variable character fields thereof according to the corresponding filling address information, respectively, to obtain and transmit display information of an update job record text file, regardless of whether the operation mode of the switch 21 is the normal use mode or the debug mode.
The display information output device 227 receives the display information of the updated job record text file from the constant information generator 226 and converts the display information into a debug display signal conforming to the input format of the display 3, in which the input format of the display 3 is Video Graphics Array (VGA), so as to output the debug display signal corresponding to the display information of the updated job record text file to the first switch input of the switch.
It should be noted that the Normal display signal includes a Normal display color information (not shown), a Normal vertical synchronization signal (Normal Vsync) (not shown), and a Normal horizontal synchronization signal (Normal Hsync) (not shown), the debug display signal includes a display color information (not shown), a vertical synchronization signal (Vsync) (not shown), and a horizontal synchronization signal (Hsync) (not shown), after the displays 3 are electrically connected to the host, the display color information, which includes three primary colors (RGB) image information, is received through the display information output terminal of the host to display the updated operation recording text file, or displaying the updated operation record character file by using the color matched with any two of the three primary colors, or displaying the updated operation record character file by using any one color of the three primary colors, the high voltage level of the vertical synchronization signal and the horizontal synchronization signal is 5 volts (V). In this embodiment, the display 3 displays the update log text file in a single color, that is, the display color information in the debug display signal output by the display information output device 227 only includes image information of a single color and does not include image information of other two colors, but not limited thereto.
To further illustrate how the present invention is implemented by a debug system, the following description will be presented in terms of a flowchart showing various steps.
Referring to fig. 3, the system for debugging a boot program executes a self-debugging process of the present invention, which has a step 501 to a step ten 510, and the step 501 is entered after the self-debugging process is started.
In step one 501, the programmable logic unit 22 sequentially receives a plurality of bit codes corresponding to the boot power sequence codes, and then proceeds to step two 502.
In step two 501, the power supply sequence processor 221 receives and triggers and starts the corresponding finite state machine according to the received boot power supply sequence codes, and then executes the corresponding state task set, and at the same time, starts to count up from 0 by one of a predetermined time or a countdown, and records each bit, each state machine code, and the detection signal value corresponding to each state machine code related to the boot power supply sequence code in sequence, and then enters step three 503.
In step three 503, the variable information updater 225 sequentially receives and records the hardware signal value information, and then proceeds to step four 504.
In step four 504, the power sequencer processor 221 determines whether the fsm has completed its normal execution of the plurality of status task groups, as further described below: firstly, the execution process is normal, when the power supply sequence processor 221 determines that the state task group corresponding to the finite state machine has been completed within the predetermined time, it determines whether the power supply sequence code corresponding to the currently executed finite state machine is the last one, if not, it continues to receive the next power supply sequence code, if it is the last one, a central processing unit CPU (not shown) takes over to start executing a Basic input/output system (BIOS) program for performing a power-on self-test process; when the power supply sequence processor 221 receives one of the boot power supply sequence codes and starts the corresponding finite state machine, and determines that the finite state machine does not complete the plurality of state task groups included in the finite state machine within the corresponding predetermined time, it is determined that the finite state machine does not complete the normal execution, and then the process goes to step five 505.
In step five 505, the programmable logic unit 22 enters the debug mode, and the switch 21 is controlled by the programmable logic unit 22 to be switched, then the display signal output terminal outputs the debug display signal outputted by the programmable logic unit 22, and then step six 506 is entered.
In step six 506, the variable information updater 225 receives each state machine code corresponding to the power-on sequence code from the power sequence processor and the detection signal value corresponding to each state machine code information in sequence, and performs table lookup on the character information comparison table according to the hardware signal value, the state machine code and the detection signal value corresponding to the state machine code to obtain a corresponding variable character information, wherein the variable character information includes character information of the hardware signal value, filling address information corresponding to the hardware signal value, character information of the state machine code, filling address information corresponding to the character information of the state machine code, character information of the detection signal value and filling address information corresponding to the character information of the detection signal value, and then proceeds to step seven 507.
In step seven 507, the variable information updater 225 sequentially sends the variable character information to the constant information generator 226, and then proceeds to step eight 508.
In step eight 508, the constant information generator 226 pre-stores a constant job record text file (con _ log _ file.txt) information, in this embodiment, the constant job record text file information records a fixed output and a plurality of signal display information related to power on are arranged according to a fixed format and position, including a header preceding stage, a signal name display line, a status display line, a detection value display line, a correct detection value (correct value character information) display line, and a pin code (pin name character information) display line, but not limited thereto, the constant job record text file information may also record other information beneficial to debugging. At least one of the variable character information (in this embodiment, at least one of the hardware signal value/the state machine code value/the detection signal value) is sequentially written into the corresponding variable character field of the constant job record file information to obtain display information of an updated job record file. Then step nine 509 is entered.
In step nine 509, the constant information generator 226 sequentially outputs the display information related to the update job record text file to the display information outputter 227 through serial output, so that the display information outputter 227 generates the debug display signal according to the display information of the update job record text file, wherein the debug display signal includes each character information in the display information of the update job record text file and each filling address information corresponding to each character information, the display start coordinate is the start coordinate of a character display dot matrix, the display resolution is the size of a character display dot matrix, in this embodiment, the size of the character display dot matrix is 8 × 12 pixels (Pixel), and the start coordinate of the character display dot matrix is (1,1), but not limited thereto. Then proceed to step ten 510.
In step ten 510, when the programmable logic unit 2 determines that the finite state machine is not normally executed, the switch 21 is controlled to operate in the debug mode, the debug display signal generated by the display information output device 227 is transmitted to the switch 21, and then the display information output terminal of the switch 21 transmits the debug display signal to the display 3, and the display 3 displays the update operation record text file to be displayed by the display information of the update operation record text file according to the debug display signal, so that the maintenance personnel can know which state or which signal value is not expected to be executed before the power start-up process is finished through the update operation record text file, thereby clarifying the reason why the power start-up process is not normally executed. And finally ending the self-built debugging process.
In summary, the debugging system of the boot program, the host and the method thereof of the present invention switch the operation mode of the switch 21 by the programmable logic unit 22 in the debugging mode, output the debugging display signal of the programmable logic unit 22 to the display 3 connected to the host, and make the display 3 display the updating operation record text file, so as to achieve the purpose of knowing the relevant information of the boot before the error occurred in the power starting process by only looking up the updating operation record text file without any additional external hardware, thereby effectively improving the debugging efficiency, and reducing the hardware cost required for debugging, thereby achieving the purpose of the present invention.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (11)
1. A debugging method of boot program is executed by a debugging system of boot program, the debugging system of boot program includes a host computer, the host computer includes a programmable logic unit, a base plate management controller, a switcher electrically connected to the programmable logic unit and the base plate management controller separately, and a display information output end electrically connected to the switcher, characterized in that, the debugging method of boot program includes following steps:
(A) the programmable logic unit receives a startup power sequence code, executes a power starting process according to the startup power sequence code, and judges whether the power starting process is normally executed;
(B) when the programmable logic unit judges that the power supply starting process is abnormal, the switcher is controlled to operate in a debugging mode, and in the debugging mode, the switcher is controlled to enable the programmable logic unit to be electrically connected with the display information output end;
(C) the programmable logic unit generates a detection signal value for indicating one of a plurality of state machine codes corresponding to a currently ongoing stage and one of the state machine codes corresponding to the currently ongoing stage in the power starting process according to the power starting process;
(D) the programmable logic unit converts at least one of the one state machine code corresponding to the current on-going stage and the detection signal value corresponding to the one state machine code into character information in a text file format to generate at least one variable character information;
(E) the programmable logic unit prestores a constant operation record character file information, and writes the at least one variable character information into a corresponding variable character field in the constant operation record character file to obtain display information of an updated operation record character file;
(F) the programmable logic unit transmits a debugging display signal corresponding to the updated operation record text file to the switcher for outputting through the display information output end;
the constant job record text file information further includes character information of a plurality of detection signal pin names.
2. The debugging method of the boot program of claim 1, wherein in step (C), the programmable logic unit converts the one of the state machine codes corresponding to the current on-going stage into a state character information in a text file format according to a pre-stored character information look-up table by looking up the table, and converts the detection signal value corresponding to the one of the state machine codes corresponding to the current on-going stage into a character information in a text file format.
3. The debugging method of the boot program of claim 1, further comprising the step of, after the step (A),
(H) the programmable logic unit receives a plurality of hardware signals from a plurality of hardware elements which are started to operate in the power supply starting process respectively.
4. The method of claim 3, wherein in step (H), the programmable logic unit correspondingly converts the detected values of the hardware signals into character information of hardware signal values in a text file format according to a pre-stored character information look-up table, wherein the character information of the hardware signal values is included in the variable character information.
5. A host with a boot debug function, comprising:
the display information output end is used for electrically connecting a display;
a switch having a first switch input terminal, a second switch input terminal, and a switch electrically connected to the display information output terminal, the switch being controlled to select one of the first switch input terminal and the second switch input terminal to be electrically connected to the display information input terminal;
a substrate management controller electrically connected to the second switching input terminal of the switch;
a programmable logic unit electrically connected to the first switching input terminal of the switch, pre-storing a constant operation record text file information, receiving a power-on sequence code, executing a power-on process according to the power-on sequence code to generate a variable character information,
the programmable logic unit writes the variable character information into the corresponding variable character field in the constant operation record text file information to obtain and transmit display information for updating the operation record text file,
when the programmable logic unit judges that the power supply starting process is not normally executed, the switcher is controlled to enter a debugging mode, so that the switcher is controlled to be electrically connected with the first switching input end and the display information output end, and a debugging display signal of display information related to the updating operation record character file and transmitted by the programmable logic unit is output through the display information output end.
6. The host of claim 5, wherein the programmable logic unit has a power sequencer processor and a display information processing module electrically connected to the power sequencer processor, the display information processing module pre-stores the constant job record text file information, the power sequencer processor receives the power sequencer code and executes the power startup procedure according to the power sequencer code, the display information processing module receives at least one state machine code from the power sequencer processor and a detection signal value of a corresponding state machine code, converts the at least one state machine code into the variable character information, determines that the power startup procedure has not been executed normally, and controls the switch to enter the debug mode.
7. The host computer of claim 6, wherein the display information processing module has a variable information updater, the variable information updater has a variable storage element storing a character information look-up table, the variable information updater receives and looks up the character information look-up table according to each state machine code and the detection signal value corresponding to each state machine code to obtain and transmit the variable character information, the variable character information includes character information of a state machine code obtained by table look-up conversion of the state machine code and character information of a detection signal value obtained by table look-up conversion of the detection signal value.
8. The host computer of claim 7, wherein the display information processing module further comprises a constant information generator, the constant information generator having a constant storage element for pre-storing the constant job record text file information.
9. The host of claim 8, wherein the display information processing module further comprises a display information outputter, the display information outputter receives display information of the update job record text file, converts the display information into the debug display signal according to the output format and the output voltage of the display, and outputs the debug display signal through the display information output terminal.
10. The host computer of claim 7, wherein the variable information updater further receives hardware signal values from hardware components that are activated to operate in the power activation process, the display information processing module correspondingly converts the hardware signal values into character information of hardware signal values in a text file format in a table look-up manner according to the pre-stored character information look-up table, the variable character information further includes character information of the hardware signal values, and the display information processing module correspondingly writes the variable character information into a variable character field in the constant operation record text file information to obtain and transmit the display information of the updated operation record text file.
11. A boot debug system, comprising:
a host computer including a display information output terminal, a switch, a substrate management controller and a programmable logic unit,
the switch includes a switch having a first switch input terminal, a second switch input terminal, and a switch electrically connected to the display information output terminal, the switch being controlled to select one of the first switch input terminal and the second switch input terminal to be electrically connected to the display information output terminal,
the baseboard management controller is electrically connected to the second switching input terminal of the switch,
the programmable logic unit is electrically connected with the first switching input end of the switcher, pre-stores a constant operation record text file information, receives a startup power sequence code, executes a power startup process according to the startup power sequence code, generates variable character information,
the programmable logic unit writes the variable character information into a corresponding variable character field in the constant operation record character file information to obtain and transmit display information of an updated operation record character file, and when the programmable logic unit judges that the power supply starting process is not normally executed, the programmable logic unit controls the switcher to enter a debugging mode so that the switcher is controlled to be electrically connected with the first switching input end and the display information output end to output a debugging display signal which is transmitted by the programmable logic unit and is related to the display information of the updated operation record character file through the display information output end;
a display electrically connected to the display information output terminal of the switcher, and receiving a debugging display signal of the display information related to the update operation record text file from the display information output terminal and displaying the update operation record text file when the switcher enters a debugging mode.
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| TWI453583B (en) * | 2011-07-25 | 2014-09-21 | Quanta Comp Inc | Computer system and diagnostic method thereof |
| US10474517B2 (en) * | 2016-07-18 | 2019-11-12 | American Megatrends International, Llc | Techniques of storing operational states of processes at particular memory locations of an embedded-system device |
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