CN1405677A - Method for turning-on computer capable of debugging system and computer system thereof - Google Patents
Method for turning-on computer capable of debugging system and computer system thereof Download PDFInfo
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- CN1405677A CN1405677A CN 02151358 CN02151358A CN1405677A CN 1405677 A CN1405677 A CN 1405677A CN 02151358 CN02151358 CN 02151358 CN 02151358 A CN02151358 A CN 02151358A CN 1405677 A CN1405677 A CN 1405677A
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Abstract
The system comprises the CPU, the system bus, the peripheral bus, the expansion bus, the south bridge and the north bridge, the ROM and debug system. The ROM connected to the expansion bus stores the program codes of the BIOS. The debug system is connected to the peripheral bus. The invention includes following steps. The CPU is switched to the normal mode, sending the data request from the system bus to the ROM. The CPU is switched to the debug mode, sending the data request from the system bus to the debug system. The north bridge transfers the data request in the system bus to the peripheral bus. Base on the position pointed by the data, the south bridge or debug system loads the BIOS to the CPU.
Description
Technical field
The present invention relates to a kind of method of computer system start, be particularly related to a kind of computer system and method for using the debugging system start, can when breaking down, still can carry out boot program and carry out debug in ROM-BIOS (BIOS) program code or its ROM (read-only memory) (ROM).
Background technology
In general, the framework of computer system is made up of a plurality of different levels.Lowest-order person is actual hardware layer, and high-order person is the application software with user's interaction.Between hardware and application software then is system software.System software itself also is divided into a plurality of parts, has comprised operating system kernel and skin, device driver or multitask executive routine.
Usually between hardware and system software, also can comprise the software layer of a low order, be referred to as ROM-BIOS (BIOS).BIOS provides basic output to go into service function between system or application software and hardware, and handles the interruptive command (interrupt) that is sent by system.Use via interruptive command can be carried out necessary control to computer system.These interruptive commands can be sent by microprocessor, system hardware or software.BIOS then handles these interruptive commands in the mode of Digital Logic.When an interruptive command produced, the control of computer system just can be handed on the interrupt vector (interrupt vector), and interrupt vector has defined in BIOS, joined section displacement (segment:offset) address of the route of giving certain interruption code.
BIOS interrupt service subroutine (ISRs, Interrupt Service Routines) is handled the interruptive command that is sent by hardware unit.Interrupt service subroutine has used the temporal data (register) in central processing unit and the BIOS data area.And BIOS device service subprogram (DSRs, DeviceService Routines) is then handled by the software interruption order of using the INT instruction to be sent.
BIOS is except the above-mentioned service that provides during computer system operation, and when the unified start of department of computer science, the essential bios program code of carrying out earlier is to carry out the work of initialization and configuration and setting for whole computer system.BIOS can carry out one at this moment and open the beginning program, is referred to as power initiation selftest (POST) program.This program can be carried out the work of many necessity, has comprised that the test of random access memory, examination are installed on devices all in the computer system, floppy disk, hard disk, keyboard, parallel port, serial port and other device (as CD-ROM or sound card or the like) that is installed in the computer system are carried out configuration and setting, will provide the computer hardware of necessary specific function (as plug and play, power management etc.) to carry out initialization.If what these work can both success finishes, then BIOS will begin the load operation system, as disc operating system (DOS) (DOS), LINUX, window 95, window 98 or the like, finishes whole start operation at last.
Because the start of computer system operation is very complicated, no matter be that BIOS or operating system all may make a mistake when starting and causes boot failure, make whole computer system can't operate at all, especially control in the start operation BIOS of groundwork.Therefore, for responsible BIOS designed system chipset fabricator, it is crucial work that bios program code is carried out debug (debug).
Yet, in that being removed, system bios staggers the time, and the situation of making us perplexing most is when system bios makes a mistake, computer system or the running of chipset can't start at all, and have no idea to learn the wrong reason that takes place.Must use this moment the most basic analytics just might locate errors reason, very labor intensive and time in the mode of direct measurement pin position signal.
Summary of the invention
In order to address the above problem, the invention provides a kind of method for turning-on computer capable of debugging system and computer system thereof, turn to debugging system by the data demand that makes central processing unit to ROM (read-only memory), and respond this requirement by debugging system, the BIOS that just can ignore fault, by debugging system catcher boot program, by debugging system BISO is revised or error analysis more afterwards.
One object of the present invention is to provide a kind of method of using the debugging system start, be applicable to a computer system, this computer system has a central processing unit, one system bus, one peripheral bus, one expansion bus, one first and second bridge, and one be connected to this expansion bus and store the ROM (read-only memory) of the first ROM-BIOS program code, this debugging system is connected to this peripheral bus, this method may further comprise the steps: this central processing unit is switched to a normal mode, under this normal mode, this central processing unit sends first data demand of this ROM (read-only memory) of sensing on this system bus; This central processing unit is switched to a debug mode, and under this debug mode, this central processing unit sends second data demand of this debugging system of sensing on this system bus; First or second data demand that will be positioned on this system bus by this first bridge transfers on this peripheral bus; Make this second bridge respond first data demand that is positioned on this peripheral bus, and this first ROM-BIOS program code is loaded this central processing unit with the first ROM-BIOS program code that is stored in this ROM (read-only memory); And make this debugging system respond this second data demand with one second ROM-BIOS program code, and this second ROM-BIOS program code is loaded this central processing unit.
Another object of the present invention is to provide a kind of computer system of using the debugging system start, comprise: a central processing unit, changeable between a normal mode and debug mode, under this normal mode, this central processing unit sends one first data demand on this system bus, and under this debug mode, this central processing unit sends second data demand of this debugging system of sensing on this system bus; One system, periphery and expansion bus, wherein this central processing unit sends this first or second data demand to this system bus, and this debugging system system is connected to this peripheral bus; One ROM (read-only memory) is connected to this expansion bus and stores one first basic output and goes into program code, and this first data demand points to this ROM (read-only memory); One first bridge, this first or second data demand that will be positioned on this system bus transfers to this peripheral bus; And one second bridge, be positioned at first data demand on this peripheral bus to be stored in first ROM-BIOS program code response in this ROM (read-only memory), and this first ROM-BIOS program code is loaded this central processing unit; Wherein, this debugging system responds this second data demand with one second ROM-BIOS program code, and this second ROM-BIOS program code is loaded this central processing unit.
By this, the present invention utilizes one to switch signal generator and open or force to forbid A20 door in the central processing unit, the data demand that central processing unit is sent points to address modification, and turn to debugging system, so just can ignore the BIOS in the ROM (read-only memory) and take over boot program, and then carry out correction or the error analysis of BISO by debugging system.
Below, the embodiment of accompanying drawings a kind of method for turning-on computer capable of debugging system and computer system thereof of the present invention.
Description of drawings
Fig. 1 has shown the computer system calcspar that can use the debugging system start in one embodiment of the invention.
Fig. 2 has shown the employed signal sequence of the computer system of Fig. 1.
Embodiment
Below, the embodiment of accompanying drawings a kind of method for turning-on computer capable of debugging system and computer system thereof of the present invention.
Fig. 1 has shown the computer system calcspar that can use the debugging system start in one embodiment of the invention.In computer system, all assemblies and bus be arranged at one can provide necessary coiling, slot, and the motherboard (figure shows) of other coupling arrangement of all kinds on.Computer system has a central processing unit 10, mainly is made of microprocessor, as intel pentium the 4th generation (Intel Pentium4).Central processing unit 10 is connected to a system bus 12, also has a high-speed cache 13 and is connected with it.
In central processing unit 10, has special A20 door (A20 gate) pin position 101.The origin of this A20 door pin position 101, be because of in the process of computer system development, 8086 old microprocessors have only the address space of 1MB size, and 20 address wires (A0-A19) have only been used, when surpassing this address scope, 8086 microprocessors just can make zero the address automatically, promptly so-called " line returns " (wraparound); Afterwards after 80286 new microprocessors develop out; it can have the address space of 16MB size; and 24 address wires have been used; but for make 80286 microprocessors can with old computer system compatibility; it must provide the address process mode identical with 8086 microprocessors; therefore two kinds of operator schemes are provided in 80286 microprocessors, i.e. the actual pattern (realmode) of the old system of emulation reaches the protected mode (protected mode) of directly using 24 address wires.In order to allow 24 address wires produce the effect that only is equivalent to 20 address wires, in the microprocessor after 80286, can use an A20 door, when this door is under an embargo (disable), just can make the 21st address wire (A20) carry-out bit " 0 " forever, and the address realm of central processing unit 10 outputs is locked within the 1MB, realize the purpose of the old system of emulation.Along with the continuous progress of little processing, the processor of a new generation as IntelPentium 4, all directly intactly uses 24 address wires with this unlatching.
Therefore, in the present embodiment, in order to be implemented in the purpose that the data demand that pointed to the BIOS ROM (read-only memory) originally can be diverted to debugging system under the debug mode, used one to switch the A20 door pin position 101 of signal generator 102 outputs one switching signal to central processing unit 10.This switching signal is under an embargo the A20 door in the central processing unit 10 with forcing, and makes the position of central processing unit 10 on address wire A20 be forced to change, and the address after the change will be set to debugging system.On the other hand, under normal mode, switching signal generator 102 can not trigger switching signal, makes the OPADD of central processing unit 10 keep original value.
There is multiple different device can be connected to peripheral bus 18, as image processor (display card) 22.In addition, a debug adapter 24 also is connected to peripheral bus 18.The function of debug adapter 24 is as computer system and another is except that the connecting interface between the computer system of misusing.
There is multiple different device to be connected to expansion bus 30 via slot 32a, 32b and 32c.ROM (read-only memory) 16 is connected to expansion bus 30 via slot 34.ROM (read-only memory) 16 has stored the employed program code of BIOS.
Fig. 2 has shown the signal sequence of computer system when using the start of ROM (read-only memory) 16 or debugging system.In fact, in the communications protocol of pci bus, used very many signals, only shown the signal relevant herein with the present invention.
As shown in Figure 2, signal CLK is the clock signal that comes from system, and signal RESET resets signal, and when reseting, signal RESET produces a logic high earlier, returns default low level afterwards.
No matter under normal or debug mode, when central processing unit 10 sent a data demand that points to ROM (read-only memory) or debugging system to system bus 12, north bridge chips 20 will trigger pip ROMSEL$.As use habit, adding behind the signal name that " $ " symbol is to represent this signal to have low logic level (active low) when being triggered.The data address (address of ROM (read-only memory) address or debugging system storer) that is required access will be sent along with data demand, and will be transferred on the pci bus 18 by north bridge chips 20.Simultaneously, also being loaded with relevant control signal in the data demand is required to represent a read cycle.According to the communications protocol of pci bus, the device that is pointed to by data demand should be in this read cycle after the phase place of address three clock period select signal DEVSEL$ with interior response one device, with presentation address effectively and can decipher.Therefore, when central processing unit 10 is in normal mode following time, South Bridge chip 28 just can use the signal ROMSEL$ from north bridge chips 20 to touch that its address decoder 283 is deciphered and at response DEVSEL$ signal within three clock period to pci bus 18, after finishing, decoding can read simultaneously in the ROM (read-only memory) 16 and the relative bios program code data of institute's decoding address, so that it is loaded in central processing unit 10.On the other hand, when central processing unit 10 is in debug mode, owing to pointing to be changed, its data demand that sends turns to debug adapter 24, therefore South Bridge chip 28 can't be done response to the ROMSEL$ signal that north bridge chips 20 is sent, respond but on pci bus 18, produce the DEVSEL$ signal by debug adapter 24, and decipher the address during data are required, according to the address after the decoding, the bios program code data that itself store are sent and loaded in the central processing unit 10.
By above-mentioned operation as can be known, because when central processing unit 10 is switched to debug mode, its original data demand that points to ROM (read-only memory) is changed and turns to debug adapter 24, therefore debugging system just can replace South Bridge chip 28 and comes the ROMSEL$ signal that north bridge chips 20 is sent is responded, and with in the bios program code data load central processing unit 10 that itself stores.So, no matter ROM (read-only memory) 16, be stored in the ROM (read-only memory) 16 bios program code even or problems when taking place in South Bridge chip 28, can force to forbid that the A20 of central processing unit 10 ignores these problems behind the door by use switching signal generator 282, and directly start shooting by debugging system.In addition, be connected because debug adapter 24 removes the computer system 4 of misusing with another, its stored bios program code also can be programmed via computer system 4.
When using debugging system to start shooting, can also carry out following program:
1. be connected with pci bus owing to removing the computer system 4 of misusing, can in computer system 4, use the mode of software, when directly reading in start operation beginning via debug adapter 24 and north bridge chips 20, the stored data content of buffer in the central processing unit 10 (register).Traditionally, this step can only or be used oscillograph directly read pin position signal and realize with logic analysis.
2. do not have under the situation of damage at South Bridge chip 28 and ROM (read-only memory) 16, utilize computer system 4 to read and be stored in the bios program code data that may make a mistake in the ROM (read-only memory) 16, to analyse and compare via debug adapter 24, South Bridge chip 28.
3. under the situation that South Bridge chip 28 and ROM (read-only memory) 16 do not have to damage, utilize computer system 4 via debug adapter 24, South Bridge chip 28 with in the burned ROM (read-only memory) 16 of correct bios program code.
Comprehensively above-mentioned, the invention provides a kind of method for turning-on computer capable of debugging system and computer system thereof, utilize one to switch signal generator and open or force to forbid A20 door in the central processing unit, the data demand that central processing unit is sent points to address modification, and turn to debugging system, so just can ignore the BIOS in the ROM (read-only memory) and take over boot program, and then carry out correction or the error analysis of BISO by debugging system.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, so the scope that protection scope of the present invention is looked accompanying Claim is as the criterion.
Claims (10)
1. the method that can use debugging system start, be applicable to a computer system, this computer system has the ROM (read-only memory) that a central processing unit, a system bus, a peripheral bus, an expansion bus, first and second bridge and are connected to this expansion bus and store the first ROM-BIOS program code, this debugging system is connected to this peripheral bus, and this method may further comprise the steps:
This central processing unit is switched to a normal mode, and under this normal mode, this central processing unit sends first data demand of this ROM (read-only memory) of sensing on this system bus;
This central processing unit is switched to a debug mode, and under this debug mode, this central processing unit sends second data demand of this debugging system of sensing on this system bus;
First or second data demand that will be positioned on this system bus by this first bridge transfers on this peripheral bus;
Make this second bridge respond first data demand that is positioned on this peripheral bus, and this first ROM-BIOS program code is loaded this central processing unit with the first ROM-BIOS program code that is stored in this ROM (read-only memory); And
Make this debugging system respond this second data demand, and this second ROM-BIOS program code is loaded this central processing unit with one second ROM-BIOS program code.
2. the method for using the debugging system start as claimed in claim 1, wherein further comprising the steps of:
When this central processing unit is switched to this debug mode, read and show the stored contents of most buffers in this central processing unit by this debugging system.
3. the method for using the debugging system start as claimed in claim 1, wherein further comprising the steps of:
When this central processing unit is switched to this debug mode, in this ROM (read-only memory), read this first ROM-BIOS program code via this second bridge by this debugging system.
4. the method for using the debugging system start as claimed in claim 1, wherein further comprising the steps of:
When this central processing unit is switched to this debug mode, by this debugging system via this second bridge with in burned this ROM (read-only memory) of this second ROM-BIOS program code.
5. the method for using debugging system start as claimed in claim 1 is wherein by opening or forcing to forbid an A20 door of this central processing unit and this central processing unit is switched between this normal and debug mode.
6. the method for using debugging system start as claimed in claim 1, wherein this second bridge is selected signal to decipher to peripheral bus, with the address in this first data demand and read according to this address to be stored in that the relative first ROM-BIOS program code responds this data demand in this ROM (read-only memory) by sending a device.
7. the method for using debugging system start as claimed in claim 1, wherein this debugging system is selected signal to decipher to peripheral bus, with the address in this second data demand and read according to this address to be stored in that the relative second ROM-BIOS program code responds this data demand in this ROM (read-only memory) by sending a device.
8. the computer system that can use debugging system start comprises:
One central processing unit, changeable between a normal mode and debug mode, under this normal mode, this central processing unit sends one first data demand on this system bus, and under this debug mode, this central processing unit sends second data demand of this debugging system of sensing on this system bus;
One system, periphery and expansion bus, wherein this central processing unit sends this first or second data demand to this system bus, and this debugging system system is connected to this peripheral bus;
One ROM (read-only memory) is connected to this expansion bus and stores one first basic output and goes into program code, and this first data demand points to this ROM (read-only memory);
One first bridge, this first or second data demand that will be positioned on this system bus transfers to this peripheral bus; And
One second bridge responds first data demand that is positioned on this peripheral bus with the first ROM-BIOS program code that is stored in this ROM (read-only memory), and this first ROM-BIOS program code is loaded this central processing unit;
Wherein, this debugging system responds this second data demand with one second ROM-BIOS program code, and this second ROM-BIOS program code is loaded this central processing unit.
9. the computer system of using debugging system start as claimed in claim 8, wherein this central processing unit has an A20 door, by opening and forcing to forbid this A20 door and carry out switching between normal mode and debug mode.
10. the computer system of using debugging system start as claimed in claim 8, wherein should the periphery and expansion bus be respectively PCI and isa bus, this first and second bridge is respectively north bridge and south bridge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021513589A CN1170221C (en) | 2002-11-18 | 2002-11-18 | Method for turning-on computer capable of debugging system and computer system thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021513589A CN1170221C (en) | 2002-11-18 | 2002-11-18 | Method for turning-on computer capable of debugging system and computer system thereof |
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| CN1405677A true CN1405677A (en) | 2003-03-26 |
| CN1170221C CN1170221C (en) | 2004-10-06 |
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| CNB021513589A Expired - Lifetime CN1170221C (en) | 2002-11-18 | 2002-11-18 | Method for turning-on computer capable of debugging system and computer system thereof |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100334556C (en) * | 2003-09-30 | 2007-08-29 | 宏达国际电子股份有限公司 | Method of starting operated during CPU shutdown and computer system thereof |
| CN100382059C (en) * | 2003-11-14 | 2008-04-16 | 威盛电子股份有限公司 | Computer system having multi-tasking I/O interface module framework |
| CN100386709C (en) * | 2003-06-06 | 2008-05-07 | 中国科学院计算技术研究所 | Dragon core-1 CPU network computer main board system and reset method |
| CN100395714C (en) * | 2005-05-28 | 2008-06-18 | 鸿富锦精密工业（深圳）有限公司 | Circuit for identificating front-end bus of central processor |
| CN100432952C (en) * | 2006-06-20 | 2008-11-12 | 威盛电子股份有限公司 | System for pick-up bus transmission and its method |
| CN100442231C (en) * | 2006-09-20 | 2008-12-10 | 威盛电子股份有限公司 | Method and device for computer system startup |
| CN101106441B (en) * | 2007-08-10 | 2011-05-04 | 华为技术有限公司 | Method and device for reducing service interruption time |
| CN112579178A (en) * | 2019-09-29 | 2021-03-30 | 佛山市顺德区顺达电脑厂有限公司 | Debugging system for boot program, and host and method thereof |
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2002
- 2002-11-18 CN CNB021513589A patent/CN1170221C/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100386709C (en) * | 2003-06-06 | 2008-05-07 | 中国科学院计算技术研究所 | Dragon core-1 CPU network computer main board system and reset method |
| CN100334556C (en) * | 2003-09-30 | 2007-08-29 | 宏达国际电子股份有限公司 | Method of starting operated during CPU shutdown and computer system thereof |
| CN100382059C (en) * | 2003-11-14 | 2008-04-16 | 威盛电子股份有限公司 | Computer system having multi-tasking I/O interface module framework |
| CN100395714C (en) * | 2005-05-28 | 2008-06-18 | 鸿富锦精密工业（深圳）有限公司 | Circuit for identificating front-end bus of central processor |
| CN100432952C (en) * | 2006-06-20 | 2008-11-12 | 威盛电子股份有限公司 | System for pick-up bus transmission and its method |
| CN100442231C (en) * | 2006-09-20 | 2008-12-10 | 威盛电子股份有限公司 | Method and device for computer system startup |
| CN101106441B (en) * | 2007-08-10 | 2011-05-04 | 华为技术有限公司 | Method and device for reducing service interruption time |
| CN112579178A (en) * | 2019-09-29 | 2021-03-30 | 佛山市顺德区顺达电脑厂有限公司 | Debugging system for boot program, and host and method thereof |
| CN112579178B (en) * | 2019-09-29 | 2022-04-05 | 佛山市顺德区顺达电脑厂有限公司 | Debugging system for boot program, and host and method thereof |
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| CN1170221C (en) | 2004-10-06 |
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