TWI815725B - Computer system - Google Patents

Abstract

A computer system includes a CPLD including a serial transmission interface, a set of specific signal pins, a set of power input pins, a first multiplexer, an embedded CPU, a first memory, a second multiplexer, a third memory, and a first control unit. The first control unit controls the first multiplexer, the second multiplexer, or the embedded CPU so that a plurality of specific signals of the specific signal pins, a plurality of power supply voltage signals of the power input pins, or the data of the first memory pass through the first multiplexer, the second multiplexer, the third memory, the serial transmission interface, and a high-speed interface conversion device are output to a test host based on a test command from the test host.

Description

computer system

The present invention relates to a computer system, and in particular, to a computer system with a flexible debugging mechanism.

Referring to Figure 1, the existing computer system is, for example, a server and is suitable for a low-speed interface conversion device 80 and a test host 9, and includes a motherboard 7 and a complex programmable logic device ( CPLD) 1, a basic input and output system (BIOS) 2, a baseboard management controller (BMC) 3, a power converter (Voltage regulator) 5, a central processing unit (CPU) 4, and a connector 6. The complex programmable logic device 1 includes a first control unit 93, a multiplexer (Mux) 92, a sequence transmission interface 91, a set of power input pins 98, a set of specific signal pins 99, an embedded Central processing unit (Embedded CPU) 94, a first memory 95 to a third memory 90, and a second control unit 96. The test host 9 is, for example, a computer host, and is electrically connected to the low-speed interface conversion device 80 through a universal serial bus interface. The low-speed interface conversion device 80 is used for converting and transmitting signals between two interfaces: integrated bus circuit (I2C) and universal serial bus (USB).

The first memory 95 is an internal flash memory (Flash) and is used to provide the embedded central processor 94 with data access. The second control unit 96 stores the signals from the basic input and output system 2 and the baseboard management controller 3 (such as the register of the Mailbox) in the second memory through the system management bus (SMBus) interface. 97. The second memory 97 is an internal random access memory (RAM). The power converter 5 is used to provide power supplies with various voltages required for operation of various components on the motherboard 7 . The set of power input pins 98 and the set of specific signal pins 99 are, for example, used to receive the baseboard management controller 3, the central processing unit 4, a system memory (not shown), and a chipset (PCH) (Fig. (not shown) each power supply voltage signal and each power supply reset signal (Reset).

The conventional computer system is limited by the space size of the third memory 90, and usually can only input signals from a small part (such as 32 pins) of the set of power input pins 98 in advance during the boot process. The timing changes of the selected 32 power supply voltage signals in logic 0 and 1 are stored in the third memory 90 . The first control unit 93 can receive instructions from the test host 9 through the low-speed interface conversion device 80 and the serial transmission and reception interface 91 to control the multiplexer 92 to select the 32 data stored in the third memory 90 The timing changes of the power supply voltage signal are output to the test host 9 through the sequence transmission interface 91 and the low-speed interface conversion device 80, or a preset part of the specific signal pins 99 is selected to be transmitted through the sequence The transmission and reception interface 91 and the low-speed interface conversion device 80 are output to the test host 9 in real time. However, whether there are other computer systems with more flexible debugging mechanisms has become a problem to be solved.

Therefore, an object of the present invention is to provide a computer system with a flexible debugging mechanism.

Therefore, one aspect of the present invention provides a computer system suitable for a high-speed interface conversion device and a test host, and includes a complex programmable logic device, a basic input and output system (BIOS), and a baseboard management controller (BMC). ), and a central processing unit. The complex programmable logic device includes a serial transmission interface, a set of specific signal pins, a set of power input pins, a first multiplexer, an embedded central processing unit, a first memory, a second A multiplexer, a third memory, and a first control unit.

The serial transmission and reception interface is electrically connected to the high-speed interface conversion device. The aforementioned set of specific signal pins receives a plurality of specific signals from the basic input output system, the baseboard management controller, and the central processing unit. The aforementioned set of power input pins receives multiple power voltage signals. The first multiplexer includes a set of output ends electrically connected to the sequence transmission interface, a set of first ends, a set of second ends electrically connected to the set of specific signal pins to receive the specific signals, and a set of The control end selects the signal of the aforementioned set of first ends or the aforementioned set of second ends according to the signal received by the control end and outputs it to the aforementioned set of output ends.

The first memory is electrically connected to the embedded CPU and used to provide the embedded CPU with access to data. The second multiplexer includes a set of first ends electrically connected to the aforementioned set of power input pins to receive the power supply voltage signals, a set of second ends electrically connected to the embedded CPU, a control end, and A group of output terminals, and according to the signal received by the control terminal, the signal of the aforementioned group of first terminals or the aforementioned group of second terminals is selected and output to the aforementioned group of output terminals. The third memory is electrically connected to the aforementioned set of output terminals of the second multiplexer to store the data output by the aforementioned set of output terminals, and is electrically connected to the aforementioned set of first terminals of the first multiplexer to store the data output by the aforementioned set of output terminals. Output the stored data to the first end of the aforementioned group.

The first control unit is electrically connected to the serial transmission and reception interface, the control end of the first multiplexer, the control end of the second multiplexer, and the embedded central processor, and passes through the high-speed interface conversion device and the sequence transmission and reception interface receives a test command from the test host.

The first control unit controls the first multiplexer according to the test instruction so that the specific signals are output to the test host through the first multiplexer, the serial transmission and reception interface, and the high-speed interface conversion device, or , controlling the second multiplexer and the first multiplexer so that the power supply voltage signals pass through the second multiplexer, the third memory, the first multiplexer, the serial transmission and reception interface, and the The high-speed interface conversion device outputs to the test host, or controls the embedded central processor to output the data of the first memory to the aforementioned set of second terminals of the second multiplexer, and controls the second multiplexer. The multiplexer and the first multiplexer allow the data of the first memory to pass through the second multiplexer, the third memory, the first multiplexer, the serial transmission interface, and the high-speed interface conversion device And output to the test host.

In some implementations, the complex programmable logic device further includes a second control unit, and a second memory electrically connected to the second control unit. The second control unit is electrically connected to the basic input output system and the baseboard management controller through the interface of the system management bus, so as to store the data of the basic input output system and the baseboard management controller in the second memory. .

The second multiplexer also includes a group of third terminals electrically connected to the second control unit, and selects the aforementioned group of first terminals, the aforementioned group of second terminals, or the aforementioned group of terminals according to the signal received by the control terminal. The signal of the third terminal is grouped and output to the aforementioned group of output terminals.

The first control unit is also electrically connected to the second control unit, and according to the test instruction, can also control the second control unit to output the data of the second memory to the aforementioned set of third groups of the second multiplexer. terminal, and controls the second multiplexer and the first multiplexer so that the data of the second memory passes through the second multiplexer, the third memory, the first multiplexer, and the sequence interface, and the high-speed interface conversion device and output to the test host.

In some implementations, the CPU receives a set of backplane hard drive signals via a connector. The complex programmable logic device also includes a receiver address decoder. The receiver address decoder includes a device electrically connected to the CPU through an interface of the system management bus to receive the aforementioned set of backplane hard disk signals. A set of input terminals, a set of output terminals, and a control terminal electrically connected to the first control unit.

The second multiplexer also includes a set of fourth terminals electrically connected to the aforementioned set of output terminals of the receiver address decoder, and selects the aforementioned set of first ends, the aforementioned set of output terminals according to the signal received by the control terminal. The signals from the second terminal, the aforementioned group of third terminals, or the aforementioned group of fourth terminals are output to the aforementioned group of output terminals.

The first control unit is electrically connected to the receiver address decoder, and according to the test command, can also control the receiver address decoder to output the aforementioned set of backplane hard disk signals to the aforementioned set of backplane hard disk signals of the second multiplexer. This set of fourth terminals controls the second multiplexer and the first multiplexer so that the aforementioned set of backplane hard disk signals passes through the second multiplexer, the third memory, and the first multiplexer. , the serial transmission and reception interface, and the high-speed interface conversion device are output to the test host.

Therefore, another aspect of the present invention provides a computer system suitable for a high-speed interface conversion device and a test host, and includes a complex programmable logic device, an external memory, a basic input and output system, and a substrate management control device, and a central processing unit. The complex programmable logic device includes a serial transmission interface, a set of specific signal pins, a set of power input pins, a first multiplexer, an embedded central processing unit, a first buffer, and a second buffer, a memory controller, and a first control unit.

The serial transmission and reception interface is electrically connected to the high-speed interface conversion device. The aforementioned set of specific signal pins receives a plurality of specific signals from the basic input output system, the baseboard management controller, and the central processing unit. The aforementioned set of power input pins receives multiple power voltage signals. The first multiplexer includes a set of output ends electrically connected to the sequence transmission interface, a set of first ends, a set of second ends electrically connected to the set of specific signal pins to receive the specific signals, and a set of The control end selects the signal of the aforementioned set of first ends or the aforementioned set of second ends according to the signal received by the control end and outputs it to the aforementioned set of output ends.

The first buffer is electrically connected to the aforementioned set of power input pins to receive the power voltage signals, buffer them and then output them. The second buffer is electrically connected to the aforementioned set of first terminals of the first multiplexer to output the received data after buffering. The memory controller is electrically connected to the first buffer, the second buffer, and the plug-in memory, and is controlled to store data from the first buffer to the plug-in memory, and to store data from the plug-in memory. The data stored in the body is output to the second buffer.

The first control unit is electrically connected to the serial transmission and reception interface, the control end of the first multiplexer, and the memory controller, and receives data from the test host through the high-speed interface conversion device and the serial transmission and reception interface. A test command.

The first control unit controls the first multiplexer according to the test command so that the specific signals are output to the test host through the first multiplexer, the serial transmission and reception interface, and the high-speed interface conversion device, or, The memory controller and the first multiplexer are controlled so that the power supply voltage signals pass through the first buffer, the memory controller, the plug-in memory, the second buffer, the first multiplexer, The serial transmission and reception interface and the high-speed interface conversion device are output to the test host.

In some implementations, the complex programmable logic device further includes an embedded central processing unit and a first memory. The first memory is electrically connected to the embedded central processing unit and is used to provide the embedded central processing unit. The central processing unit accesses data.

The first buffer is also electrically connected to the embedded CPU to receive the output data, buffer it and then output it. The first control unit is also electrically connected to the embedded central processor, and according to the test instruction, can also control the embedded central processor to output the data of the first memory to the first buffer, and control the memory The bank controller and the first multiplexer cause the data of the first memory to pass through the first buffer, the memory controller, the plug-in memory, the second buffer, the first multiplexer, the The serial transmission and reception interface and the high-speed interface conversion device are output to the test host.

In some implementations, the complex programmable logic device further includes a second control unit and a second memory electrically connected to the second control unit. The second control unit is electrically connected to the basic input output system and the baseboard management controller through the interface of the system management bus, so as to store the data of the basic input output system and the baseboard management controller in the second memory. .

The first buffer is also electrically connected to the second control unit to receive the output data, buffer it and then output it. The first control unit is also electrically connected to the second control unit, and according to the test instruction, can also control the second control unit to output the data of the second memory to the first buffer, and control the memory control The controller and the first multiplexer allow the data of the second memory to pass through the first buffer, the memory controller, the plug-in memory, the second buffer, the first multiplexer, and the serial transmitter. The receiving interface and the high-speed interface conversion device output to the test host.

In some implementations, the CPU receives a set of backplane hard drive signals via a connector. The complex programmable logic device also includes a receiver address decoder. The receiver address decoder includes a device electrically connected to the CPU through an interface of the system management bus to receive the aforementioned set of backplane hard disk signals. A set of input terminals, a set of output terminals, and a control terminal electrically connected to the first control unit.

The first buffer is also electrically connected to the aforementioned set of output terminals of the receiver address decoder to receive the output data, buffer it and then output it. The first control unit is also electrically connected to the receiver address decoder, and according to the test instruction, can also control the receiver address decoder to output the aforementioned set of backplane hard disk signals to the first buffer, and The memory controller and the first multiplexer are controlled so that the aforementioned set of backplane hard disk signals passes through the first buffer, the memory controller, the plug-in memory, the second buffer, and the first multiplexer. The processor, the serial transmission and reception interface, and the high-speed interface conversion device are output to the test host.

The effect of the present invention is to control the second multiplexer and the embedded central processor through the first control unit, and select the data stored in the first memory by the embedded central processor or the aforementioned set of power inputs. The power supply voltage signals received by the pins are output to the first multiplexer and control the first controller to select the data of the first memory, the power supply voltage signals, or the aforementioned set of specific signal connections. The specific signals received by the pins can be output to the test host in real time through the high-speed interface conversion device, so a more flexible debugging mechanism can be implemented.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are designated with the same numbering.

Referring to Figure 2, a first embodiment of the computer system of the present invention is suitable for a high-speed interface conversion device 8 and a test host 9, and includes a motherboard 7 and a complex programmable logic device ( CPLD) 1, a basic input and output system (BIOS) 2, a baseboard management controller (BMC) 3, a central processing unit (CPU) 4, a power converter (Voltage regulator) 5, and a connector 6. The test host 9 is, for example, a computer host, and is electrically connected to the high-speed interface conversion device 8 through a Universal Serial Bus (USB) interface. The high-speed interface conversion device 8 is electrically connected to the complex programmable logic device 1 using, for example, a serial peripheral interface (SPI), and is used to provide signal conversion between a universal serial bus and a serial peripheral interface. The power converter 5 is used to stabilize multiple voltages from a power supply and output them into multiple power voltage signals for use as the basic input and output system 2 , the baseboard management controller 3 , and the central processing unit 4 , and the power required for the operation of various components such as a chipset.

The complex programmable logic device 1 includes a serial transmission interface 11, a set of specific signal pins 19, a set of power input pins 18, a first multiplexer (MUX) 12, a first control unit 13, a Embedded CPU 14, a first memory 15, a second control unit 16, a second memory 17, a second multiplexer 22, a third memory 23, and a receiver address decoding RX address decoder21.

The embedded CPU 14 is electrically connected to the first memory 15 and is at least used to execute a PFR (Platform firmware resilience) mechanism. The first memory 15 is an internal flash memory (Flash) and is used to provide the embedded central processor 14 with access to data. The second control unit 16 is electrically connected to the embedded central processing unit 14, and is electrically connected to the basic input and output system 2 and the baseboard management controller 3 through a system management bus (SMBus) interface to respond to the basic input and output system 2 and the baseboard management controller 3. The data of the input and output system 2 and the baseboard management controller 3 (such as the register value corresponding to the Mailbox) are stored in the second memory 17. The second memory 17 is an internal random access memory (RAM). And can also be used to provide the baseboard management controller 3 to write data (such as updating the basic input and output system 2, the baseboard management controller 3, and the upgraded version of the complex programmable logic device 1), and provide the complex programmable logic device 1 Program logic device 1 writes data.

The aforementioned set of specific signal pins 19 receives, for example, multiple specific signals from the basic input and output system 2, the baseboard management controller 3, the central processing unit 4, or other components, such as multiple power restart signals ( Reset). The aforementioned set of power input pins 18 receives the power voltage signals.

The CPU 4 receives a set of backplane hard disk signals from a backplane via the connector 6, and the aforementioned set of backplane hard disk signals is used for the status of multiple hard disks. The receiver address decoder 21 includes a set of input terminals, a set of output terminals, and a set of output terminals electrically connected to the CPU 4 through a system management bus interface to receive the aforementioned set of backplane hard disk signals. A control terminal of the first control unit 13 selects a corresponding one of the signals of the aforementioned set of input terminals according to the signal received by the control terminal and outputs the signal to the aforementioned set of output terminals.

The second multiplexer 22 includes a set of first ends electrically connected to the aforementioned set of power input pins 18 to receive the power supply voltage signals, a set of second ends electrically connected to the embedded CPU 14 , and a set of second ends electrically connected to the embedded CPU 14 . A set of third terminals of the second control unit 16, a set of fourth terminals electrically connected to the aforementioned set of output terminals of the receiver address decoder 21, a control terminal electrically connected to the first control unit 13, and Connect a group of output terminals of the third memory 23, and select the aforementioned group of first terminals, the aforementioned group of second terminals, the aforementioned group of third terminals, or the aforementioned group of third terminals according to the signal received by the control terminal. The signals from the four terminals are output to the aforementioned set of output terminals.

The first multiplexer 12 includes a set of output terminals, a set of first terminals, a set of second terminals electrically connected to the aforementioned set of specific signal pins 19 to receive the specific signals, and a set of electrically connected to the first control unit. A control terminal of 13, and according to the signal received by the control terminal, the signal of the aforementioned group of first terminals or the aforementioned group of second terminals is selected and output to the aforementioned group of output terminals. The third memory 23 is electrically connected to the aforementioned set of output terminals of the second multiplexer 22 to store the data output by the aforementioned set of output terminals of the second multiplexer 22, and is electrically connected to the first multiplexer 22. The aforementioned set of first terminals of the first multiplexer 12 is used to output the stored data to the aforementioned set of first terminals of the first multiplexer 12 . The serial transmission and reception interface 11 is electrically connected to the high-speed interface conversion device 8 , the aforementioned set of output terminals of the serial transmission and reception interface 11 , and the first control unit 13 .

The first control unit 13 is also electrically connected to the embedded CPU 14 and the second control unit 16, and receives a test command from the test host 9 through the serial transmission and reception interface 11 and the high-speed interface conversion device 8 .

The first control unit 13 can control the first multiplexer 12 according to the test command so that the specific signals are transmitted in real time through the first multiplexer 12 , the serial transmission and reception interface 11 , and the high-speed interface conversion device 8 output to the test host 9. Alternatively, the first control unit 13 can control the second multiplexer 22 and the first multiplexer 12 according to the test instruction so that the power supply voltage signals are stored in the third memory through the second multiplexer 22 The body 23 is then output to the test host 9 through the first multiplexer 12, the serial transmission and reception interface 11, and the high-speed interface conversion device 8.

Alternatively, the first control unit 13 can control the embedded central processor 14 to output the data of the first memory 15 to the aforementioned set of second terminals of the second multiplexer 22 according to the test instruction, and control The second multiplexer 22 and the first multiplexer 12 allow the data of the first memory 15 to be stored in the third memory 23 through the second multiplexer 22 and then through the first multiplexer 12 , the serial transmission and reception interface 11 , and the high-speed interface conversion device 8 and output to the test host 9 .

Alternatively, the first control unit 13 can control the second control unit 16 to output the data of the second memory 17 to the aforementioned set of third terminals of the second multiplexer 22 according to the test instruction, and control the The second multiplexer 22 and the first multiplexer 12 allow the data of the second memory 17 to be stored in the third memory 23 through the second multiplexer 22, and then through the first multiplexer 12, The serial transmission and reception interface 11 and the high-speed interface conversion device 8 output to the test host 9 .

Alternatively, the first control unit 13 can control the receiver address decoder 21 to output the aforementioned set of backplane hard disk signals to the aforementioned set of fourth terminals of the second multiplexer 22 according to the test command, and The second multiplexer 22 and the first multiplexer 12 are controlled so that the aforementioned set of backplane hard disk signals are stored in the third memory 23 through the second multiplexer 22 and then passed through the first multiplexer. 12. The serial transmission and reception interface 11 and the high-speed interface conversion device 8 output to the test host 9 .

That is to say, when the storage space of the third memory 23 is limited, the third memory 23 can completely record the power supply voltage signals with a small amount of data, the data of the first memory 15, and the third memory. The data in the second memory 17 or the backplane hard disk signals, such as the voltage corresponding to the timing changes of logic 0 and 1. On the contrary, the specific signals whose data volume is large and cannot be completely stored in the third memory 23 can be output to the test host 9 in real time through the high-speed interface conversion device 8 .

Referring to Figure 3, a second embodiment of the computer system of the present invention is shown. The functions of some components are the same as those of the first embodiment. The difference is that the computer system also includes an external memory 71, and the complex programmable logic device The second multiplexer 22 and the third memory 23 are omitted, and a first buffer 24, a second buffer 25, and a memory controller 26 are also included.

The first buffer 24 is electrically connected to the aforementioned set of power input pins, the embedded CPU, the second control unit, the aforementioned set of output terminals of the receiver address decoder, and the memory controller 26 , so as to be able to receive the power voltage signals, the data of the first memory, the data of the second memory, and the aforementioned set of backplane hard disk signals, and output them to the memory controller 26 after buffering .

The second buffer 25 is electrically connected to the memory controller 26 and the aforementioned set of first terminals of the first multiplexer, so as to buffer the data from the memory controller 26 and then output it to the third buffer. The aforementioned set of first terminals of a multiplexer.

The memory controller 26 is also electrically connected to the external memory 71 and the first control unit, and is controlled by the first control unit to store data from the first buffer 24 to the external memory 71, and The data stored in the external memory 71 is output to the second buffer 25 .

The first control unit can control the first multiplexer according to the test command so that the specific signals are output to the test host through the first multiplexer, the serial transmission and reception interface, and the high-speed interface conversion device, Alternatively, the first control unit can control the memory controller 26 and the first multiplexer according to the test instruction so that the power supply voltage signals are stored in the memory controller 26 via the first buffer 24 and the memory controller 26 . The external memory 71 is then output to the test host through the memory controller 26, the second buffer 25, the first multiplexer, the serial transmission and reception interface, and the high-speed interface conversion device.

Alternatively, the first control unit can control the embedded central processor to output the data of the first memory to the first buffer 24 according to the test instruction, and control the memory controller 26 and the first multiplexer. The processor causes the data of the first memory to be stored in the plug-in memory 71 through the first buffer 24 and the memory controller 26, and then passes through the memory controller 26, the second buffer 25, and the The first multiplexer, the serial transmission and reception interface, and the high-speed interface conversion device are output to the test host.

Alternatively, the first control unit can enable the second control unit to output the data of the second memory to the first buffer 24 and control the memory controller 26 and the first multiplexer according to the test instruction. The data in the second memory is stored in the plug-in memory 71 through the first buffer 24 and the memory controller 26, and then passes through the plug-in memory 71, the second buffer 25, and the first multi-function memory 71. The processor, the serial transmission and reception interface, and the high-speed interface conversion device are output to the test host.

Alternatively, the first control unit can control the receiver address decoder to output the aforementioned set of backplane hard disk signals to the first buffer 24 according to the test command, and control the memory controller 26 and the third A multiplexer allows the aforementioned set of backplane hard disk signals to be stored in the external memory 71 through the first buffer 24 and the memory controller 26, and then pass through the external memory 71 and the second buffer 25 , the first multiplexer, the serial transmission and reception interface, and the high-speed interface conversion device are output to the test host.

In other words, in the second embodiment, the storage space of the external memory 71 can be larger than the third memory 23 of the complex programmable logic device, so that various signals or data that engineers want to observe can be completely processed. Storage and recording, and then output to the test host to provide debugging use.

To sum up, compared with the previous technology shown in Figure 1, the memory space for storing data is limited, and the only parts that can be debugged are the motherboard boot sequence and the pin status of the complex programmable logic device after the motherboard is powered on. In this case, through the arrangement and design of different hardware and software of the complex programmable logic device of the computer system, or coupled with the use of the plug-in memory 71, the ways in which debugging can be greatly increased, such as the motherboard boot sequence The pin status of the complex programmable logic device after the motherboard is powered on, the backplane hard disk signal, the data status of the internal flash memory (such as the first memory), the data of the baseboard management controller and the basic input and output system status, thus realizing a more flexible debugging mechanism, thus achieving the purpose of the present invention.

However, the above are only examples of the present invention and should not be used to limit the scope of the present invention. All simple equivalent changes and modifications made based on the patent scope of the present invention and the content of the patent specification are still within the scope of the present invention. within the scope covered by the patent of this invention.

1: Complex programmable logic device 11. 91: Sequence transmission and reception interface 12:First multiplexer 13. 93: First control unit 14, 94: Embedded CPU 15, 95: first memory 16, 96: Second control unit 17, 97: Second memory 18, 98: Power input pin 19, 99: Specific signal pins 2:Basic input and output system 21:Receiver address decoder 22: Second multiplexer 23, 90: Third memory 24: First buffer 25: Second buffer 26:Memory controller 3: Baseboard management controller 4:Central processing unit 5:Power converter 6:Connector 7: Motherboard 71: External memory 8: High-speed interface conversion device 80: Low speed interface conversion device 9: Test host 92:Multiplexer

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, in which: Figure 1 is a block diagram illustrating a computer system of conventional technology; Figure 2 is a block diagram illustrating a first embodiment of the computer system of the present invention; and Figure 3 is a block diagram illustrating a second embodiment of the computer system of the present invention.

1: Complex programmable logic device

11: Sequence transmission and reception interface

12:First multiplexer

13:First control unit

14:Embedded CPU

15: First memory

16: Second control unit

17: Second memory

18:Power input pin

19:Specific signal pin

21:Receiver address decoder

22: Second multiplexer

23:Third memory

2:Basic input and output system

3: Baseboard management controller

4:Central processing unit

5:Power converter

6:Connector

7: Motherboard

8: High-speed interface conversion device

9: Test host

Claims (7)

A computer system suitable for a high-speed interface conversion device and a test host, and includes a complex programmable logic device (CPLD), a basic input and output system (BIOS), a baseboard management controller (BMC), and a central processing unit A complex programmable logic device containing: A sequence of transmission and reception interfaces electrically connected to the high-speed interface conversion device; a set of specific signal pins to receive a plurality of specific signals from the basic input output system, the baseboard management controller, and the central processor; A set of power input pins that receive multiple power voltage signals; A first multiplexer, including a set of output ends electrically connected to the sequence transmission interface, a set of first ends, a set of second ends electrically connected to the aforementioned set of specific signal pins to receive the specific signals, and A control terminal, and according to the signal received by the control terminal, selects the signal of the aforementioned group of first terminals or the aforementioned group of second terminals and outputs it to the aforementioned group of output terminals; an embedded central processing unit; a first memory electrically connected to the embedded central processor and used to provide the embedded central processor with access to data; A second multiplexer, including a set of first ends electrically connected to the aforementioned set of power input pins to receive the power supply voltage signals, a set of second ends electrically connected to the embedded central processor, and a control end, and a group of output terminals, and according to the signal received by the control terminal, the signal of the aforementioned group of first terminals or the aforementioned group of second terminals is selected and output to the aforementioned group of output terminals; A third memory is electrically connected to the aforementioned group of output terminals of the second multiplexer to store the data output by the aforementioned group of output terminals, and is electrically connected to the aforementioned group of first terminals of the first multiplexer, To output the stored data to the first end of the aforementioned group; A first control unit electrically connected to the serial transmission and reception interface, the control end of the first multiplexer, the control end of the second multiplexer, and the embedded central processor, and converts through the high-speed interface The device and the serial transmission interface receive a test command from the test host, The first control unit controls the first multiplexer according to the test instruction so that the specific signals are output to the test host through the first multiplexer, the serial transmission and reception interface, and the high-speed interface conversion device, or , controlling the second multiplexer and the first multiplexer so that the power supply voltage signals pass through the second multiplexer, the third memory, the first multiplexer, the serial transmission and reception interface, and the The high-speed interface conversion device outputs to the test host, or controls the embedded central processor to output the data of the first memory to the aforementioned set of second terminals of the second multiplexer, and controls the second multiplexer. The multiplexer and the first multiplexer allow the data of the first memory to pass through the second multiplexer, the third memory, the first multiplexer, the serial transmission interface, and the high-speed interface conversion device And output to the test host. The computer system of claim 1, wherein the complex programmable logic device further includes a second control unit, and a second memory electrically connected to the second control unit, and the second control unit is managed by the system The interface of the bus (SMBus) is electrically connected to the basic input and output system and the baseboard management controller to store the data of the basic input and output system and the baseboard management controller in the second memory, The second multiplexer also includes a group of third terminals electrically connected to the second control unit, and selects the aforementioned group of first terminals, the aforementioned group of second terminals, or the aforementioned group of terminals according to the signal received by the control terminal. The signal from the third terminal is combined and output to the aforementioned group of output terminals. The first control unit is also electrically connected to the second control unit, and according to the test instruction, can also control the second control unit to output the data of the second memory to the aforementioned set of third groups of the second multiplexer. terminal, and controls the second multiplexer and the first multiplexer so that the data of the second memory passes through the second multiplexer, the third memory, the first multiplexer, and the sequence interface, and the high-speed interface conversion device and output to the test host. The computer system as claimed in claim 2, wherein the central processing unit receives a set of backplane hard disk signals through a connector, and the complex programmable logic device further includes a receiver address decoder (RX address decoder), The receiver address decoder includes a set of input terminals, a set of output terminals electrically connected to the central processor through an interface of the system management bus to receive the aforementioned set of backplane hard disk signals, and a set of electrically connected to the first A control terminal of the control unit, The second multiplexer also includes a set of fourth terminals electrically connected to the aforementioned set of output terminals of the receiver address decoder, and selects the aforementioned set of first ends, the aforementioned set of output terminals according to the signal received by the control terminal. The signal from the second terminal, the aforementioned group of third terminals, or the aforementioned group of fourth terminals is output to the aforementioned group of output terminals, The first control unit is electrically connected to the receiver address decoder, and according to the test command, can also control the receiver address decoder to output the aforementioned set of backplane hard disk signals to the aforementioned set of backplane hard disk signals of the second multiplexer. This set of fourth terminals controls the second multiplexer and the first multiplexer so that the aforementioned set of backplane hard disk signals passes through the second multiplexer, the third memory, and the first multiplexer. , the serial transmission and reception interface, and the high-speed interface conversion device are output to the test host. A computer system is suitable for a high-speed interface conversion device and a test host, and includes a complex programmable logic device, an external memory, a basic input and output system, a baseboard management controller, and a central processing unit. The complex Programmable logic devices include: A sequence of transmission and reception interfaces electrically connected to the high-speed interface conversion device; a set of specific signal pins to receive a plurality of specific signals from the basic input output system, the baseboard management controller, and the central processor; A set of power input pins that receive multiple power voltage signals; A first multiplexer, including a set of output ends electrically connected to the sequence transmission interface, a set of first ends, a set of second ends electrically connected to the aforementioned set of specific signal pins to receive the specific signals, and A control terminal, and according to the signal received by the control terminal, selects the signal of the aforementioned group of first terminals or the aforementioned group of second terminals and outputs it to the aforementioned group of output terminals; a first buffer, electrically connected to the aforementioned set of power input pins to receive the power supply voltage signals, buffer them and then output them; a second buffer electrically connected to the aforementioned set of first terminals of the first multiplexer to output the received data after buffering; A memory controller is electrically connected to the first buffer, the second buffer, and the plug-in memory, and is controlled to store data from the first buffer to the plug-in memory, and to store the plug-in memory. The data stored in the memory is output to the second buffer; A first control unit is electrically connected to the serial transmission and reception interface, the control end of the first multiplexer, and the memory controller, and receives data from the test via the high-speed interface conversion device and the serial transmission and reception interface. A test command from the host, The first control unit controls the first multiplexer according to the test instruction so that the specific signals are output to the test host through the first multiplexer, the serial transmission and reception interface, and the high-speed interface conversion device, or , controlling the memory controller and the first multiplexer so that the power supply voltage signals pass through the first buffer, the memory controller, the plug-in memory, the second buffer, and the first multiplexer. , the serial transmission and reception interface, and the high-speed interface conversion device are output to the test host. The computer system as claimed in claim 4, wherein the complex programmable logic device further includes an embedded central processing unit and a first memory, the first memory is electrically connected to the embedded central processing unit and is used to provide The embedded central processing unit accesses data, The first buffer is also electrically connected to the embedded central processing unit to receive the output data and buffer it for output. The first control unit is also electrically connected to the embedded central processing unit, and according to the test instruction, also The embedded central processor can be controlled to output the data of the first memory to the first buffer, and the memory controller and the first multiplexer can be controlled to cause the data of the first memory to pass through the first buffer. The buffer, the memory controller, the plug-in memory, the second buffer, the first multiplexer, the serial transmission and reception interface, and the high-speed interface conversion device are output to the test host. The computer system as claimed in claim 5, wherein the complex programmable logic device further includes a second control unit and a second memory electrically connected to the second control unit, and the second control unit communicates through the system management The interface of the row is electrically connected to the basic input and output system and the baseboard management controller, so as to store the data of the basic input and output system and the baseboard management controller in the second memory, The first buffer is also electrically connected to the second control unit to receive the output data, and output the data after buffering. The first control unit is also electrically connected to the second control unit, and can also control according to the test command. The second control unit outputs the data of the second memory to the first buffer, and controls the memory controller and the first multiplexer so that the data of the second memory passes through the first buffer, The memory controller, the plug-in memory, the second buffer, the first multiplexer, the serial transmission and reception interface, and the high-speed interface conversion device are output to the test host. The computer system of claim 6, wherein the central processing unit receives a set of backplane hard disk signals through a connector, and the complex programmable logic device further includes a receiver address decoder, and the receiver address decoder The decoder includes a set of input terminals, a set of output terminals electrically connected to the central processor through an interface of the system management bus to receive the aforementioned set of backplane hard disk signals, and a control terminal electrically connected to the first control unit. , The first buffer is also electrically connected to the aforementioned set of output terminals of the receiver address decoder to receive the output data and buffer it for output. The first control unit is also electrically connected to the receiver address decoder. , and according to the test command, the receiver address decoder can also be controlled to output the aforementioned set of backplane hard disk signals to the first buffer, and the memory controller and the first multiplexer can be controlled to make the aforementioned The set of backplane hard disk signals passes through the first buffer, the memory controller, the plug-in memory, the second buffer, the first multiplexer, the serial transmission interface, and the high-speed interface conversion device And output to the test host.

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