TWI815725B - Computer system - Google Patents
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本發明是有關於一種電腦系統,特別是指一種具備彈性的偵錯機制的電腦系統。The present invention relates to a computer system, and in particular, to a computer system with a flexible debugging mechanism.
參閱圖1,現有的電腦系統例如是一伺服器,並適用於一低速介面轉換裝置80及一測試主機9,且包含一主板7,及設置在該主板7上的一複雜可程式邏輯裝置(CPLD)1、一基本輸入輸出系統(BIOS)2、一基板管理控制器(BMC)3,一電源轉換器(Voltage regulator)5、一中央處理器(CPU)4、與一連接器6。該複雜可程式邏輯裝置1包括一第一控制單元93、一多工器(Mux)92、一序列傳收介面91、一組電源輸入接腳98、一組特定信號接腳99、一嵌入式中央處理器(Embedded CPU)94、一第一記憶體95至一第三記憶體90、及一第二控制單元96。該測試主機9例如是一電腦主機,並以通用序列匯流排的介面而電連接該低速介面轉換裝置80。該低速介面轉換裝置80用於將積體匯流排電路(I2C)與通用序列匯流排(USB)兩種介面之間的信號作轉換與傳收。Referring to Figure 1, the existing computer system is, for example, a server and is suitable for a low-speed
該第一記憶體95是一種內部的快閃記憶體(Flash),並用於提供該嵌入式中央處理器94作資料的存取。該第二控制單元96藉由系統管理匯流排(SMBus)的介面,將來自該基本輸入輸出系統2及該基板管理控制器3的信號(如Mailbox的暫存器)儲存於該第二記憶體97,該第二記憶體97是一種內部的隨機記憶體(RAM)。該電源轉換器5用於提供在該主板7上的各個元件運作所需的各種不同電壓大小的電源。這組電源輸入接腳98及這組特定信號接腳99例如是接收該基板管理控制器3、該中央處理器4、一系統記憶體(圖未示)、及一晶片組(PCH)(圖未示)的各個電源電壓信號及各個電源重啟信號(Reset)。The
習知的該電腦系統收限於該第三記憶體90的空間大小,通常只能將這組電源輸入接腳98之其中小部分(如32根接腳)的信號在開機的過程中,將事先選定的32個電源電壓信號在邏輯0與1的時序變化儲存於該第三記憶體90中。該第一控制單元93能夠經由該低速介面轉換裝置80及該序列傳收介面91,接收來自該測試主機9的指令,以控制該多工器92選擇將該第三記憶體90所儲存的32個電源電壓信號的時序變化經由該序列傳收介面91及該低速介面轉換裝置80而輸出至該測試主機9,或者,選擇將這組特定信號接腳99之其中事先設定的部分者經由該序列傳收介面91及該低速介面轉換裝置80而即時地輸出至該測試主機9。然而,是否存有其他更具彈性的偵錯機制的電腦系統便成為一個待解決的問題。The conventional computer system is limited by the space size of the
因此,本發明的目的,即在提供一種具備彈性的偵錯機制的電腦系統。Therefore, an object of the present invention is to provide a computer system with a flexible debugging mechanism.
於是,本發明之一觀點,提供一種電腦系統,適用於一高速介面轉換裝置及一測試主機,並包含一複雜可程式邏輯裝置、一基本輸入輸出系統(BIOS)、一基板管理控制器(BMC)、及一中央處理器。該複雜可程式邏輯裝置包含一序列傳收介面、一組特定信號接腳、一組電源輸入接腳、一第一多工器、一嵌入式中央處理器、一第一記憶體、一第二多工器、一第三記憶體、及一第一控制單元。Therefore, one aspect of the present invention provides a computer system suitable for a high-speed interface conversion device and a test host, and includes a complex programmable logic device, a basic input and output system (BIOS), and a baseboard management controller (BMC). ), and a central processing unit. The complex programmable logic device includes a serial transmission interface, a set of specific signal pins, a set of power input pins, a first multiplexer, an embedded central processing unit, a first memory, a second A multiplexer, a third memory, and a first control unit.
該序列傳收介面電連接該高速介面轉換裝置。前述這組特定信號接腳接收來自該基本輸入輸出系統、該基板管理控制器、及該中央處理器的多個特定信號。前述這組電源輸入接腳接收多個電源電壓信號。該第一多工器包括電連接該序列傳收介面的一組輸出端、一組第一端、電連接前述這組特定信號接腳以接收該等特定信號的一組第二端、及一控制端,並根據該控制端所接收的信號以選擇前述這組第一端或前述這組第二端的信號而輸出至前述這組輸出端。The serial transmission and reception interface is electrically connected to the high-speed interface conversion device. The aforementioned set of specific signal pins receives a plurality of specific signals from the basic input output system, the baseboard management controller, and the central processing unit. The aforementioned set of power input pins receives multiple power voltage signals. The first multiplexer includes a set of output ends electrically connected to the sequence transmission interface, a set of first ends, a set of second ends electrically connected to the set of specific signal pins to receive the specific signals, and a set of The control end selects the signal of the aforementioned set of first ends or the aforementioned set of second ends according to the signal received by the control end and outputs it to the aforementioned set of output ends.
該第一記憶體電連接該嵌入式中央處理器,並用於提供該嵌入式中央處理器存取資料。該第二多工器包括電連接前述這組電源輸入接腳以接收該等電源電壓信號的一組第一端、電連接該嵌入式中央處理器的一組第二端、一控制端、及一組輸出端,並根據該控制端所接收的信號以選擇前述這組第一端或前述這組第二端的信號而輸出至前述這組輸出端。該第三記憶體電連接該第二多工器的前述這組輸出端,以儲存前述這組輸出端所輸出的資料,並電連接該第一多工器的前述這組第一端,以輸出所儲存的資料至前述這組第一端。The first memory is electrically connected to the embedded CPU and used to provide the embedded CPU with access to data. The second multiplexer includes a set of first ends electrically connected to the aforementioned set of power input pins to receive the power supply voltage signals, a set of second ends electrically connected to the embedded CPU, a control end, and A group of output terminals, and according to the signal received by the control terminal, the signal of the aforementioned group of first terminals or the aforementioned group of second terminals is selected and output to the aforementioned group of output terminals. The third memory is electrically connected to the aforementioned set of output terminals of the second multiplexer to store the data output by the aforementioned set of output terminals, and is electrically connected to the aforementioned set of first terminals of the first multiplexer to store the data output by the aforementioned set of output terminals. Output the stored data to the first end of the aforementioned group.
該第一控制單元電連接該序列傳收介面、該第一多工器的該控制端、該第二多工器的該控制端、及該嵌入式中央處理器,並經由該高速介面轉換裝置及該序列傳收介面,接收來自該測試主機的一測試指令。The first control unit is electrically connected to the serial transmission and reception interface, the control end of the first multiplexer, the control end of the second multiplexer, and the embedded central processor, and passes through the high-speed interface conversion device and the sequence transmission and reception interface receives a test command from the test host.
該第一控制單元根據該測試指令,控制該第一多工器使得該等特定信號經由該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機,或者,控制該第二多工器及該第一多工器使得該等電源電壓信號經由該第二多工器、該第三記憶體、該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機,或者,控制該嵌入式中央處理器將該第一記憶體的資料輸出至該第二多工器的前述這組第二端,並控制該第二多工器及該第一多工器使得該第一記憶體的資料經由該第二多工器、該第三記憶體、該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機。The first control unit controls the first multiplexer according to the test instruction so that the specific signals are output to the test host through the first multiplexer, the serial transmission and reception interface, and the high-speed interface conversion device, or , controlling the second multiplexer and the first multiplexer so that the power supply voltage signals pass through the second multiplexer, the third memory, the first multiplexer, the serial transmission and reception interface, and the The high-speed interface conversion device outputs to the test host, or controls the embedded central processor to output the data of the first memory to the aforementioned set of second terminals of the second multiplexer, and controls the second multiplexer. The multiplexer and the first multiplexer allow the data of the first memory to pass through the second multiplexer, the third memory, the first multiplexer, the serial transmission interface, and the high-speed interface conversion device And output to the test host.
在一些實施態樣中,其中,該複雜可程式邏輯裝置還包含一第二控制單元,及電連接該第二控制單元的一第二記憶體。該第二控制單元藉由系統管理匯流排的介面電連接該基本輸入輸出系統及該基板管理控制器,以將對應該基本輸入輸出系統及該基板管理控制器的資料儲存於該第二記憶體。In some implementations, the complex programmable logic device further includes a second control unit, and a second memory electrically connected to the second control unit. The second control unit is electrically connected to the basic input output system and the baseboard management controller through the interface of the system management bus, so as to store the data of the basic input output system and the baseboard management controller in the second memory. .
該第二多工器還包括電連接該第二控制單元的一組第三端,並根據該控制端所接收的信號以選擇前述這組第一端、前述這組第二端、或前述這組第三端的信號而輸出至前述這組輸出端。The second multiplexer also includes a group of third terminals electrically connected to the second control unit, and selects the aforementioned group of first terminals, the aforementioned group of second terminals, or the aforementioned group of terminals according to the signal received by the control terminal. The signal of the third terminal is grouped and output to the aforementioned group of output terminals.
該第一控制單元還電連接該第二控制單元,並根據該測試指令,還能夠控制該第二控制單元將該第二記憶體的資料輸出至該第二多工器的前述這組第三端,並控制該第二多工器及該第一多工器使得該第二記憶體的資料經由該第二多工器、該第三記憶體、該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機。The first control unit is also electrically connected to the second control unit, and according to the test instruction, can also control the second control unit to output the data of the second memory to the aforementioned set of third groups of the second multiplexer. terminal, and controls the second multiplexer and the first multiplexer so that the data of the second memory passes through the second multiplexer, the third memory, the first multiplexer, and the sequence interface, and the high-speed interface conversion device and output to the test host.
在一些實施態樣中,其中,該中央處理器經由一連接器接收一組背板硬碟信號。該複雜可程式邏輯裝置還包含一接收器位址解碼器,該接收器位址解碼器包括藉由系統管理匯流排的介面電連接該中央處理器以接收前述這組背板硬碟信號的一組輸入端、一組輸出端、及電連接該第一控制單元的一控制端。In some implementations, the CPU receives a set of backplane hard drive signals via a connector. The complex programmable logic device also includes a receiver address decoder. The receiver address decoder includes a device electrically connected to the CPU through an interface of the system management bus to receive the aforementioned set of backplane hard disk signals. A set of input terminals, a set of output terminals, and a control terminal electrically connected to the first control unit.
該第二多工器還包括電連接該接收器位址解碼器的前述這組輸出端的一組第四端,並根據該控制端所接收的信號以選擇前述這組第一端、前述這組第二端、前述這組第三端、或前述這組第四端的信號而輸出至前述這組輸出端。The second multiplexer also includes a set of fourth terminals electrically connected to the aforementioned set of output terminals of the receiver address decoder, and selects the aforementioned set of first ends, the aforementioned set of output terminals according to the signal received by the control terminal. The signals from the second terminal, the aforementioned group of third terminals, or the aforementioned group of fourth terminals are output to the aforementioned group of output terminals.
該第一控制單元電連接該接收器位址解碼器,並根據該測試指令,還能夠控制該接收器位址解碼器將前述這組背板硬碟信號輸出至該第二多工器的前述這組第四端,並控制該第二多工器及該第一多工器使得前述這組背板硬碟信號經由該第二多工器、該第三記憶體、該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機。The first control unit is electrically connected to the receiver address decoder, and according to the test command, can also control the receiver address decoder to output the aforementioned set of backplane hard disk signals to the aforementioned set of backplane hard disk signals of the second multiplexer. This set of fourth terminals controls the second multiplexer and the first multiplexer so that the aforementioned set of backplane hard disk signals passes through the second multiplexer, the third memory, and the first multiplexer. , the serial transmission and reception interface, and the high-speed interface conversion device are output to the test host.
於是,本發明之另一觀點,提供一種電腦系統,適用於一高速介面轉換裝置及一測試主機,並包含一複雜可程式邏輯裝置、一外掛記憶體、一基本輸入輸出系統、一基板管理控制器、及一中央處理器。該複雜可程式邏輯裝置包含一序列傳收介面、一組特定信號接腳、一組電源輸入接腳、一第一多工器、一嵌入式中央處理器、一第一緩衝器、一第二緩衝器、一記憶體控制器、及一第一控制單元。Therefore, another aspect of the present invention provides a computer system suitable for a high-speed interface conversion device and a test host, and includes a complex programmable logic device, an external memory, a basic input and output system, and a substrate management control device, and a central processing unit. The complex programmable logic device includes a serial transmission interface, a set of specific signal pins, a set of power input pins, a first multiplexer, an embedded central processing unit, a first buffer, and a second buffer, a memory controller, and a first control unit.
該序列傳收介面電連接該高速介面轉換裝置。前述這組特定信號接腳接收來自該基本輸入輸出系統、該基板管理控制器、及該中央處理器的多個特定信號。前述這組電源輸入接腳接收多個電源電壓信號。該第一多工器包括電連接該序列傳收介面的一組輸出端、一組第一端、電連接前述這組特定信號接腳以接收該等特定信號的一組第二端、及一控制端,並根據該控制端所接收的信號以選擇前述這組第一端或前述這組第二端的信號而輸出至前述這組輸出端。The serial transmission and reception interface is electrically connected to the high-speed interface conversion device. The aforementioned set of specific signal pins receives a plurality of specific signals from the basic input output system, the baseboard management controller, and the central processing unit. The aforementioned set of power input pins receives multiple power voltage signals. The first multiplexer includes a set of output ends electrically connected to the sequence transmission interface, a set of first ends, a set of second ends electrically connected to the set of specific signal pins to receive the specific signals, and a set of The control end selects the signal of the aforementioned set of first ends or the aforementioned set of second ends according to the signal received by the control end and outputs it to the aforementioned set of output ends.
該第一緩衝器電連接前述這組電源輸入接腳以接收該等電源電壓信號,且作緩衝後而輸出。該第二緩衝器電連接該第一多工器的前述這組第一端以在作緩衝後而輸出所接收的資料。該記憶體控制器電連接該第一緩衝器、該第二緩衝器、及該外掛記憶體,並受控制以將來自該第一緩衝器的資料儲存至該外掛記憶體,及將該外掛記憶體所儲存的資料輸出至該第二緩衝器。The first buffer is electrically connected to the aforementioned set of power input pins to receive the power voltage signals, buffer them and then output them. The second buffer is electrically connected to the aforementioned set of first terminals of the first multiplexer to output the received data after buffering. The memory controller is electrically connected to the first buffer, the second buffer, and the plug-in memory, and is controlled to store data from the first buffer to the plug-in memory, and to store data from the plug-in memory. The data stored in the body is output to the second buffer.
第一控制單元電連接該序列傳收介面、該第一多工器的該控制端、及該記憶體控制器,並經由該高速介面轉換裝置及該序列傳收介面,接收來自該測試主機的一測試指令。The first control unit is electrically connected to the serial transmission and reception interface, the control end of the first multiplexer, and the memory controller, and receives data from the test host through the high-speed interface conversion device and the serial transmission and reception interface. A test command.
該第一控制單元根據該測試指令控制該第一多工器使得該等特定信號經由該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機,或者,控制該記憶體控制器及該第一多工器使得該等電源電壓信號經由該第一緩衝器、該記憶體控制器、該外掛記憶體、該第二緩衝器、該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機。The first control unit controls the first multiplexer according to the test command so that the specific signals are output to the test host through the first multiplexer, the serial transmission and reception interface, and the high-speed interface conversion device, or, The memory controller and the first multiplexer are controlled so that the power supply voltage signals pass through the first buffer, the memory controller, the plug-in memory, the second buffer, the first multiplexer, The serial transmission and reception interface and the high-speed interface conversion device are output to the test host.
在一些實施態樣中,其中,該複雜可程式邏輯裝置還包含一嵌入式中央處理器及一第一記憶體,該第一記憶體電連接該嵌入式中央處理器,並用於提供該嵌入式中央處理器存取資料。In some implementations, the complex programmable logic device further includes an embedded central processing unit and a first memory. The first memory is electrically connected to the embedded central processing unit and is used to provide the embedded central processing unit. The central processing unit accesses data.
該第一緩衝器還電連接該嵌入式中央處理器以接收所輸出的資料,且作緩衝後而輸出。該第一控制單元還電連接該嵌入式中央處理器,並根據該測試指令,還能夠控制該嵌入式中央處理器將該第一記憶體的資料輸出至該第一緩衝器,並控制該記憶體控制器及該第一多工器使得該第一記憶體的資料經由該第一緩衝器、該記憶體控制器、該外掛記憶體、該第二緩衝器、該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機。The first buffer is also electrically connected to the embedded CPU to receive the output data, buffer it and then output it. The first control unit is also electrically connected to the embedded central processor, and according to the test instruction, can also control the embedded central processor to output the data of the first memory to the first buffer, and control the memory The bank controller and the first multiplexer cause the data of the first memory to pass through the first buffer, the memory controller, the plug-in memory, the second buffer, the first multiplexer, the The serial transmission and reception interface and the high-speed interface conversion device are output to the test host.
在一些實施態樣中,其中,該複雜可程式邏輯裝置還包含一第二控制單元及電連接該第二控制單元的一第二記憶體。該第二控制單元藉由系統管理匯流排的介面電連接該基本輸入輸出系統及該基板管理控制器,以將對應該基本輸入輸出系統及該基板管理控制器的資料儲存於該第二記憶體。In some implementations, the complex programmable logic device further includes a second control unit and a second memory electrically connected to the second control unit. The second control unit is electrically connected to the basic input output system and the baseboard management controller through the interface of the system management bus, so as to store the data of the basic input output system and the baseboard management controller in the second memory. .
該第一緩衝器還電連接該第二控制單元以接收所輸出的資料,且作緩衝後而輸出。該第一控制單元還電連接該第二控制單元,並根據該測試指令,還能夠控制該第二控制單元將該第二記憶體的資料輸出至該第一緩衝器,並控制該記憶體控制器及該第一多工器使得該第二記憶體的資料經由該第一緩衝器、該記憶體控制器、該外掛記憶體、該第二緩衝器、該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機。The first buffer is also electrically connected to the second control unit to receive the output data, buffer it and then output it. The first control unit is also electrically connected to the second control unit, and according to the test instruction, can also control the second control unit to output the data of the second memory to the first buffer, and control the memory control The controller and the first multiplexer allow the data of the second memory to pass through the first buffer, the memory controller, the plug-in memory, the second buffer, the first multiplexer, and the serial transmitter. The receiving interface and the high-speed interface conversion device output to the test host.
在一些實施態樣中,其中,該中央處理器經由一連接器接收一組背板硬碟信號。該複雜可程式邏輯裝置還包含一接收器位址解碼器,該接收器位址解碼器包括藉由系統管理匯流排的介面電連接該中央處理器以接收前述這組背板硬碟信號的一組輸入端、一組輸出端、及電連接該第一控制單元的一控制端。In some implementations, the CPU receives a set of backplane hard drive signals via a connector. The complex programmable logic device also includes a receiver address decoder. The receiver address decoder includes a device electrically connected to the CPU through an interface of the system management bus to receive the aforementioned set of backplane hard disk signals. A set of input terminals, a set of output terminals, and a control terminal electrically connected to the first control unit.
該第一緩衝器還電連接該接收器位址解碼器的前述這組輸出端以接收所輸出的資料,且作緩衝後而輸出。該第一控制單元還電連接該接收器位址解碼器,並根據該測試指令,還能夠控制該接收器位址解碼器將前述這組背板硬碟信號輸出至該第一緩衝器,並控制該記憶體控制器及該第一多工器使得前述這組背板硬碟信號經由該第一緩衝器、該記憶體控制器、該外掛記憶體、該第二緩衝器、該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機。The first buffer is also electrically connected to the aforementioned set of output terminals of the receiver address decoder to receive the output data, buffer it and then output it. The first control unit is also electrically connected to the receiver address decoder, and according to the test instruction, can also control the receiver address decoder to output the aforementioned set of backplane hard disk signals to the first buffer, and The memory controller and the first multiplexer are controlled so that the aforementioned set of backplane hard disk signals passes through the first buffer, the memory controller, the plug-in memory, the second buffer, and the first multiplexer. The processor, the serial transmission and reception interface, and the high-speed interface conversion device are output to the test host.
本發明的功效在於:藉由該第一控制單元控制該第二多工器及該嵌入式中央處理器,選擇該嵌入式中央處理器儲存於該第一記憶體的資料或前述這組電源輸入接腳所接收的該等電源電壓信號,輸出至該第一多工器,並控制該第一控制器,選擇該第一記憶體的資料、該等電源電壓信號、或前述這組特定信號接腳所接收的該等特定信號,以經由該高速介面轉換裝置而能夠即時地輸出至該測試主機,故能實現一種更具彈性的偵錯機制。The effect of the present invention is to control the second multiplexer and the embedded central processor through the first control unit, and select the data stored in the first memory by the embedded central processor or the aforementioned set of power inputs. The power supply voltage signals received by the pins are output to the first multiplexer and control the first controller to select the data of the first memory, the power supply voltage signals, or the aforementioned set of specific signal connections. The specific signals received by the pins can be output to the test host in real time through the high-speed interface conversion device, so a more flexible debugging mechanism can be implemented.
在本發明被詳細描述之前,應當注意在以下的說明內容中,類似的元件是以相同的編號來表示。Before the present invention is described in detail, it should be noted that in the following description, similar elements are designated with the same numbering.
參閱圖2,本發明電腦系統之一第一實施例,適用於一高速介面轉換裝置8及一測試主機9,並包含一主板7,及設置在該主板7上的一複雜可程式邏輯裝置(CPLD)1、一基本輸入輸出系統(BIOS)2、一基板管理控制器(BMC)3、一中央處理器(CPU)4、一電源轉換器(Voltage regulator)5、及一連接器6。該測試主機9例如是一電腦主機,並以通用序列匯流排(USB)的介面而電連接該高速介面轉換裝置8。該高速介面轉換裝置8例如以序列周邊介面(SPI)而電連接該複雜可程式邏輯裝置1,並用於提供通用序列匯流排與序列周邊介面之間的信號轉換。該電源轉換器5用於將來自一電源供應器的多種電壓作穩壓後而輸出成多個電源電壓信號,以作為該基本輸入輸出系統2、該基板管理控制器3、該中央處理器4、及一晶片組等各個元件運作所需的電力。Referring to Figure 2, a first embodiment of the computer system of the present invention is suitable for a high-speed interface conversion device 8 and a test host 9, and includes a
該複雜可程式邏輯裝置1包含一序列傳收介面11、一組特定信號接腳19、一組電源輸入接腳18、一第一多工器(MUX)12、一第一控制單元13、一嵌入式中央處理器14、一第一記憶體15、一第二控制單元16、一第二記憶體17、一第二多工器22、一第三記憶體23、及一接收器位址解碼器(RX address decoder)21。The complex programmable logic device 1 includes a
該嵌入式中央處理器14電連接該第一記憶體15,並至少用於執行一種PFR(Platform firmware resilience)機制。該第一記憶體15是一種內部的快閃記憶體(Flash),並用於提供該嵌入式中央處理器14存取資料。該第二控制單元16電連接該嵌入式中央處理器14,並藉由系統管理匯流排(SMBus)的介面而電連接該基本輸入輸出系統2及該基板管理控制器3,以將對應該基本輸入輸出系統2及該基板管理控制器3的資料(如對應Mailbox的暫存器的數值)儲存於該第二記憶體17,該第二記憶體17是一種內部的隨機記憶體(RAM),並還能夠用於提供該基板管理控制器3寫入資料(如更新該基本輸入輸出系統2、該基板管理控制器3、與該複雜可程式邏輯裝置1的升級版本),及提供該複雜可程式邏輯裝置1寫入資料。The embedded
前述這組特定信號接腳19例如是接收來自該基本輸入輸出系統2、該基板管理控制器3、該中央處理器4、或還有其他元件的多個特定信號,如多個電源重啟信號(Reset)。前述這組電源輸入接腳18接收該等電源電壓信號。The aforementioned set of specific signal pins 19 receives, for example, multiple specific signals from the basic input and
該中央處理器4經由該連接器6接收來自一背板的一組背板硬碟信號,前述這組背板硬碟信號用於多個硬碟的狀態。該接收器位址解碼器21包括藉由系統管理匯流排的介面而電連接該中央處理器4以接收前述這組背板硬碟信號的一組輸入端、一組輸出端、及電連接該第一控制單元13的一控制端,並根據該控制端所接收的信號,選擇前述這組輸入端的信號之其中對應者而輸出至前述這組輸出端。The CPU 4 receives a set of backplane hard disk signals from a backplane via the connector 6, and the aforementioned set of backplane hard disk signals is used for the status of multiple hard disks. The
該第二多工器22包括電連接前述這組電源輸入接腳18以接收該等電源電壓信號的一組第一端、電連接該嵌入式中央處理器14的一組第二端、電連接該第二控制單元16的一組第三端、電連接該接收器位址解碼器21的前述這組輸出端的一組第四端、電連接該第一控制單元13的一控制端、及電連接該第三記憶體23的一組輸出端,並根據該控制端所接收的信號以選擇前述這組第一端、前述這組第二端、前述這組第三端、或前述這組第四端的信號而輸出至前述這組輸出端。The
該第一多工器12包括一組輸出端、一組第一端、電連接前述這組特定信號接腳19以接收該等特定信號的一組第二端、及電連接該第一控制單元13的一控制端,並根據該控制端所接收的信號以選擇前述這組第一端或前述這組第二端的信號而輸出至前述這組輸出端。該第三記憶體23電連接該第二多工器22的前述這組輸出端,以儲存該第二多工器22的前述這組輸出端所輸出的資料,並電連接該第一多工器12的前述這組第一端,以輸出所儲存的資料至該第一多工器12的前述這組第一端。該序列傳收介面11電連接該高速介面轉換裝置8、電連接該序列傳收介面11的前述這組輸出端、及該第一控制單元13。The
該第一控制單元13還電連接該嵌入式中央處理器14及該第二控制單元16,並經由該序列傳收介面11及該高速介面轉換裝置8,接收來自該測試主機9的一測試指令。The
該第一控制單元13根據該測試指令,能夠控制該第一多工器12使得該等特定信號經由該第一多工器12、該序列傳收介面11、及該高速介面轉換裝置8而即時地輸出至該測試主機9。或者,該第一控制單元13根據該測試指令,能夠控制該第二多工器22及該第一多工器12使得該等電源電壓信號經由該第二多工器22儲存至該第三記憶體23,再經由該第一多工器12、該序列傳收介面11、及該高速介面轉換裝置8而輸出至該測試主機9。The
或者,該第一控制單元13根據該測試指令,能夠控制該嵌入式中央處理器14將該第一記憶體15的資料輸出至該第二多工器22的前述這組第二端,並控制該第二多工器22及該第一多工器12使得該第一記憶體15的資料經由該第二多工器22儲存至該第三記憶體23,再經由該第一多工器12、該序列傳收介面11、及該高速介面轉換裝置8而輸出至該測試主機9。Alternatively, the
或者,該第一控制單元13根據該測試指令,能夠控制該第二控制單元16將該第二記憶體17的資料輸出至該第二多工器22的前述這組第三端,並控制該第二多工器22及該第一多工器12使得該第二記憶體17的資料經由該第二多工器22儲存至該第三記憶體23,再經由該第一多工器12、該序列傳收介面11、及該高速介面轉換裝置8而輸出至該測試主機9。Alternatively, the
或者,該第一控制單元13根據該測試指令,能夠控制該接收器位址解碼器21將前述這組背板硬碟信號輸出至該第二多工器22的前述這組第四端,並控制該第二多工器22及該第一多工器12使得前述這組背板硬碟信號經由該第二多工器22儲存至該第三記憶體23,再經由該第一多工器12、該序列傳收介面11、及該高速介面轉換裝置8而輸出至該測試主機9。Alternatively, the
也就是說,在該第三記憶體23的儲存空間有限的情況下,該第三記憶體23能夠完整記錄資料量較小的該等電源電壓信號、該第一記憶體15的資料、該第二記憶體17的資料、或該等背板硬碟信號,如電壓對應邏輯0與1的時序變化情形。相反地,對於資料量較大而無法完整儲存於該第三記憶體23的該等特定信號,則藉由該高速介面轉換裝置8而能夠即時地輸出至該測試主機9。That is to say, when the storage space of the
參閱圖3,本發明電腦系統之一第二實施例,部分元件的功能與該第一實施例相同,不同的地方在於:該電腦系統還包含一外掛記憶體71,且該複雜可程式邏輯裝置省略該第二多工器22及該第三記憶體23,並還包含一第一緩衝器(Buffer)24、一第二緩衝器25、及一記憶體控制器(Memory controller)26。Referring to Figure 3, a second embodiment of the computer system of the present invention is shown. The functions of some components are the same as those of the first embodiment. The difference is that the computer system also includes an
該第一緩衝器24電連接前述這組電源輸入接腳、該嵌入式中央處理器、該第二控制單元、該接收器位址解碼器的前述這組輸出端、及該記憶體控制器26,以能夠接收該等電源電壓信號、該第一記憶體的資料、該第二記憶體的資料、及前述這組背板硬碟信號,且在作緩衝後而輸出至該記憶體控制器26。The
該第二緩衝器25電連接該記憶體控制器26,及該第一多工器的前述這組第一端,以將來自該記憶體控制器26的資料在作緩衝後而輸出至該第一多工器的前述這組第一端。The
該記憶體控制器26還電連接該外掛記憶體71及該第一控制單元,並受該第一控制單元的控制以將來自該第一緩衝器24的資料儲存至該外掛記憶體71,及將該外掛記憶體71所儲存的資料輸出至該第二緩衝器25。The
該第一控制單元根據該測試指令,能夠控制該第一多工器使得該等特定信號經由該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機,或者,該第一控制單元根據該測試指令,能夠控制該記憶體控制器26及該第一多工器使得該等電源電壓信號經由該第一緩衝器24及該記憶體控制器26而儲存至該外掛記憶體71,再經由該記憶體控制器26、該第二緩衝器25、該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機。The first control unit can control the first multiplexer according to the test command so that the specific signals are output to the test host through the first multiplexer, the serial transmission and reception interface, and the high-speed interface conversion device, Alternatively, the first control unit can control the
或者,該第一控制單元根據該測試指令,能夠控制該嵌入式中央處理器將該第一記憶體的資料輸出至該第一緩衝器24,並控制該記憶體控制器26及該第一多工器使得該第一記憶體的資料經由該第一緩衝器24及該記憶體控制器26而儲存至該外掛記憶體71,再經由該記憶體控制器26、該第二緩衝器25、該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機。Alternatively, the first control unit can control the embedded central processor to output the data of the first memory to the
或者,該第一控制單元根據該測試指令,能夠該第二控制單元將該第二記憶體的資料輸出至該第一緩衝器24,並控制該記憶體控制器26及該第一多工器使得該第二記憶體的資料經由該第一緩衝器24及該記憶體控制器26而儲存至該外掛記憶體71,再經由該外掛記憶體71、該第二緩衝器25、該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機。Alternatively, the first control unit can enable the second control unit to output the data of the second memory to the
或者,該第一控制單元根據該測試指令,能夠控制該接收器位址解碼器將前述這組背板硬碟信號輸出至該第一緩衝器24,並控制該記憶體控制器26及該第一多工器使得前述這組背板硬碟信號經由該第一緩衝器24及該記憶體控制器26而儲存至該外掛記憶體71,再經由該外掛記憶體71、該第二緩衝器25、該第一多工器、該序列傳收介面、及該高速介面轉換裝置而輸出至該測試主機。Alternatively, the first control unit can control the receiver address decoder to output the aforementioned set of backplane hard disk signals to the
換句話說,該第二實施例藉由該外掛記憶體71的儲存空間能夠大於該複雜可程式邏輯裝置的該第三記憶體23,因而能夠將工程人員想要觀察的各種信號或資料作完整的儲存與記錄,進而再輸出至該測試主機,以提供偵錯使用。In other words, in the second embodiment, the storage space of the
綜上所述,相較於圖1所示的先前技術具有記憶體能存放資料的空間有限、可偵錯的部分僅有主板開機時序與主板已開機後的複雜可程式邏輯裝置的腳位狀態,本案藉由該電腦系統的該複雜可程式邏輯裝置作不同硬體與軟體的編排與設計,或再加上該外掛記憶體71的使用,能夠偵錯的態樣大幅地增加,如主板開機時序與主板已開機後的複雜可程式邏輯裝置的腳位狀態、背板硬碟信號、內部的快閃記憶體(如第一記憶體)的資料狀態、基板管理控制器與基本輸入輸出系統的資料狀態,因而實現一種更具彈性的偵錯機制,故確實能達成本發明的目的。To sum up, compared with the previous technology shown in Figure 1, the memory space for storing data is limited, and the only parts that can be debugged are the motherboard boot sequence and the pin status of the complex programmable logic device after the motherboard is powered on. In this case, through the arrangement and design of different hardware and software of the complex programmable logic device of the computer system, or coupled with the use of the plug-in
惟以上所述者,僅為本發明的實施例而已,當不能以此限定本發明實施的範圍,凡是依本發明申請專利範圍及專利說明書內容所作的簡單的等效變化與修飾,皆仍屬本發明專利涵蓋的範圍內。However, the above are only examples of the present invention and should not be used to limit the scope of the present invention. All simple equivalent changes and modifications made based on the patent scope of the present invention and the content of the patent specification are still within the scope of the present invention. within the scope covered by the patent of this invention.
1:複雜可程式邏輯裝置
11、91:序列傳收介面
12:第一多工器
13、93:第一控制單元
14、94:嵌入式中央處理器
15、95:第一記憶體
16、96:第二控制單元
17、97:第二記憶體
18、98:電源輸入接腳
19、99:特定信號接腳
2:基本輸入輸出系統
21:接收器位址解碼器
22:第二多工器
23、90:第三記憶體
24:第一緩衝器
25:第二緩衝器
26:記憶體控制器
3:基板管理控制器
4:中央處理器
5:電源轉換器
6:連接器
7:主板
71:外掛記憶體
8:高速介面轉換裝置
80:低速介面轉換裝置
9:測試主機
92:多工器1: Complex
本發明的其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中: 圖1是一方塊圖,說明習知技術的一種電腦系統; 圖2是一方塊圖,說明本發明電腦系統的一第一實施例;及 圖3是一方塊圖,說明本發明電腦系統的一第二實施例。 Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, in which: Figure 1 is a block diagram illustrating a computer system of conventional technology; Figure 2 is a block diagram illustrating a first embodiment of the computer system of the present invention; and Figure 3 is a block diagram illustrating a second embodiment of the computer system of the present invention.
1:複雜可程式邏輯裝置 1: Complex programmable logic device
11:序列傳收介面 11: Sequence transmission and reception interface
12:第一多工器 12:First multiplexer
13:第一控制單元 13:First control unit
14:嵌入式中央處理器 14:Embedded CPU
15:第一記憶體 15: First memory
16:第二控制單元 16: Second control unit
17:第二記憶體 17: Second memory
18:電源輸入接腳 18:Power input pin
19:特定信號接腳 19:Specific signal pin
21:接收器位址解碼器 21:Receiver address decoder
22:第二多工器 22: Second multiplexer
23:第三記憶體 23:Third memory
2:基本輸入輸出系統 2:Basic input and output system
3:基板管理控制器 3: Baseboard management controller
4:中央處理器 4:Central processing unit
5:電源轉換器 5:Power converter
6:連接器 6:Connector
7:主板 7: Motherboard
8:高速介面轉換裝置 8: High-speed interface conversion device
9:測試主機 9: Test host
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CN111026588A (en) * | 2018-10-09 | 2020-04-17 | 美超微电脑股份有限公司 | Computer system and method for testing a computer system |
CN112579178A (en) * | 2019-09-29 | 2021-03-30 | 佛山市顺德区顺达电脑厂有限公司 | Debugging system for boot program, and host and method thereof |
TWI726405B (en) * | 2019-09-04 | 2021-05-01 | 神雲科技股份有限公司 | Boot procedure debugging system, host and method thereof |
TWI771952B (en) * | 2021-03-16 | 2022-07-21 | 英業達股份有限公司 | Server system with baseboard management controller to update firmware |
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Patent Citations (5)
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CN111026588A (en) * | 2018-10-09 | 2020-04-17 | 美超微电脑股份有限公司 | Computer system and method for testing a computer system |
US11119876B2 (en) * | 2018-10-09 | 2021-09-14 | Super Micro Computer, Inc. | Device and method for testing computer system |
TWI726405B (en) * | 2019-09-04 | 2021-05-01 | 神雲科技股份有限公司 | Boot procedure debugging system, host and method thereof |
CN112579178A (en) * | 2019-09-29 | 2021-03-30 | 佛山市顺德区顺达电脑厂有限公司 | Debugging system for boot program, and host and method thereof |
TWI771952B (en) * | 2021-03-16 | 2022-07-21 | 英業達股份有限公司 | Server system with baseboard management controller to update firmware |
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