CN112564864B - ARINC818 bus link rate automatic adaption method - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/234—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
- H04N21/2343—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
- H04N21/234363—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements by altering the spatial resolution, e.g. for clients with a lower screen resolution
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/234—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
- H04N21/2343—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
- H04N21/234381—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements by altering the temporal resolution, e.g. decreasing the frame rate by frame skipping
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
- H04N21/440263—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the spatial resolution, e.g. for displaying on a connected PDA
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
- H04N21/440281—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the temporal resolution, e.g. by frame skipping
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
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Abstract
The invention provides a method for automatically adapting ARINC818 bus link rate, which comprises three parts, namely high-speed serial transceiver link rate dynamic reconfiguration, high-speed serial transceiver link rate polling and ARINC818 protocol end line rate reconfiguration, wherein the method for dynamically reconfiguring the high-speed serial transceiver link rate is used at a receiving end to realize rate handshake with a transmitting end, the matching process uses a line rate polling mode to carry out polling of different line rates at intervals, and the link rate of the current transmitting end is determined by judging link handshake state so as to realize link rate matching with the transmitting end. The ARINC818 bus link rate automatic adaption method based on the FPGA high-speed serial transceiver can realize the self-adaption receiving and sending of various resolution videos through the ARINC818 bus, and compared with the design of a single link rate, the method can meet the requirements of self-adaption transmission of various resolution videos.
Description
Technical Field
The invention relates to the technical field of aviation video buses, in particular to an ARINC818 bus link rate automatic adaptation method based on an FPGA high-speed serial transceiver.
Background
The avionic digital video bus (ADVB, also called ARINC 818) is an avionic video transmission standard formulated based on the FC-AV standard, which enables transmission and exchange of video stream data in a fiber optic network, specifying mapping rules between video streams and FC frames. The ADVB protocol allows link rates of 1.0625Gbps,2.125Gbps, 3.1875Gbps, 4.25Gbps, etc. The link rate of the optical fiber channel matched with the video data is selected according to the format of the transmitted video data, so that the maximization of the link utilization rate can be ensured, the bandwidth loss is reduced, and the cost is reduced.
The ARINC818 video bus technology is a mainstream technology of a novel avionics video system due to the unique technical advantages. The ARINC818 bus technology is deeply researched and developed, and has profound significance for the technical development of the military and commercial avionics video fields in China. Therefore, we propose an automatic adaptation method for the ARINC818 bus link rate based on the FPGA high-speed serial transceiver.
Disclosure of Invention
The invention aims to provide a method for automatically adapting the ARINC818 bus link rate based on an FPGA high-speed serial transceiver, which is used for solving the problems that the link utilization rate is maximized, the bandwidth loss is reduced and the cost is reduced only by selecting the link rate of a fiber channel matched with the FPGA high-speed serial transceiver according to the format of transmitted video data, which is proposed by the background art.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a method for automatically adapting ARINC818 bus link rate is based on an FPGA high-speed serial transceiver, and comprises three parts of dynamic reconfiguration of the link rate of the FPGA high-speed serial transceiver, link rate polling of the high-speed serial transceiver, and line rate reconfiguration of an ARINC818 protocol end.
Preferably, the high-speed serial transceiver link rate dynamic reconfiguration: the method mainly aims at an XILINX high-speed serial communication interface IP, a receiving end can configure the high-speed serial transceiver into four ARINC818 link rates of 1.0625Gbps,2.125Gbps, 3.1875Gbps and 4.25Gbps respectively through parameter configuration, and the XILINX high-speed serial transceiver IP can reconfigure the internal PLL coefficients through a dynamic reconfiguration interface so as to reconfigure the link rates of the high-speed transceiver ports.
Preferably, the FPGA high-speed serial transceiver has the IP provided configurable PLL coefficient and link line rate calculation relation as follows
Wherein the method comprises the steps off PLLClkin As an external reference clock to which the reference clock is to be applied,f PLLClkout for the PLL clock output,f LineRate is the link rate of the high-speed serial transceiver.
Preferably, the link rate polling method of the FPGA high-speed serial transceiver comprises the following steps: and judging whether the line rates of the receiving end and the transmitting end are consistent by monitoring the link state returned by the high-speed serial transceiver, if not, changing the line rate of the high-speed serial transceiver through parameter configuration, judging again until the line rates of the receiving end and the transmitting end are consistent, and finally feeding back the scanning result to the ARINC818 protocol end.
Preferably, the implementation steps of the line rate adaptive scan are as follows:
the first step: first, the high-speed serial transceiver line rate is configured to 1.0625Gbps;
and a second step of: monitoring the link state of the high-speed serial transceiver after waiting for a period of time, if the state returns to be successful handshake, executing the fourth step, otherwise executing the third step;
and a third step of: reconfiguring the high-speed serial transceiver line rate to other line rates, such as 2.125Gbps, 3.1875Gbps, 4.25gbpsarinc818 link rate, performing a second step;
fourth step: detecting and acquiring the current line rate, fixing the configuration parameter information of the current high-speed serial transceiver IP, and exiting the link rate polling state of the high-speed serial transceiver;
fifth step: acquiring link line rate information and a working state from a high-speed serial transceiver;
sixth step: and according to the acquired link line rate information and state, estimating the working state of the ARINC818 protocol end, and reconfiguring parameters of the ARINC818 protocol end to adapt to the receiving requirements of different video resolutions.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a method for realizing automatic adaptation of ARINC818 bus link rate based on an FPGA (field programmable gate array) high-speed serial transceiver, which is used for realizing rate handshake with a transmitting end by using a method for dynamically reconfiguring the link rate of the high-speed serial transceiver at a receiving end, wherein the adaptation process uses a linear rate polling mode to poll at intervals of different linear rates, the link rate of the current transmitting end is determined by judging the link handshake state, so that the link rate matching with the transmitting end is realized, four ARINC818 link rates of 1.0625Gbps,2.125Gbps, 3.1875Gbps and 4.25Gbps are supported, the video state is judged according to the matched rate characteristics, so that the self-adaption capability of the whole transmitting and receiving module is realized, in addition, the self-adaption transmitting and the receiving of various resolution videos through the ARINC818 bus can be realized according to the automatic rate matching method.
Drawings
Fig. 1 is a schematic block diagram of a link rate adaptation method of the present invention.
FIG. 2 is a diagram illustrating dynamic reconfiguration parameters of a high-speed serial transceiver according to the present invention.
Description of the embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
Referring to fig. 1-2, the present invention provides a technical solution:
a method for automatically adapting ARINC818 bus link rate uses FPGA high-speed serial transceiver, including FPGA high-speed serial transceiver link rate dynamic reconfiguration, high-speed serial transceiver link rate polling, ARINC818 protocol end line rate reconfiguration three parts, realizing rate handshake with transmitting end by using high-speed serial transceiver link rate dynamic reconfiguration method at receiving end, wherein adapting process uses line rate polling mode to poll different line rates at intervals, determining current transmitting end link rate by judging link handshake state, and realizing link rate matching with transmitting end.
The high-speed serial transceiver link rate dynamic reconfiguration: the method mainly aims at an XILINX high-speed serial communication interface IP, a receiving end can configure the high-speed serial transceiver into four ARINC818 link rates of 1.0625Gbps,2.125Gbps, 3.1875Gbps and 4.25Gbps respectively through parameter configuration, and the XILINX high-speed serial transceiver IP can reconfigure the internal PLL coefficients through a dynamic reconfiguration interface so as to reconfigure the link rates of the high-speed transceiver ports.
The high-speed serial transceiver IP provides the configurable PLL coefficients as shown in fig. 2, and the PLL coefficients are calculated as follows:
Wherein the method comprises the steps off PLLClkin As an external reference clock to which the reference clock is to be applied,f PLLClkout for the PLL clock output,f LineRate for the link rate of the high-speed serial transceiver, the common clock generated outside the ARINC818 is 212.5Mhz, and the corresponding parameter configuration is as follows:
| link rate | M | N1 | N2 | D |
| 1.0625G | 1 | 2 | 5 | 4 |
| 2.125G | 1 | 2 | 5 | 2 |
| 3.1875G | 1 | 3 | 5 | 2 |
| 4.25G | 1 | 2 | 5 | 1 |
Table 1 parameter configuration table corresponding to different line rates
Through the external dynamic configuration interface, as shown in table 1, the parameters corresponding to the high-speed serial transceiver IP are configured, so that dynamic reconfiguration of the link rate can be realized.
The high-speed serial transceiver link rate polls: and judging whether the line rates of the receiving end and the transmitting end are consistent by monitoring the link state returned by the high-speed serial transceiver, if not, changing the line rate of the high-speed serial transceiver through parameter configuration, judging again until the line rates of the receiving end and the transmitting end are consistent, and finally feeding back the scanning result to the ARINC818 protocol end.
The implementation steps of the line rate adaptive scanning are as follows:
the first step: first, the high-speed serial transceiver line rate is configured to 1.0625Gbps;
and a second step of: monitoring the link state of the high-speed serial transceiver after waiting for a period of time, if the state returns to be successful handshake, executing the fourth step, otherwise executing the third step;
and a third step of: reconfiguring the high-speed serial transceiver line rate to other line rates, such as 2.125Gbps, 3.1875Gbps, 4.25gbpsarinc818 link rate, performing a second step;
fourth step: detecting and acquiring the current line rate, fixing the configuration parameter information of the current high-speed serial transceiver IP, and exiting the link rate polling state of the high-speed serial transceiver;
fifth step: acquiring link line rate information and a working state from a high-speed serial transceiver;
sixth step: and according to the acquired link line rate information and state, estimating the working state of the ARINC818 protocol end, and reconfiguring parameters of the ARINC818 protocol end to adapt to the receiving requirements of different video resolutions.
Claims (3)
1. A method for automatically adapting ARINC818 bus link rate uses an FPGA high-speed serial transceiver, which comprises three parts of dynamic reconfiguration of the link rate of the FPGA high-speed serial transceiver, link rate polling of the high-speed serial transceiver and line rate reconfiguration of the ARINC818 protocol end, and is characterized in that: the method comprises the steps that a method of dynamic reconfiguration of the link rate of a high-speed serial transceiver is used at a receiving end to realize rate handshake with a transmitting end, wherein a linear rate polling mode is used in an adaptation process, polling of different linear rates is carried out at intervals, the link rate of the current transmitting end is determined by judging the link handshake state, and then link rate matching with the transmitting end is realized;
the FPGA high-speed serial transceiver link rate dynamic reconfiguration method comprises the following steps: aiming at an XILINX high-speed serial communication interface IP, a receiving end configures a high-speed serial transceiver through parameters, the line rates of the high-speed serial transceiver are respectively configured to be four ARINC818 link rates of 1.0625Gbps,2.125Gbps, 3.1875Gbps and 4.25Gbps, and the XILINX high-speed serial transceiver IP reconfigures the internal PLL coefficients of the XILINX high-speed serial transceiver through a dynamic reconfiguration interface, so that the link rates of the high-speed transceiver port are reconfigured;
the link rate polling of the high-speed serial transceiver is specifically as follows: and judging whether the line rates of the receiving end and the transmitting end are consistent by monitoring the link state returned by the high-speed serial transceiver, if not, changing the line rate of the high-speed serial transceiver through parameter configuration, judging again until the line rates of the receiving end and the transmitting end are consistent, and finally feeding back the scanning result to the ARINC818 protocol end.
2. The method for automatic adaptation of ARINC818 bus link rate of claim 1 wherein: the calculation relation between the configurable PLL coefficient and the link line rate provided by the IP of the FPGA high-speed serial transceiver is as follows:
Wherein the method comprises the steps off PLLClkin As an external reference clock to which the reference clock is to be applied,f PLLClkout for the PLL clock output,f LineRate is the link rate of the high-speed serial transceiver.
3. The method for automatic adaptation of ARINC818 bus link rate of claim 1 wherein: the implementation steps of the line rate adaptive scanning are as follows:
the first step: first, the high-speed serial transceiver line rate is configured to 1.0625Gbps;
and a second step of: monitoring the link state of the high-speed serial transceiver after waiting for a period of time, if the state returns to be successful handshake, executing the fourth step, otherwise executing the third step;
and a third step of: reconfiguring the high-speed serial transceiver line rate to other line rates, such as 2.125Gbps, 3.1875Gbps, 4.25gbpsarinc818 link rate, performing a second step;
fourth step: detecting and acquiring the current line rate, fixing the configuration parameter information of the current high-speed serial transceiver IP, and exiting the link rate polling state of the high-speed serial transceiver;
fifth step: acquiring link line rate information and a working state from a high-speed serial transceiver;
sixth step: and according to the acquired link line rate information and state, estimating the working state of the ARINC818 protocol end, and reconfiguring parameters of the ARINC818 protocol end to adapt to the receiving requirements of different video resolutions.
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| CN104780333A (en) * | 2014-12-03 | 2015-07-15 | 中国航天科工集团第三研究院第八三五七研究所 | High-bandwidth video source interface adaptation device based on FPGA (Field Programmable Gate Array) |
| CN109040836B (en) * | 2018-07-05 | 2020-11-06 | 中国航空工业集团公司洛阳电光设备研究所 | Method and device for analyzing ARINC818 protocol video stream |
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| CN110881027A (en) * | 2019-10-22 | 2020-03-13 | 中国航空工业集团公司洛阳电光设备研究所 | Video transmission system and conversion method of Camera Link-ARINC818 protocol |
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| CN105357070A (en) * | 2015-11-05 | 2016-02-24 | 天津津航计算技术研究所 | FPGA-based ARINC818 bus analysis and test apparatus |
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