CN201274482Y - High speed data transmission interface system - Google Patents
High speed data transmission interface system Download PDFInfo
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- CN201274482Y CN201274482Y CNU2008201457847U CN200820145784U CN201274482Y CN 201274482 Y CN201274482 Y CN 201274482Y CN U2008201457847 U CNU2008201457847 U CN U2008201457847U CN 200820145784 U CN200820145784 U CN 200820145784U CN 201274482 Y CN201274482 Y CN 201274482Y
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Abstract
The utility model relates to a high-speed data transmission interface system which comprises a primary device interface device and a plurality of slave device interface devices. Each device thereof adopts one FPGA chip as CPRI protocol processing chip; and a singlechip is used as the monitor of a CPRI protocol processor. An optical-electrical convertor is connected with the lead foot of a serial-to-parallel converter of the FPGA chip; the clock signal of the FPGA chip is provided by a clock management chip which uses an active crystal oscillator as a clock source. The clock management chip has two clock phase reference input ends which are used correspondingly according to the device interface either in the dominant mode or in the slave mode provided by the CPRI protocol processor. The REC mode uses another active crystal oscillator as the clock phase reference; and the RE mode uses a clock signal provided by the CPRI protocol processor. All interface devices are connected by optical fibers. The high-speed data transmission interface system has the advantages of not only providing a relatively flexible I/Q data transmission interface to conveniently connect all DDC/DUC digital signal processors, but also effectively reducing the using cost.
Description
[technical field]
The utility model is about the device in a kind of remote digital communication system, is meant a kind of high speed data transmission interface system especially, in order to the digital baseband data of transport communication radio system.
[background technology]
Use special-purpose CPRI (Common Public Radio Interface in the high speed data transmission interface at present, common public radio interface) protocol processes chip, this special use CPRI protocol processes chip kind is single, price is also very high, and is very unfavorable for the cost that reduces whole digital communication system.In addition, special chip is more fixing to I/Q (same-phase/quadrature phase) transfer of data, carrying out in the data butt joint with the DDC/DUC of multicarrier (on the numeral/down-conversion) digital signal processor, usually need to use an extra FPGA (Field-Programmable Gate Array, field programmable gate array) chip is handled the I/Q carrier data of multicarrier in advance, make it to meet the interface standard of CPRI protocol processes chip, could use, therefore, the existing high speed data transmission interface of special-purpose CPRI protocol processes chip that utilizes uses very inconvenient, and because the existence of this conversion FPGA, cost has also improved much.
[summary of the invention]
Technical problem to be solved in the utility model is to provide a kind of can freely change the data mating interface, adapting to different DDC/DUC processors, and reduces the high speed data transmission interface system of whole system cost greatly.
The utility model solves the problems of the technologies described above by the following technical programs: a kind of high speed data transmission interface system, comprise 1 master control interface arrangement, with several slave unit interface arrangements, described master control interface arrangement comprises a master control CPRI protocol processor, on the numeral/the down-converted device, a Clock management chip, 4 optical-electrical converters, and 1 single-chip microcomputer, the slave unit interface arrangement comprises a subordinate CPRI protocol processor, on the numeral/the down-converted device, a Clock management chip, 2 optical-electrical converters, a single-chip microcomputer, it is characterized in that: the master control CPRI protocol processor of described master control interface arrangement is a slice field programmable gate array chip, have 4 serial ports, the Clock management chip of described master control interface arrangement, optical-electrical converter, single-chip microcomputer is connected respectively on the described master control CPRI protocol processor, this master control CPRI protocol processor also provides an I/Q transfer of data user interface to connect on the numeral/the down-converted device simultaneously, wherein 4 optical-electrical converters are received 4 serial ports of master control CPRI protocol processor respectively, are connected with 1 active crystal oscillator of master clock and the active crystal oscillator of the reference as phase reference on the Clock management chip of master control interface arrangement;
Should be a slice field programmable gate array chip from the subordinate CPRI protocol processor of interface arrangement, have 4 serial ports, the Clock management chip of slave unit interface arrangement, 2 optical-electrical converters, single-chip microcomputer is connected respectively to subordinate CPRI protocol processor, this subordinate CPRI protocol processor also provides an I/Q transfer of data user interface to connect on the numeral/the down-converted device simultaneously, wherein 2 optical-electrical converters are received 2 serial ports of slave protocol processor respectively, two other serial port is idle, be connected with 1 active crystal oscillator of master clock on the Clock management chip of slave unit interface arrangement, its phase reference clock source is from a synchronizing clock signals of subordinate CPRI protocol processor output;
Use optical fiber to connect between the optical-electrical converter of the optical-electrical converter of described master control interface arrangement and slave unit interface arrangement.
This utility model can further be specially:
The active crystal oscillator of master clock of described master control interface arrangement and slave unit interface arrangement all is active crystal oscillators of the band temperature-compensating of a 245.76MHz, as the clock source, the active crystal oscillator of the reference of described master control interface arrangement is the active crystal oscillator of a 30.72MHz.
Described master control CPRI protocol processor and subordinate CPRI protocol processor use respectively and between the optical-electrical converter isometric impedance matching differential lines to connect.
Comprise 1 slave unit interface arrangement, an optical-electrical converter of described master control interface arrangement and one of them optical-electrical converter of this slave unit interface arrangement are connected, and that is to say traditional P2P connected mode.
An optical-electrical converter of perhaps described master control interface arrangement and one of them optical-electrical converter of a slave unit interface arrangement are connected, interconnect by optical-electrical converter between the slave unit interface arrangement, and also be the connected mode of daisy chain.
Perhaps comprise four slave unit interface arrangements, four optical-electrical converters of described master control interface arrangement are connected i.e. Y-connection mode with the optical-electrical converter of four slave unit interface arrangements respectively.
Four optical-electrical converters of perhaps described master control interface arrangement are connected with the optical-electrical converter of four slave unit interface arrangements respectively, interconnect by optical-electrical converter between the slave unit interface arrangement, being the connected mode of tree topology, is the mixed type of daisy chain and Y-connection mode.
The advantage of a kind of high speed data transmission interface of the utility model system is: use FPGA to realize the CPRI protocol processes, an I/Q data transmission interface relatively flexibly is provided, conveniently be connected with various DDC/DUC digital signal processors, effectively reduce use cost, can realize software upgrading by the change code simultaneously.
[description of drawings]
The utility model will be further described in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the hardware principle block diagram of the utility model high speed data transmission interface system.
Fig. 2 is the schematic diagram of the daisy chain connected mode of the utility model high speed data transmission interface system.
Fig. 3 is the schematic diagram of the Y-connection mode of the utility model high speed data transmission interface system.
Fig. 4 is the schematic diagram of the tree topology connected mode of the utility model high speed data transmission interface system.
[embodiment]
See also Fig. 1, this utility model high speed data transmission interface comprises master control interface arrangement 10 and the slave unit interface arrangement 20 of at least one.The intercommunication of master control interface arrangement 10 and slave unit interface arrangement 20, wherein master control interface arrangement 10 is descending to the transmission of slave unit interface arrangement 20, otherwise is up.
This master control interface arrangement 10 comprises a master control CPRI protocol processor 12, DDC/DUC digital signal processor 14, Clock management chip 16, four optical-electrical converters 18, and a single-chip microcomputer 19.
This master control CPRI protocol processor 12 is a slice fpga chip, has four serial ports.DDC/DUC digital signal processor 14, Clock management chip 16, four optical-electrical converters 18, and single-chip microcomputer 19 is connected respectively to this master control CPRI protocol processor 12.
Wherein master control CPRI protocol processor 12 provides one group of I/Q data transmission interface and I/Q Data Receiving interface for DDC/DUC digital signal processor 14.
Wherein four optical-electrical converters 18 are connected respectively to four serial ports of master control CPRI protocol processor 12.Also be connected with 1 active crystal oscillator 162 of master clock and the active crystal oscillator 164 of the reference as phase reference on this Clock management chip 16, the active crystal oscillator of the band temperature-compensating that the active crystal oscillator 162 of this master clock is 245.76MHz is as the clock source of Clock management chip 16.With reference to active crystal oscillator 164 are active crystal oscillators of a 30.72MHz, as the reference clock of Clock management chip 16.
This slave unit interface arrangement 20 comprises a subordinate CPRI protocol processor 22, DDC/DUC digital signal processor 24,26,2 optical-electrical converters 28 of Clock management chip, and a single-chip microcomputer 29.
This subordinate CPRI protocol processor 22 is a slice fpga chip, has 4 serial ports.DDC/DUC digital signal processor 24, Clock management chip 26, four optical-electrical converters 28, and single-chip microcomputer 29 is connected respectively to this subordinate CPRI protocol processor 22.
Wherein subordinate CPRI protocol processor 22 provides one group of I/Q data transmission interface and I/Q Data Receiving interface for DDC/DUC digital signal processor 24.
Wherein 2 optical-electrical converters 28 link to each other with 2 serial ports of subordinate CPRI protocol processor 22 respectively.Also be connected with 1 active crystal oscillator 262 of master clock on this Clock management chip 26, the active crystal oscillator of the band temperature-compensating that the active crystal oscillator 262 of this master clock is 245.76MHz is as the clock source of Clock management chip 26.Its phase reference clock source is from a synchronizing clock signals of subordinate CPRI protocol processor 22 outputs.
Above-mentioned master control interface arrangement 10 is on the reference clock of Clock management chip with the maximum difference of slave unit interface arrangement 20, wherein the reference clock of the Clock management chip 16 of master control interface arrangement 10 is active crystal oscillators 164 of reference of 30.72MHz, and the reference clock of the Clock management chip 26 of slave unit interface arrangement 20 is the clocks from a 30.72MHz of CPRI protocol processor 22 outputs, this clock is the clock that CPRI protocol processor 22 extracts from the high speed transmission data signal and recovers to come out, and can accomplish that like this clock between master control interface arrangement 10 and the slave unit interface arrangement 20 is the homology clock.Give master control CPRI protocol processor 12 as the work reference clock by 1 group of difference 61.44MHz clock of Clock management chip 16 outputs again, give subordinate CPRI protocol processor 22 as the work reference clock by 1 group of difference 61.44MHz clock of Clock management chip 26 outputs, so just can guarantee that whole transmission system is in same clock source.
The connected mode of above-mentioned master control interface arrangement 10 and slave unit interface arrangement 20 comprises following several:
P2P connected mode as shown in Figure 1, promptly this high speed data transmission interface system comprises 10,1 slave unit interface arrangement 20 of 1 master control interface arrangement, and an optical-electrical converter 18 of described master control interface arrangement 10 and one of them optical-electrical converter 28 of this slave unit interface arrangement 20 are connected.
As shown in Figure 2 be the schematic diagram of the connected mode of daisy chain, promptly this high speed data transmission interface system comprises 1 master control interface arrangement 10, a plurality of slave unit interface arrangement 20, an optical-electrical converter 18 of master control interface arrangement 10 and one of them optical-electrical converter 28 of a slave unit interface arrangement 20 are connected, and interconnect by optical-electrical converter 28 between the slave unit interface arrangement 20.
As shown in Figure 3 be the schematic diagram of Y-connection mode, promptly this high speed data transmission interface system comprises 10,4 slave unit interface arrangements 20 of 1 master control interface arrangement, and four optical-electrical converters 18 of described master control interface arrangement 10 are connected with the optical-electrical converter 28 of four slave unit interface arrangements 20 respectively.
As shown in Figure 4 be the schematic diagram of the connected mode of tree topology, promptly this high speed data transmission interface system comprises 1 master control interface arrangement 10, a plurality of slave unit interface arrangement 20, four optical-electrical converters 18 of described master control interface arrangement 10 are connected with the optical-electrical converter 28 of four slave unit interface arrangements 20 respectively, interconnecting by optical-electrical converter 28 between the slave unit interface arrangement 20, promptly is the mixed type of above-mentioned daisy chain and Y-connection mode.
Four optical-electrical converters 18 of above-mentioned master control interface arrangement 10 and the optical-electrical converter of slave unit interface arrangement 20 28 are connected by optical fiber, realize communication thereby make between master control interface arrangement 10 and the slave unit interface arrangement 20.
The course of work of this high speed data transmission interface is as described below:
At first, the I/Q data that master control interface arrangement 10 receives are at master control CPRI protocol processor 12 the inside CPRI protocol data-flows, and sending optical-electrical converter 18 to after converting the signal of telecommunication to by serial port, optical-electrical converter 18 is processed into light signal with the signal of telecommunication, enables to give far-end by Optical Fiber Transmission;
Far-end slave unit interface arrangement 20 receives the light signal that master control interface arrangement 10 sends by optical-electrical converter 28, and it is processed into the signal of telecommunication sends subordinate CPRI protocol processor 22 to by serial port, subordinate CPRI protocol processor 22 recovers the I/Q data to come out from protocol data, and be transferred to DDC/DUC digital signal processor 24 and handle, and the serial port by subordinate CPRI protocol processor 22 in the mode of broadcasting to descending transmission;
Meanwhile, the I/Q data that I/Q data that slave unit interface arrangement 20 also obtains 24 processing of far-end DDC/DUC digital signal processor and descending subordinate CPRI protocol processor 22 are uploaded are carried out addition and are closed the road, are transferred to master control interface arrangement 10 in the same way by the serial port of giving subordinate CPRI protocol processor 22.The I/Q data that the master control CPRI protocol processor 12 of master control interface arrangement 10 recovers are wherein given DDC/DUC digital signal processor 14.
In addition, single-chip microcomputer 19 and single-chip microcomputer 29 carry out the work monitoring of master control CPRI protocol processor 12 and subordinate CPRI protocol processor 22.
Above-mentioned master control CPRI protocol processor 12 and subordinate CPRI protocol processor 22 use respectively and between the optical- electrical converter 18,28 isometric impedance matching differential lines to connect.
Above-mentioned master control CPRI protocol processor 12 and subordinate CPRI protocol processor 22 are LatticeLFE2M20SE or Lattice LFE2M35SE, optical- electrical converter 18,28 is HisenseLTE3405/LTE4305, Clock management chip 16 and Clock management chip 26 are CDCM7005, and single-chip microcomputer 19 and single-chip microcomputer 29 are ATMEL16L.
Claims (7)
1. high speed data transmission interface system, comprise 1 master control interface arrangement, with several slave unit interface arrangements, described master control interface arrangement comprises a master control common public radio interface protocol processor, on the numeral/the down-converted device, a Clock management chip, 4 optical-electrical converters, and 1 single-chip microcomputer, each slave unit interface arrangement comprises a subordinate common public radio interface protocol processor, on the numeral/the down-converted device, a Clock management chip, 2 optical-electrical converters, a single-chip microcomputer, it is characterized in that: the master control common public radio interface protocol processor of described master control interface arrangement is a slice field programmable gate array chip, have 4 serial ports, the Clock management chip of described master control interface arrangement, optical-electrical converter, single-chip microcomputer is connected respectively on the described master control common public radio interface protocol processor, this master control common public radio interface protocol processor also provides a same-phase/quadrature phase transfer of data user interface to connect on the numeral/the down-converted device simultaneously, wherein 4 optical-electrical converters are received 4 serial ports of master control common public radio interface protocol processor respectively, are connected with 1 active crystal oscillator of master clock and the active crystal oscillator of the reference as phase reference on the Clock management chip of master control interface arrangement;
Should be a slice field programmable gate array chip from the subordinate common public radio interface protocol processor of interface arrangement, have 4 serial ports, the Clock management chip of slave unit interface arrangement, 2 optical-electrical converters, single-chip microcomputer is connected respectively to subordinate common public radio interface protocol processor, this subordinate common public radio interface protocol processor also provides an I/Q transfer of data user interface to connect on the numeral/the down-converted device simultaneously, wherein 2 optical-electrical converters are received 2 serial ports of slave protocol processor respectively, two other serial port is idle, be connected with 1 active crystal oscillator of master clock on the Clock management chip of slave unit interface arrangement, its phase reference clock source is from a synchronizing clock signals of subordinate common public radio interface protocol processor output;
Use optical fiber to connect between the optical-electrical converter of the optical-electrical converter of described master control interface arrangement and slave unit interface arrangement.
2. a kind of high speed data transmission interface as claimed in claim 1 system, it is characterized in that: the active crystal oscillator of master clock of described master control interface arrangement and slave unit interface arrangement all is active crystal oscillators of the band temperature-compensating of a 245.76MHz, as the clock source, the active crystal oscillator of the reference of described master control interface arrangement is the active crystal oscillator of a 30.72MHz.
3. a kind of high speed data transmission interface as claimed in claim 1 system is characterized in that: described master control common public radio interface protocol processor and subordinate common public radio interface protocol processor are respectively and use isometric impedance matching differential lines to connect between the optical-electrical converter.
4. a kind of high speed data transmission interface as claimed in claim 1 system, it is characterized in that: comprise 1 slave unit interface arrangement, an optical-electrical converter of described master control interface arrangement and one of them optical-electrical converter of this slave unit interface arrangement are connected.
5. a kind of high speed data transmission interface as claimed in claim 1 system, it is characterized in that: an optical-electrical converter of described master control interface arrangement and one of them optical-electrical converter of a slave unit interface arrangement are connected, and interconnect by optical-electrical converter between the slave unit interface arrangement.
6. a kind of high speed data transmission interface as claimed in claim 1 system, it is characterized in that: comprise four slave unit interface arrangements, four optical-electrical converters of described master control interface arrangement are connected with the optical-electrical converter of four slave unit interface arrangements respectively
7. a kind of high speed data transmission interface as claimed in claim 1 system, it is characterized in that: four optical-electrical converters of described master control interface arrangement are connected with the optical-electrical converter of four slave unit interface arrangements respectively, interconnect by optical-electrical converter between the slave unit interface arrangement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201457847U CN201274482Y (en) | 2008-09-28 | 2008-09-28 | High speed data transmission interface system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201457847U CN201274482Y (en) | 2008-09-28 | 2008-09-28 | High speed data transmission interface system |
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| CN201274482Y true CN201274482Y (en) | 2009-07-15 |
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| CNU2008201457847U Expired - Fee Related CN201274482Y (en) | 2008-09-28 | 2008-09-28 | High speed data transmission interface system |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158287A (en) * | 2010-12-16 | 2011-08-17 | 中国北车集团大连机车车辆有限公司 | Star-network-based serial communication module and control method thereof |
| CN102117439B (en) * | 2010-01-06 | 2012-11-28 | 湖北省烟草公司襄樊市公司 | Enterprise data monitoring and early warning device |
| CN104467906A (en) * | 2014-12-01 | 2015-03-25 | 沈阳工业大学 | Super-speed digital signal wireless transceiver |
| CN105354166A (en) * | 2015-10-10 | 2016-02-24 | 上海未来伙伴机器人有限公司 | Robot and applicable data transmission method |
| CN110505200A (en) * | 2019-07-09 | 2019-11-26 | 惠州市亿能电子有限公司 | A kind of multi-protocols daisy chain interface conversion chip |
| CN113505094A (en) * | 2021-09-06 | 2021-10-15 | 上海类比半导体技术有限公司 | MCU, host and method for transmitting data by multiple MCUs |
-
2008
- 2008-09-28 CN CNU2008201457847U patent/CN201274482Y/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102117439B (en) * | 2010-01-06 | 2012-11-28 | 湖北省烟草公司襄樊市公司 | Enterprise data monitoring and early warning device |
| CN102158287A (en) * | 2010-12-16 | 2011-08-17 | 中国北车集团大连机车车辆有限公司 | Star-network-based serial communication module and control method thereof |
| CN102158287B (en) * | 2010-12-16 | 2014-10-29 | 中国北车集团大连机车车辆有限公司 | Star-network-based serial communication module and control method thereof |
| CN104467906A (en) * | 2014-12-01 | 2015-03-25 | 沈阳工业大学 | Super-speed digital signal wireless transceiver |
| CN105354166A (en) * | 2015-10-10 | 2016-02-24 | 上海未来伙伴机器人有限公司 | Robot and applicable data transmission method |
| CN105354166B (en) * | 2015-10-10 | 2018-08-14 | 上海未来伙伴机器人有限公司 | Robot and the data transmission method being applicable in |
| CN110505200A (en) * | 2019-07-09 | 2019-11-26 | 惠州市亿能电子有限公司 | A kind of multi-protocols daisy chain interface conversion chip |
| CN113505094A (en) * | 2021-09-06 | 2021-10-15 | 上海类比半导体技术有限公司 | MCU, host and method for transmitting data by multiple MCUs |
| CN113505094B (en) * | 2021-09-06 | 2022-01-25 | 上海类比半导体技术有限公司 | MCU, host and method for transmitting data by multiple MCUs |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090715 Termination date: 20140928 |
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| EXPY | Termination of patent right or utility model |