CN112559260A - Power-on self-test method and device - Google Patents

Power-on self-test method and device Download PDF

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Publication number
CN112559260A
CN112559260A CN201910919222.6A CN201910919222A CN112559260A CN 112559260 A CN112559260 A CN 112559260A CN 201910919222 A CN201910919222 A CN 201910919222A CN 112559260 A CN112559260 A CN 112559260A
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self
power
test
controlling
starting
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CN201910919222.6A
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王振真
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Beijing L&s Lancom Platform Tech Co ltd
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Beijing L&s Lancom Platform Tech Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Stored Programmes (AREA)

Abstract

The application discloses a power-on self-test method and device. Wherein, the method comprises the following steps: configuring a main starting component and a standby starting component; controlling the main starting assembly to execute power-on self-test; and under the condition that the main starting assembly fails to execute the power-on self-test, switching to the standby starting assembly to execute the power-on self-test. The power-on self-checking method and the power-on self-checking device solve the technical problem that self-checking fails easily due to the fact that the power-on self-checking mode in the prior art is adopted.

Description

Power-on self-test method and device
Technical Field
The application relates to the field of computers, in particular to a power-on self-test method and device.
Background
The BIOS is a set of programs solidified on a ROM chip on the mainboard in the computer, which stores the most important basic input and output programs of the computer, the self-checking program after power-on and the system self-starting program, and can read and write the specific information set by the system from the CMOS. Its primary function is to provide the lowest level, most direct hardware setup and control for the computer. The BIOS also provides some system parameters to the operating system. The change of system hardware is hidden by BIOS, and programs use BIOS functions rather than directly control the hardware.
The BIOS setting program is stored in BIOS chip, which is one rectangular or square chip on the mainboard and may be set only during starting. The BIOS setting program is mainly used for managing and setting the basic input and output system of the hardware, so that the system can run in the best state, and system faults or system problems can be eliminated or diagnosed by using the BIOS setting program.
When the power key of the mainboard is pressed, the power supply can immediately supply power, and meanwhile, the BIOS program on the mainboard can sequentially perform self-checking from the aspects of the CPU, the memory, the display equipment and the hard disk. The system is entered when the self-test is completed. bios mainly stores the most basic i/o program of the host and the self-checking system after booting. The system is more like a micro system of a mainboard and is responsible for setting and guiding the startup of a host, and if the link fails, the hard disk and the U disk can not be identified, so that the system cannot be installed; hardware self-test may not be performed, and the host cannot be started after repeated restart. It may also cause the motherboard device to card into the BIOS interface and not be able to access the system.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the application provides a power-on self-test method and device, which are used for at least solving the technical problem that the power-on self-test mode in the prior art is easy to cause self-test failure.
According to an aspect of the embodiments of the present application, a power-on self-test method is provided, including: configuring a main starting component and a standby starting component; controlling the main starting assembly to execute power-on self-test; and under the condition that the main starting assembly fails to execute the power-on self-test, switching to the standby starting assembly to execute the power-on self-test.
Optionally, after controlling the active startup component to perform power on self-test, the method further includes: controlling a first timer to start timing; and if the main starting assembly successfully executes the power-on self-test within the first preset time period recorded by the first timer, controlling the first timer to reset.
Optionally, the method further comprises: and if the first timer is reset, controlling the mainboard to start.
Optionally, switching to the standby initiating component to perform power-on self-test includes: sending a starting instruction to the standby starting component; calling a starting program fed back by the standby starting component based on the starting instruction; and controlling the standby starting assembly to execute power-on self-test based on the starting program.
Optionally, after switching to the standby initiating component to perform power-on self-test, the method further includes: controlling a second timer to start timing; and if the standby starting assembly successfully executes the power-on self-test within a second preset time period recorded by the second timer, controlling the second timer to reset.
Optionally, after controlling the second timer to reset, the method further includes: acquiring a first mapping file of the standby starting assembly, wherein the first mapping file is used for executing power-on self-test; sending the first mapping file to the main starting component; and controlling the main starting component to update a second mapping file into the first mapping file, wherein the second mapping file is a file when the main starting component fails to execute the power-on self-test.
According to an aspect of the embodiments of the present application, there is provided a power on self test apparatus, including: the configuration module is used for configuring the main starting component and the standby starting component; the control module is used for controlling the main starting assembly to execute power-on self-test; and the switching module is used for switching to the standby starting assembly to execute the power-on self-test under the condition that the main starting assembly fails to execute the power-on self-test.
Optionally, after controlling the active startup component to perform power on self-test, the apparatus is further configured to: controlling a first timer to start timing; and if the main starting assembly successfully executes the power-on self-test within the first preset time period recorded by the first timer, controlling the first timer to reset.
Optionally, the apparatus is further configured to: and if the first timer is reset, controlling the mainboard to start.
According to an aspect of the embodiments of the present application, a storage medium is provided, where the storage medium includes a stored program, and when the program runs, the device where the storage medium is located is controlled to execute the power-on self-test method described above.
According to an aspect of the embodiments of the present application, there is provided a processor, where the processor is configured to execute a program, where the program executes the power-on self-test method described above.
In the embodiment of the application, a main starting component and a standby starting component are configured; controlling the main starting assembly to execute power-on self-test; when the main starting assembly fails to execute the power-on self-test, the mode of executing the power-on self-test by the standby starting assembly is switched to, and the reliability of executing the power-on self-test by the BIOS mode is improved through the setting of the standby starting assembly, so that the technical effect of improving the success rate of the power-on self-test by still executing the power-on self-test by the standby starting assembly when the main starting assembly BIOS fails to execute the power-on self-test is realized, and the technical problem that the power-on self-test fails easily caused by the power-on self-test mode in the prior art is.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic flowchart of a power-on self-test method according to an embodiment of the present application;
fig. 2 is a schematic flowchart of a power-on self-test method according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an alternative power-on self-test apparatus according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
According to an embodiment of the present application, there is provided a power on self test method embodiment, it should be noted that the steps shown in the flowchart of the drawings may be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in an order different from that shown or described herein.
Fig. 1 is a schematic flowchart of a power-on self-test method according to an embodiment of the present application, and as shown in fig. 1, the method at least includes the following steps:
step S102, configuring a main starting component and a standby starting component;
in some optional embodiments of the present application, the active boot component may be disposed in the BIO chip, and the standby boot component may be disposed in another BIOs chip.
In other alternative embodiments of the present application, the active boot component and the standby boot component may also be the BIOS chip itself. The BIOS chip can be welded on the mainboard.
Optionally, the main boot component and the standby boot component may respectively carry independent BIOS images, the BIOS images may be images for performing power on self-test and/or motherboard boot and/or operating system boot, and parameters of the images may be covered; the standby boot component may carry a BIOS image that is locked to factory default values, which may ensure that a power-on self-test and/or a motherboard boot and/or an operating system boot is performed safely and successfully.
In some optional embodiments of the present application, the update of the BIOS image of the active boot component may be implemented by overwriting the BIOS image of the standby boot component with the BIOS image of the active boot component.
Step S104, controlling the main starting assembly to execute power-on self-test;
in some optional embodiments of the present application, the motherboard may control the active boot component to perform power-on self-test. Specifically, the active startup component can be controlled by a control chip arranged on the mainboard to execute power-on self-test.
Step S106, under the condition that the main starting component fails to execute the power-on self-test, the standby starting component is switched to execute the power-on self-test.
Optionally, after controlling the active startup component to perform power on self-test, the method further needs to perform the following steps: controlling a first timer to start timing; and if the main starting assembly successfully executes the power-on self-test within the first preset time period recorded by the first timer, controlling the first timer to reset.
In some optional embodiments of the present application, the first timer may be disposed in the motherboard, the first preset time period may be set to 7 minutes, and when the motherboard detects that the active startup component successfully implements the power-on self-test within 7 minutes, the first timer is controlled to reset.
Optionally, the method further needs to perform the following steps: and if the first timer is reset, controlling the mainboard to start.
In some optional embodiments of the present application, the reset of the first timer represents that the main-use startup component successfully implements the power-on self-test, and when the power-on self-test passes, the main board may be controlled to start. Specifically, the motherboard can be controlled to start by a control chip arranged on the motherboard.
In some optional embodiments of the application, before switching to the standby initiating component to perform the power on self test, the method further needs to execute a step of, after the first timer starts to count time, if the first timer is not reset after a first preset time period, determining that the main initiating component fails to perform the power on self test, and starting to switch to the standby initiating component to perform the program of the power on self test.
Optionally, switching to the standby initiating component to perform power-on self-test may be implemented by: sending a starting instruction to the standby starting component; calling a starting program fed back by the standby starting component based on the starting instruction; and controlling the standby starting assembly to execute power-on self-test based on the starting program.
Optionally, after the standby starting component is controlled based on the starting program to execute the power-on self-test successfully, the main board is controlled to be started, and the operating system is automatically started.
Optionally, after switching to the standby initiating component to perform the power-on self-test, the method further needs to perform the following steps: controlling a second timer to start timing; and if the standby starting assembly successfully executes the power-on self-test within a second preset time period recorded by the second timer, controlling the second timer to reset.
In some alternative embodiments of the present application, the CPLD starts counting (7 minutes) after the motherboard is started. When the BIOS corresponding to the main starting component completes the power-on self-test, the CPLD is informed to reset the count and send the mainboard starting preparation. If the CPLD does not receive the counting reset within 7 minutes, the control chip resets, controls the BIOS corresponding to the standby starting component to execute the power-on self-test, and sends out the counting reset to send the mainboard starting preparation. After the counting is reset, the CPLD stops counting and returns the SPI CS # to the BIOS corresponding to the primary boot component, which may be used to update the BIOS corresponding to the primary boot component.
Optionally, after controlling the second timer to reset, the method further needs to perform the following steps: acquiring a first mapping file of the standby starting assembly, wherein the first mapping file is used for executing power-on self-test; sending the first mapping file to the main starting component; and controlling the main starting component to update a second mapping file into the first mapping file, wherein the second mapping file is a file when the main starting component fails to execute the power-on self-test.
According to the main board double-BIOS design, the data on the main BIOS chip can be prevented from being damaged by malicious software attack, or the main BIOS can not work due to physical damage. When the main BIOS file is damaged or has errors, the auxiliary BIOS automatically repairs programs, or the main BIOS switch and the auxiliary BIOS switch on the mainboard are directly switched, so that the safety and the use stability of the host are improved.
The problem that the mainboard and the operating system cannot normally run due to damage of the BIOS is well solved. According to the application, the two BIOS chips do not need manual operation, and the main board can directly monitor whether the main BIOS is damaged or not. The main BIOS is prevented from being damaged to cause the failure of the main board, and the repair amount of equipment is reduced.
Fig. 2 is a schematic flowchart of a power-on self-test method according to an embodiment of the present application, and as shown in fig. 2, the method at least includes the following steps:
step S202, electrifying the mainboard;
step S204, the mainboard executes power-on self-test from the main BIOS;
optionally, the main BIOS may be the above-mentioned main boot component;
step S206, whether the main BIOS completes power-on self-test within 7 minutes or not is judged; if yes, the following step S208 is executed, and if no, the following step S210 is executed.
Step S208, entering an operating system;
step S210, automatically resetting the mainboard;
step S212, the main board is switched to the standby BIOS to execute power-on self-test;
the standby BIOS may be the standby boot component described above.
Step S214, the operation system is entered.
Optionally, after step S214, repair and image update may be performed on the main BIOS.
Optionally, after the main BIOS is repaired and the image is updated, the system may be manually powered off, and the system may re-execute the step S204.
In the embodiment of the application, a main starting component and a standby starting component are configured; controlling the main starting assembly to execute power-on self-test; when the main starting assembly fails to execute the power-on self-test, the mode of executing the power-on self-test by the standby starting assembly is switched to, and the reliability of executing the power-on self-test by the BIOS mode is improved through the setting of the standby starting assembly, so that the technical effect of improving the success rate of the power-on self-test by still executing the power-on self-test by the standby starting assembly when the main starting assembly BIOS fails to execute the power-on self-test is realized, and the technical problem that the power-on self-test fails easily caused by the power-on self-test mode in the prior art is.
According to an embodiment of the present application, there is also provided a power on self test apparatus for implementing the power on self test method, as shown in fig. 3, the apparatus includes: a configuration module 32, a control module 34, a switching module 36; wherein:
a configuration module 32, configured to configure the active startup component and the standby startup component;
the control module 34 is configured to control the active startup component to perform power-on self-test;
and a switching module 36, configured to switch to the standby starting component to perform the power on self test when the primary starting component fails to perform the power on self test.
Optionally, after controlling the active startup component to perform power on self-test, the apparatus is further configured to: controlling a first timer to start timing; and if the main starting assembly successfully executes the power-on self-test within the first preset time period recorded by the first timer, controlling the first timer to reset.
Optionally, the apparatus is further configured to: and if the first timer is reset, controlling the mainboard to start.
Optionally, the apparatus is further configured to: sending a starting instruction to the standby starting component; calling a starting program fed back by the standby starting component based on the starting instruction; and controlling the standby starting assembly to execute power-on self-test based on the starting program.
Optionally, after switching to the standby initiating component to perform power-on self-test, the apparatus is further configured to: controlling a second timer to start timing; and if the standby starting assembly successfully executes the power-on self-test within a second preset time period recorded by the second timer, controlling the second timer to reset.
Optionally, after controlling the second timer to reset, the apparatus is further configured to: acquiring a first mapping file of the standby starting assembly, wherein the first mapping file is used for executing power-on self-test; sending the first mapping file to the main starting component; and controlling the main starting component to update a second mapping file into the first mapping file, wherein the second mapping file is a file when the main starting component fails to execute the power-on self-test.
It should be noted that, reference may be made to the description related to the embodiment shown in fig. 1 for a preferred implementation of the embodiment shown in fig. 3, and details are not described here again.
According to another aspect of the embodiments of the present application, there is also provided a storage medium including a stored program, optionally in this embodiment, the storage medium is configured to store program code for performing the following steps:
configuring a main starting component and a standby starting component; controlling the main starting assembly to execute power-on self-test; and under the condition that the main starting assembly fails to execute the power-on self-test, switching to the standby starting assembly to execute the power-on self-test.
According to another aspect of the embodiments of the present application, there is further provided a processor, where the processor is configured to execute a program, where the program may execute the following steps in the power-on self-test method of the application program when the program runs:
configuring a main starting component and a standby starting component; controlling the main starting assembly to execute power-on self-test; and under the condition that the main starting assembly fails to execute the power-on self-test, switching to the standby starting assembly to execute the power-on self-test.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present application, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit may be a division of a logic function, and an actual implementation may have another division, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or may not be executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present application and it should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims (11)

1. A power-on self-test method is characterized by comprising the following steps:
configuring a main starting component and a standby starting component;
controlling the main starting assembly to execute power-on self-test;
and under the condition that the main starting assembly fails to execute the power-on self-test, switching to the standby starting assembly to execute the power-on self-test.
2. The method according to claim 1, wherein after controlling the active boot component to perform power-on self-test, the method further comprises:
controlling a first timer to start timing;
and if the main starting assembly successfully executes the power-on self-test within the first preset time period recorded by the first timer, controlling the first timer to reset.
3. The method of claim 2, further comprising: and if the first timer is reset, controlling the mainboard to start.
4. The method of claim 3, wherein switching to the standby initiating component to perform power-on self-test comprises:
sending a starting instruction to the standby starting component;
calling a starting program fed back by the standby starting component based on the starting instruction;
and controlling the standby starting assembly to execute power-on self-test based on the starting program.
5. The method of claim 4, wherein after switching to the standby initiating component to perform power-on self-test, the method further comprises:
controlling a second timer to start timing;
and if the standby starting assembly successfully executes the power-on self-test within a second preset time period recorded by the second timer, controlling the second timer to reset.
6. The method of claim 5, wherein after controlling the second timer to reset, the method further comprises:
acquiring a first mapping file of the standby starting assembly, wherein the first mapping file is used for executing power-on self-test;
sending the first mapping file to the main starting component;
and controlling the main starting component to update a second mapping file into the first mapping file, wherein the second mapping file is a file when the main starting component fails to execute the power-on self-test.
7. A power-on self-test device is characterized by comprising:
the configuration module is used for configuring the main starting component and the standby starting component;
the control module is used for controlling the main starting assembly to execute power-on self-test;
and the switching module is used for switching to the standby starting assembly to execute the power-on self-test under the condition that the main starting assembly fails to execute the power-on self-test.
8. The apparatus according to claim 7, wherein after controlling the active boot component to perform power-on self-test, the apparatus is further configured to:
controlling a first timer to start timing;
and if the main starting assembly successfully executes the power-on self-test within the first preset time period recorded by the first timer, controlling the first timer to reset.
9. The apparatus of claim 8, wherein the apparatus is further configured to: and if the first timer is reset, controlling the mainboard to start.
10. A storage medium, comprising a stored program, wherein when the program runs, the apparatus where the storage medium is located is controlled to execute the power on self test method according to any one of claims 1 to 6.
11. A processor, configured to execute a program, wherein the program executes the power on self test method according to any one of claims 1 to 6.
CN201910919222.6A 2019-09-26 2019-09-26 Power-on self-test method and device Pending CN112559260A (en)

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Application Number Priority Date Filing Date Title
CN201910919222.6A CN112559260A (en) 2019-09-26 2019-09-26 Power-on self-test method and device

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