CN114816886A - Server restart test optimization method, system, terminal and storage medium - Google Patents

Server restart test optimization method, system, terminal and storage medium Download PDF

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Publication number
CN114816886A
CN114816886A CN202210606667.0A CN202210606667A CN114816886A CN 114816886 A CN114816886 A CN 114816886A CN 202210606667 A CN202210606667 A CN 202210606667A CN 114816886 A CN114816886 A CN 114816886A
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China
Prior art keywords
bios
cpu initialization
server
bmc
initialization interface
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CN202210606667.0A
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Inventor
张国奇
周帅
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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Priority to CN202210606667.0A priority Critical patent/CN114816886A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Stored Programmes (AREA)

Abstract

The invention relates to the technical field of AMD X86 servers, in particular to a server restart test optimization method, a system, a terminal and a storage medium, which comprise the following steps: the BMC judges whether the server is restarted and clamped on a CPU initialization interface or not based on the potential signal state of the target pin or the communication state of the target pin and the BIOS; and if the server reboots the card on the CPU initialization interface, skipping over the CPU initialization interface by repeatedly training a target pin or switching the BIOS running state control system. The invention can assist the system to skip the PSP interface to enter the BIOS system, and avoid the problem of the PSP interface being blocked in the process of restarting the test.

Description

Server restart test optimization method, system, terminal and storage medium
Technical Field
The invention belongs to the technical field of AMD X86 servers, and particularly relates to a server restart test optimization method, a system, a terminal and a storage medium.
Background
Current AMD X86 CPUs have outperformed Intel's servers in performance, but may require market and time milling in ecological adaptations. For the AMD Milan series of servers, during the use process of simulating extreme environment, some problems occur that card PSP (CPU initialization interface) appears in continuous power cycle test and the BIOS system interface can not be accessed.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present invention provides a method, a system, a terminal and a storage medium for optimizing a server restart test, so as to solve the above-mentioned technical problems.
In a first aspect, the present invention provides a server restart test optimization method, including:
the BMC judges whether the server is restarted and is clamped on a CPU initialization interface or not based on the potential signal state of the target pin or the communication state of the target pin and the BIOS;
and if the server reboots the card on the CPU initialization interface, skipping over the CPU initialization interface by repeatedly training a target pin or switching the BIOS running state control system.
Further, the BMC determines whether the server is restarted and is stuck to the CPU initialization interface based on the potential signal state of the target pin or the communication state with the BIOS, including:
BMC judges whether the potential signals of the reset pin, the enable pin and the all-time pin which control the starting of the PCIE equipment are all in a normal state: if not, judging that the server rebooting card is in the CPU initialization interface;
the BMC records the power-on time and judges whether communication transmission exists between the BMC and the BIOS before the power-on time reaches a specified time limit: if not, judging that the server reboots the card on the CPU initialization interface.
Further, if the server reboots the card and skips the CPU initialization interface by repeatedly training the target pin or switching the BIOS operating state control system, including:
the BMC trains the potential state of the target pin for multiple times until the set times are reached;
if the system is still clamped on the CPU initialization interface, the BIOS process influencing the startup of the BIOS firmware is forbidden, so that the BIOS keeps minimum system operation, and the forbidden setting is released after the CPU initialization interface is skipped.
In a second aspect, the present invention provides a server restart test optimization system, including:
the abnormality detection unit is used for judging whether the server is restarted and is clamped on a CPU initialization interface or not by the BMC based on the potential signal state of the target pin or the communication state of the BMC and the BIOS;
and the exception handling unit is used for skipping the CPU initialization interface by repeatedly training the target pin or switching the BIOS running state control system if the server restart card is on the CPU initialization interface.
Further, the abnormality detection unit includes:
the first detection module is used for the BMC to judge whether potential signals of the reset pin, the enable pin and the all-time pin which control the starting of the PCIE equipment are all in a normal state: if not, judging that the server rebooting card is in the CPU initialization interface;
the second detection module is used for recording the power-on time by the BMC and judging whether communication transmission exists between the BMC and the BIOS before the power-on time reaches a specified period: if not, judging that the server reboots the card on the CPU initialization interface.
Further, the exception handling unit includes:
the first processing module is used for the BMC to train the potential state of the target pin for multiple times until the set times is reached;
and the second processing module is used for forbidding the BIOS process influencing the startup of the BIOS firmware if the system is still clamped on the CPU initialization interface so as to ensure that the BIOS keeps minimum system operation, and removing the forbidding setting after skipping the CPU initialization interface.
In a third aspect, a terminal is provided, including:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is configured to call and run the computer program from the memory, so that the terminal performs the method of the terminal described above.
In a fourth aspect, a computer storage medium is provided having stored therein instructions that, when executed on a computer, cause the computer to perform the method of the above aspects.
The server restart test optimization method, the server restart test optimization system, the server restart test optimization terminal and the storage medium have the advantages that the server firmware BMC is used as the BMC of the server monitoring software, the server firmware BMC can be communicated with hardware to acquire some potential information of the hardware in the PSP process, and meanwhile, the server restart test optimization method can be judged by communicating with a BIOS system through a command protocol; the BMC judges whether the server is abnormal in a PSP interface in the starting process through the interaction process of the BIOS software and the hardware, meanwhile, the BMC can interact with the BIOS system in a command protocol mode to assist in skipping over the PSP interface to enter the BIOS system, and if the server cannot enter the BIOS system interface, the BMC can also control through controlling the hardware to avoid the problem of being blocked on the PSP interface.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.
FIG. 2 is another schematic flow diagram of a method of one embodiment of the invention.
FIG. 3 is a schematic block diagram of a system of one embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. The execution subject in fig. 1 may be a server restart test optimization system.
As shown in fig. 1, the method includes:
step 110, the BMC judges whether the server is restarted and is clamped on a CPU initialization interface or not based on the potential signal state of the target pin or the communication state of the target pin and the BIOS;
and step 120, if the server reboots the card on the CPU initialization interface, skipping the CPU initialization interface by repeatedly training the target pin or switching the BIOS running state control system.
In order to facilitate understanding of the present invention, the server restart test optimization method provided by the present invention is further described below with reference to the principle of the server restart test optimization method of the present invention and the process of optimizing the server restart test in the embodiment.
A CPU server of AMD MILAN model generates a PSP card phenomenon in the restarting process, potential signals of three pins of power reset/power enable/clock are obtained through interaction of server firmware BMC hardware to judge whether the PSP signal is blocked, and the signal is not enough to judge whether an interface is blocked. The server firmware BMC judges through another channel, the power-on state is that the firmware BMC obtains a state, and the BMC judges whether a card is confirmed on a PSP interface by matching with the firmware BIOS whether communication transmission exists between the firmware BMC and the BMC in an effective time or not according to the length of the power-on time.
And judging that the AMD server has a PSP phenomenon, wherein the firmware BMC needs to assist in handling the PSP phenomenon. Firstly, the firmware BMC tries to recover hardware drive of a power reset/power enable/clock potential signal which cannot enter a BIOS system interface on a PSP interface for a plurality of times of trailing several potential signals, the recovery is tried for a plurality of times, if the hardware drive can be recovered, the hardware drive cannot be moved, other actions cannot be performed, another scheme cannot be recovered and selected, the firmware BMC is used for influencing the starting of a BIOS process of the firmware BIOS to disable the minimum system operation, and if the hardware drive can enter the interface, the firmware BMC needs to release the limitation on the BIOS.
Specifically, referring to fig. 2, the server restart test optimization method includes:
s1, the BMC determines whether the server is rebooted on the CPU initialization interface based on the potential signal state of the target pin or the communication state with the BIOS.
BMC judges whether the potential signals of the reset pin, the enable pin and the all-time pin which control the starting of the PCIE equipment are all in a normal state: if not, judging that the server rebooting card is in the CPU initialization interface; the BMC records the power-on time and judges whether communication transmission exists between the BMC and the BIOS before the power-on time reaches a specified time limit: if not, judging that the server reboots the card on the CPU initialization interface.
Specifically, restarting operation is carried out in an extreme environment of the AMD CPU server; in the process of powering on the server, the firmware BMC starts a monitoring mode;
the abnormality judgment is to control the PCIE equipment to start whether three potential reset/power enable/clock signals are abnormal or not, namely whether the three potential signals are normal or not, and whether the BMC has communication transmission judgment with the BMC within the effective time by matching with the firmware BIOS according to the length of the power-on time;
whether the card is in the PSP interface is judged by two ways.
And S2, if the server reboots the card on the CPU initialization interface, skipping over the CPU initialization interface by repeatedly training the target pin or switching the BIOS running state control system.
The BMC trains the potential state of the target pin for multiple times until the set times are reached; if the system is still clamped on the CPU initialization interface, the BIOS process influencing the startup of the BIOS firmware is forbidden, so that the BIOS keeps minimum system operation, and the forbidden setting is released after the CPU initialization interface is skipped.
Specifically, if the abnormal card is judged to be blocked on the PSP interface, the repair work is started, firstly, several potential signals are drawn for a plurality of times to try to recover the hardware drive of the card which can not enter the BIOS system interface, and if the card can not enter the BIOS system interface, the repair work is started; the BIOS process influencing the startup of the firmware BIOS is forbidden in a command protocol mode by the firmware BMC, minimum system operation is reserved, namely, the basic operation startup mode of the BIOS is reserved, and when the BIOS enters an interface, the rest initialization setting is released; and if the repair is successful, entering a BIOS system interface, and if the repair is unsuccessful, repeating the actions.
As shown in fig. 3, the system 300 includes:
the abnormality detection unit 310 is used for the BMC to judge whether the server is restarted and is clamped on a CPU initialization interface or not based on the potential signal state of the target pin or the communication state of the BIOS;
and an exception handling unit 320, configured to skip the CPU initialization interface by repeatedly training the target pin or switching the BIOS operating state control system if the server restart card is on the CPU initialization interface.
Optionally, as an embodiment of the present invention, the abnormality detecting unit includes:
the first detection module is used for the BMC to judge whether potential signals of the reset pin, the enable pin and the all-time pin which control the starting of the PCIE equipment are all in a normal state: if not, judging that the server rebooting card is in the CPU initialization interface;
the second detection module is used for recording the power-on time by the BMC and judging whether communication transmission exists between the BMC and the BIOS before the power-on time reaches a specified period: if not, judging that the server reboots the card on the CPU initialization interface.
Optionally, as an embodiment of the present invention, the exception handling unit includes:
the first processing module is used for the BMC to train the potential state of the target pin for multiple times until the set times is reached;
and the second processing module is used for forbidding the BIOS process influencing the startup of the BIOS firmware if the system is still clamped on the CPU initialization interface so as to ensure that the BIOS keeps minimum system operation, and removing the forbidding setting after skipping the CPU initialization interface.
Fig. 4 is a schematic structural diagram of a terminal 400 according to an embodiment of the present invention, where the terminal 400 may be used to execute the server restart test optimization method according to the embodiment of the present invention.
Among them, the terminal 400 may include: a processor 410, a memory 420, and a communication unit 330. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 420 may be used for storing instructions executed by the processor 410, and the memory 420 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 420, when executed by processor 410, enable terminal 400 to perform some or all of the steps in the method embodiments described below.
The processor 410 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 420 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, the processor 410 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 330, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Therefore, the server firmware BMC is used as the BMC of the server monitoring software, can be communicated with hardware to acquire some potential information of the hardware in the PSP process, and can be communicated with a BIOS system through a command protocol to judge; the BMC judges whether the server is abnormal in a PSP interface in a starting process through the interaction process of the BIOS software and the hardware, meanwhile, the BMC can interact with the BIOS system in a command protocol mode to assist in skipping the PSP interface to enter the BIOS system, and if the server cannot enter the BIOS system interface, the BMC can also control the hardware through control, so that the problem of the server being blocked on the PSP interface is avoided.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention.
The same and similar parts among the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.
In the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (8)

1. A server restart test optimization method is characterized by comprising the following steps:
the BMC judges whether the server is restarted and clamped on a CPU initialization interface or not based on the potential signal state of the target pin or the communication state of the target pin and the BIOS;
and if the server reboots the card on the CPU initialization interface, skipping over the CPU initialization interface by repeatedly training a target pin or switching the BIOS running state control system.
2. The method of claim 1, wherein the BMC determining whether the server reboot card is on the CPU initialization interface based on the potential signal state of the target pin or the communication state with the BIOS comprises:
BMC judges whether the potential signals of the reset pin, the enable pin and the all-time pin which control the starting of the PCIE equipment are all in a normal state: if not, judging that the server rebooting card is in the CPU initialization interface;
the BMC records the power-on time and judges whether communication transmission exists between the BMC and the BIOS before the power-on time reaches a specified time limit: if not, judging that the server reboots the card on the CPU initialization interface.
3. The method of claim 1, wherein skipping over the CPU initialization interface by repeatedly training a target pin or switching the BIOS run state control system if the server reboots the card on the CPU initialization interface comprises:
the BMC trains the potential state of the target pin for multiple times until the set times are reached;
if the system is still clamped on the CPU initialization interface, the BIOS process influencing the startup of the BIOS firmware is forbidden, so that the BIOS keeps minimum system operation, and the forbidden setting is released after the CPU initialization interface is skipped.
4. A server restart test optimization system, comprising:
the abnormality detection unit is used for judging whether the server is restarted and is clamped on a CPU initialization interface or not by the BMC based on the potential signal state of the target pin or the communication state of the BMC and the BIOS;
and the exception handling unit is used for skipping the CPU initialization interface by repeatedly training the target pin or switching the BIOS running state control system if the server restart card is on the CPU initialization interface.
5. The system according to claim 4, wherein the abnormality detection unit includes:
the first detection module is used for the BMC to judge whether potential signals of a reset pin, an enable pin and a pin all the time which are used for controlling the starting of the PCIE equipment are all in a normal state: if not, judging that the server rebooting card is in the CPU initialization interface;
the second detection module is used for recording the power-on time by the BMC and judging whether communication transmission exists between the BMC and the BIOS before the power-on time reaches a specified time limit: if not, judging that the server reboots the card on the CPU initialization interface.
6. The system of claim 4, wherein the exception handling unit comprises:
the first processing module is used for the BMC to train the potential state of the target pin for multiple times until the set times is reached;
and the second processing module is used for forbidding the BIOS process influencing the startup of the BIOS firmware if the system is still clamped on the CPU initialization interface so as to ensure that the BIOS keeps minimum system operation, and removing the forbidding setting after skipping the CPU initialization interface.
7. A terminal, comprising:
a processor;
a memory for storing instructions for execution by the processor;
wherein the processor is configured to perform the method of any one of claims 1-3.
8. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-3.
CN202210606667.0A 2022-05-31 2022-05-31 Server restart test optimization method, system, terminal and storage medium Pending CN114816886A (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210606667.0A CN114816886A (en) 2022-05-31 2022-05-31 Server restart test optimization method, system, terminal and storage medium

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Publication Number Publication Date
CN114816886A true CN114816886A (en) 2022-07-29

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