CN100511148C - CPU system starting method and system - Google Patents
CPU system starting method and system Download PDFInfo
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- CN100511148C CN100511148C CNB2007101245190A CN200710124519A CN100511148C CN 100511148 C CN100511148 C CN 100511148C CN B2007101245190 A CNB2007101245190 A CN B2007101245190A CN 200710124519 A CN200710124519 A CN 200710124519A CN 100511148 C CN100511148 C CN 100511148C
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Abstract
The invention discloses a start-up method of a CPU system and a system thereof. The start-up method comprises powering on a single board, starting a BOOT FLASH chip and running version software therein to boot the start-up of the CPU system, if the starting or running is failed, resetting the single board and starting another BOOT FLASH chip and running version software therein to boot the start up of the CPU system. The invention protects key points during the start-up process of the CPU system by adopting coordination of software and hardware through the two BOOT FLASH chips, when the start-up of the BOOT FLASH or the version software running is failed, the CPU start-up can be booted by restarting another BOOT FLASH, and the software of the two BOOT FLASH chips can be updated, so as to realize more reliable CPU system start-up and updating of the boot program.
Description
Technical field
The present invention relates to digital communication and field of computer technology, relate in particular to a kind of startup method and system of cpu system.
Background technology
Along with the high speed development of digital communication technology and computer technology, relative and MCU (one chip microcomputer, Micro Controller Unit), the application of CPU in the embedded intelligence system is more and more general.A typical CPU minimum system is by CPU, RAM (random access memory, random access memory), BOOT FLASH (being used to deposit the flash memory of start-up code, flash used to store boot code), peripheral communications interface, power supply and power management and veneer management logic are formed.CPU mainly is responsible for providing the MIPS (million to be unit, refer to the instruction number that per second is carried out, be used to represent the processing power of CPU, Million Instructions per second) of data processing and veneer control; RAM provides the memory block of code and data; Depositing necessary hardware configuration word of startup CPU and system bootstrap routine among the BOOTFLASH; The type of peripheral communications interface determines that according to practical application main interface has the RS232/RS485 interface, 100,000,000/gigabit Ethernet mouth etc.; Power unit comprises core voltage and IO voltage for system provides each voltage gradation, when the voltage electrifying timing sequence is had requirement, also will increase electric power management circuit; The veneer management logic mainly is responsible for control CPU electrification reset and decoding, and the veneer control register is provided.
Wherein, BOOT FLASH before dispatching from the factory, need with special-purpose cd-rom recorder the BOOT burning program in BOOT FLASH chip, then chips welding to veneer or be inserted in the BOOT socket of veneer.In the prior art, only use a slice BOOT chip on the veneer, there is following shortcoming: in case this BOOT FLASH chip damages or because the program code defective will cause CPU normally to start, and it is very inconvenient to the maintenance of veneer, especially when equipment is in the backcountry, the engineering maintenance personnel must arrive on-the-spot could the solution, have increased cost of equipment maintenance.
Summary of the invention
Technical matters to be solved by this invention provides a kind of startup method and system of cpu system, improves the normal reliability that starts of CPU.
For solving the problems of the technologies described above, the present invention is achieved by the following technical solutions:
A kind of startup method of cpu system, described method is: Board Power up, the version software that starts a slice BOOTFLASH and move wherein comes guiding CPU system start-up, if start or the operation failure, then with board resetting, start another sheet BOOT FLASH and operation version software wherein comes guiding CPU system start-up.
Wherein, described method also comprises: after the version software operation is normal, this version software is carried out online upgrading, redaction is write the BOOT FLASH that is just moving, and another BOOT FLASH is carried out regular verification according to this redaction, if incorrect, then by the version software among this BOOTFLASH of rule upgrading.
Wherein, described method further may further comprise the steps:
A, Board Power up read chip selection signal;
B, according to described chip selection signal, select a slice BOOT FLASH to start, if start failure, then write new chip selection signal, with board resetting, start BOOTFLASH and operation version software wherein according to new chip selection signal;
C, operation have started the version software among the BOOT FLASH, if the operation failure then writes new chip selection signal, with board resetting, start BOOT FLASH and operation version software wherein according to new chip selection signal.
Wherein, also comprise in the described method: the initial time starting BOOT FLASH writes handshaking information in the BOOT handshake register; Initial time at the operation version software writes handshaking information in the version handshake register; Simultaneously, judge that according to the handshaking information in BOOT handshake register and the version handshake register BOOT FLASH starts or whether the version software operation fails in the described method.
Wherein, described method also comprises: during the described chip selection signal of read-write, do not allow Reset Board.
Wherein, in the described method, determine the read-write clock of chip selection signal according to reset signal and major clock.
A kind of start-up system of cpu system comprises CPU, also comprises two identical BOOTFLASH chips, EPLD (electrically programmable logical device, electronic programmable logicdevice) chip;
Described BOOT FLASH chip links to each other respectively with CPU with the EPLD chip, is used to deposit version software, starts with guiding CPU;
Described EPLD chip links to each other respectively with two BOOT FLASH chips with CPU, is used to select a slice BOOT FLASH to start and moves wherein version software; BOOTFLASH start or the situation of version software operation failure under initiate the board resetting signal, select another BOOT FLASH to start and move wherein version software.
Wherein, described EPLD chip also is used for after the version software upgrading of current operation redaction being write the BOOT FLASH that is just moving, and another BOOT FLASH is carried out regular verification according to this redaction, if incorrect, then by the version software among this BOOT FLASH of rule upgrading.
Wherein, described start-up system also comprises NVRAM (non-volatile readable memory write, non-volatile random access memory) chip, with the EPLD chip interconnect, is used to deposit chip selection signal, to indicate the BOOT FLASH chip that will start;
Simultaneously, described EPLD chip is selected BOOT FLASH chip according to this chip selection signal, and writes new chip selection signal to the NVRAM chip when BOOT FLASH startup or version software operation failure.
Wherein, described EPLD chip comprises NVRAM interface module, two BOOT control module;
Described NVRAM interface module links to each other with the NVRAM chip, is used for reading and writing the chip selection signal of NVRAM chip;
Described pair of BOOT control module links to each other with NVRAM interface module, two BOOT FLASH chips, be used for starting BOOT FLASH chip and moving its version software according to chip selection signal, when starting or move failure, write new chip selection signal to the NVRAM chip, initiate the board resetting signal by the NVRAM interface module; Also be used for version software upgrading according to two BOOT FLASH chips of control.
Wherein, described EPLD chip also comprises register realization module, clock generation module, NVRAM protection module;
Described register realizes that module links to each other with two BOOT control modules, comprises BOOT handshake register and version handshake register, is used to deposit handshaking information; Simultaneously, the described pair of BOOT control module also is used at the initial time that BOOT FLASH starts and version software moves, in BOOT handshake register and version handshake register, deposit handshaking information respectively, judge that according to this handshaking information BOOT FLASH starts or whether the version software operation fails;
Described clock generation module links to each other with the NVRAM interface module with two BOOT control modules, is used for determining the read-write operation clock of NVRAM chip and the time-out time point of respectively shaking hands according to reset signal and major clock;
Described NVRAM protection module links to each other with the NVRAM interface module, is used for setting the time of reading NVRAM chip chip selection signal.
The present invention has following beneficial effect:
The mode that the present invention adopts software and hardware to cooperate; by using two BOOT FLASH chips; key point in the cpu system start-up course is protected; when starting failure or version software operation failure, BOOT FLASH all can come guiding CPU to start by restarting another BOOT FLASH; and can upgrade to the software of two BOOT FLASH chips, realized that more reliable cpu system starts and the upgrading of boot.
Description of drawings
Fig. 1 is the structural drawing of start-up system of the present invention;
Fig. 2 is the system construction drawing of the embodiment of the invention;
Fig. 3 is the method flow diagram of the embodiment of the invention.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments:
The present invention has realized a kind of start-up system of cpu system, and as shown in Figure 1, this start-up system comprises: CPU, BOOT FLASH chip 1 and 2, EPLD chip.
Wherein, BOOT FLASH chip 1 all links to each other respectively with CPU with the EPLD chip with 2, is used to deposit version software, starts with guiding CPU;
The EPLD chip links to each other respectively with two BOOT FLASH chips with CPU, is used to select a slice BOOT FLASH to start and moves wherein version software; BOOT FLASH start or the situation of version software operation failure under initiate the board resetting signal, select another BOOTFLASH to start and move wherein version software.
See also Fig. 2, this figure is an embodiment of said system, comprises CPU, EPLD chip, BOOT FLASH chip 1 and 2, NVRAM chip; Comprise register realization module, clock generation module, NVRAM protection module, two BOOT control module, NVRAM interface module in the EPLD chip again.To the annexation and the function of each ingredient be described in detail below:
CPU: address, data, control bus are provided.
BOOT FLASH chip 1 is with 2: be two identical BOOT FLASH chips, link to each other respectively with CPU with the EPLD chip, required boot when being used to deposit CPU and starting.When dispatching from the factory, with the boot of the good identical version of burning in two BOOT; As after the BOOT upgrading, two BOOT stored be respectively the boot of new and old different editions, after the redaction operation is normal, carry out from the legacy version to the redaction synchronously.
NVRAM chip: with the EPLD chip interconnect, be used to deposit chip selection signal, to indicate the BOOT FLASH chip that will start.
NVRAM interface module: link to each other with the NVRAM chip, with the read-write interface of logical code realization with the NVRAM chip.Board Power up or when resetting reads the particular address byte among the NVRAM, and promptly chip selection signal starts the indication that chip is selected as current BOOT.
Two BOOT control modules: link to each other with NVRAM interface module, BOOT FLASH chip 1 and 2, CPU, be used for starting also operation version software wherein of BOOT FLASH chip 1 or 2 according to chip selection signal, starting or writing after by of the selection position negate of NVRAM interface module during the operation failure the NVRAM chip, as new chip selection signal, initiate the board resetting signal afterwards; Also be used to control the upgrading of the version software of BOOT FLASH chip 1 and 2.
Clock generation module: link to each other with the NVRAM interface module with two BOOT control modules, be used for determining the read-write operation clock of NVRAM chip and the time-out time point of respectively shaking hands according to reset signal and major clock.
The NVRAM protection module: linking to each other with the NVRAM interface module, mainly is agreement NVRAM time for reading, during doing the NVRAM read-write operation, does not allow to reset, and avoids not reading the startup chip and selects the position just to reset, thereby avoid entering the endless loop that constantly resets.
Register is realized module: link to each other with two BOOT control modules, mainly provide the interface of EPLD and CPU, realize the register that two BOOT control modules need, comprise BOOT handshake register and version handshake register, be used to deposit handshaking information.The application process of this module is: the above-mentioned pair of BOOT control module is at BOOT FLASH starts and version software moves initial time, in BOOT handshake register and version handshake register, deposit handshaking information respectively, according to whether there being handshaking information to judge that BOOT FLASH starts or whether the version software operation fails in the register in the time-out time scope of shaking hands of clock generation module settings.
The present invention also provides a kind of startup method of cpu system, this method is: Board Power up, the version software that starts a slice BOOT and move wherein starts cpu system, if start or the operation failure, then with board resetting, start another sheet BOOT and operation version software wherein starts cpu system.
Accompanying drawing 3 is an embodiment of said method, may further comprise the steps:
301, Board Power up or reset, EPLD reads chip selection signal in the NVRAM chip by its NVRAM interface module, according to this chip selection signal BOOT FLASH chip 1 or 2 is done the sheet choosing, which BOOT FLASH this has determined to start, and software just begins from selected BOOT FLASH operation boot.
302, at the initial time that starts selected BOOT FLASH, EPLD visit BOOT handshake register is to wherein writing handshaking information.According to whether there being handshaking information to judge whether EPLD and BOOT FLASH shake hands in the register in the time-out time scope of shaking hands of clock generation module settings,, then continue next step if it is normal to shake hands; Undesired if shake hands, then to the negate of NVRAM zone bit, and initiate the board resetting signal, turn back to step 301, start another one BOOTFLASH.
303, operation has started the version software among the BOOT FLASH, and at the initial time of operation, EPLD visit version handshake register is to wherein writing handshaking information.According in the predetermined time-out time scope of shaking hands, whether having handshaking information to judge whether EPLD and version software shake hands in the register,, then continue next step if it is normal to shake hands; Undesired if shake hands, then to the negate of NVRAM zone bit, initiate reset signal, turn back to step 301, start another one BOOT FLASH.In above-mentioned steps, during the read-write chip selection signal, do not allow Reset Board, avoid not reading the startup chip and select the position just to reset, thereby avoid entering the endless loop that constantly resets.
304, after the version software operation normally, this version software is carried out online upgrading, redaction is write the BOOT FLASH that is just moving, and another BOOT FLASH is carried out regular verification according to this redaction, if incorrect, then by the version software among this BOOT FLASH of rule upgrading.
In this step, the present invention has realized writing the interface of BOOT FLASH in version software, calls during for the boot of the BOOT FLASH that need upgrade on the backstage, two effects is arranged: the BOOT FLASH boot of 1) can upgrading; 2) after the upgrading, read BOOT FLASH boot version,, illustrate that the boot after the upgrading has problem, then can return back to the preceding version of upgrading if discovery remains the preceding version of upgrading; 3) after the upgrading, read BOOT FLASH boot version,, illustrate that the boot after the upgrading is no problem, then can also upgrade other a slice BOOT FLASH if discovery is the version after the upgrading.
In the said method, determine the read-write operation clock of NVRAM chip and the time-out time point of respectively shaking hands according to reset signal and major clock.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1, a kind of startup method of cpu system, it is characterized in that, described method is: Board Power up, the version software that starts a slice BOOT FLASH and move wherein comes guiding CPU system start-up, if start or the operation failure, then with board resetting, start another sheet BOOTFLASH and operation version software wherein comes guiding CPU system start-up; After the version software operation is normal, this version software is carried out online upgrading, redaction is write the BOOTFLASH that is just moving, and another BOOT FLASH is carried out regular verification according to this redaction, if incorrect, then by the version software among this BOOT FLASH of rule upgrading.
2, the startup method of cpu system as claimed in claim 1 is characterized in that, the step in the described method before the normal operation of version software further may further comprise the steps:
A, Board Power up read chip selection signal;
B, according to described chip selection signal, select a slice BOOT FLASH to start, if start failure, then write new chip selection signal, with board resetting, start BOOT FLASH and operation version software wherein according to new chip selection signal;
C, operation have started the version software among the BOOT FLASH, if the operation failure then writes new chip selection signal, with board resetting, start BOOTFLASH and operation version software wherein according to new chip selection signal.
3, the startup method of cpu system as claimed in claim 2 is characterized in that, also comprises in the described method: the initial time starting BOOT FLASH writes handshaking information in the BOOT handshake register; Initial time at the operation version software writes handshaking information in the version handshake register; Simultaneously, judge that according to the handshaking information in BOOT handshake register and the version handshake register BOOT FLASH starts or whether the version software operation fails in the described method.
4, the startup method of cpu system as claimed in claim 2 is characterized in that, described method also comprises: during the described chip selection signal of read-write, do not allow Reset Board.
5, the startup method of cpu system as claimed in claim 3 is characterized in that, in the described method, determines the read-write clock of chip selection signal according to reset signal and major clock.
6, a kind of start-up system of cpu system comprises CPU, it is characterized in that, also comprises two identical BOOT FLASH chips, the EPLD chip;
Described BOOT FLASH chip links to each other respectively with CPU with the EPLD chip, is used to deposit version software, starts with guiding CPU;
Described EPLD chip links to each other respectively with two BOOT FLASH chips with CPU, is used to select a slice BOOT FLASH to start and moves wherein version software; BOOT FLASH start or the situation of version software operation failure under initiate the board resetting signal, select another BOOT FLASH to start and move wherein version software; Described EPLD chip also is used for after the version software upgrading of current operation redaction being write the BOOT FLASH that is just moving, and another BOOT FLASH is carried out regular verification according to this redaction, if incorrect, then by the version software among this BOOT FLASH of rule upgrading.
7, the start-up system of cpu system as claimed in claim 6 is characterized in that, described start-up system also comprises the NVRAM chip, with the EPLD chip interconnect, is used to deposit chip selection signal, to indicate the BOOT FLASH chip that will start;
Simultaneously, described EPLD chip is selected BOOT FLASH chip according to this chip selection signal, and writes new chip selection signal to the NVRAM chip when BOOT FLASH startup or version software operation failure.
8, the start-up system of cpu system as claimed in claim 7 is characterized in that, described EPLD chip comprises NVRAM interface module, two BOOT control module;
Described NVRAM interface module links to each other with the NVRAM chip, is used for reading and writing the chip selection signal of NVRAM chip;
Described pair of BOOT control module links to each other with NVRAM interface module, two BOOTFLASH chips, be used for starting BOOT FLASH chip and moving its version software according to chip selection signal, when starting or move failure, write new chip selection signal to the NVRAM chip, initiate the board resetting signal by the NVRAM interface module; Also be used for version software upgrading according to two BOOT FLASH chips of control.
9, the start-up system of cpu system as claimed in claim 8 is characterized in that, described EPLD chip also comprises register realization module, clock generation module, NVRAM protection module;
Described register realizes that module links to each other with two BOOT control modules, comprises BOOT handshake register and version handshake register, is used to deposit handshaking information; Simultaneously, the described pair of BOOT control module also is used at the initial time that BOOT FLASH starts and version software moves, in BOOT handshake register and version handshake register, deposit handshaking information respectively, judge that according to this handshaking information BOOT FLASH starts or whether the version software operation fails;
Described clock generation module links to each other with the NVRAM interface module with two BOOT control modules, is used for determining the read-write operation clock of NVRAM chip and the time-out time point of respectively shaking hands according to reset signal and major clock;
Described NVRAM protection module links to each other with the NVRAM interface module, is used for setting the time of reading NVRAM chip chip selection signal.
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| CNB2007101245190A CN100511148C (en) | 2007-11-12 | 2007-11-12 | CPU system starting method and system |
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| CNB2007101245190A CN100511148C (en) | 2007-11-12 | 2007-11-12 | CPU system starting method and system |
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| CN101169727A CN101169727A (en) | 2008-04-30 |
| CN100511148C true CN100511148C (en) | 2009-07-08 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102902556A (en) * | 2012-09-06 | 2013-01-30 | 深圳市共进电子股份有限公司 | Multistage boot load method of embedded equipment |
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| CN102830986A (en) * | 2011-06-17 | 2012-12-19 | 中兴通讯股份有限公司 | Method and device for turning on system in double-BOOT program condition |
| CN102736941A (en) * | 2012-07-03 | 2012-10-17 | 江西省电力公司信息通信分公司 | Method for automatically starting central processing unit (CPU) system by utilizing double flashes |
| CN102819444B (en) * | 2012-08-27 | 2015-09-02 | 新邮通信设备有限公司 | The method and system of loading procedure in a kind of base station |
| CN105278974A (en) * | 2014-06-30 | 2016-01-27 | 深圳市中兴微电子技术有限公司 | Chip starting method and device |
| CN105068800B (en) * | 2015-07-31 | 2018-09-14 | 深圳市华星光电技术有限公司 | A kind of method of download configuration code, system and timer/counter control register |
| CN105406981A (en) * | 2015-10-20 | 2016-03-16 | 上海斐讯数据通信技术有限公司 | System and method used for upgrading router |
| CN107766090A (en) * | 2016-08-15 | 2018-03-06 | 天津科畅慧通信息技术有限公司 | A kind of method and device for assisting CPU to start based on EPLD |
| CN109273031B (en) * | 2018-10-09 | 2021-07-27 | 珠海格力电器股份有限公司 | Flash decoding circuit and flash decoding method |
| CN111124826A (en) * | 2019-12-20 | 2020-05-08 | 深圳市源拓光电技术有限公司 | Method and system for protecting normal power-on start of CPU |
| CN112162794B (en) * | 2020-09-30 | 2023-03-28 | 新华三大数据技术有限公司 | Single board starting method, device, single board and network equipment |
| CN114655140B (en) * | 2022-03-15 | 2024-03-26 | 东软睿驰汽车技术（沈阳）有限公司 | Vehicle starting control method and related device |
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| CN1295903C (en) * | 2002-11-18 | 2007-01-17 | 华为技术有限公司 | A safe system starting method |
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Cited By (2)
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| CN102902556B (en) * | 2012-09-06 | 2016-06-01 | 深圳市共进电子股份有限公司 | The multistage boot load method of a kind of embedded equipment |
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| CN101169727A (en) | 2008-04-30 |
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