CN112558673A - Timing control circuit and timing control system - Google Patents
Timing control circuit and timing control system Download PDFInfo
- Publication number
- CN112558673A CN112558673A CN202110190710.5A CN202110190710A CN112558673A CN 112558673 A CN112558673 A CN 112558673A CN 202110190710 A CN202110190710 A CN 202110190710A CN 112558673 A CN112558673 A CN 112558673A
- Authority
- CN
- China
- Prior art keywords
- module
- input
- switch
- output end
- input end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
The invention provides a timing control circuit and a timing control system, wherein the timing control circuit comprises an input control module, a switch module, a storage capacitor, a constant current source charging module, a comparison module and a triggering and latching module; the input control module comprises a first input end, a second input end, a third input end, a first output end and a second output end, and the first input end of the input control module is used as the input end of the timing control circuit; the switch module comprises a first control end, a second control end, a reference voltage input end, a grounding end and an input end; the first control end of the switch module is connected with the first output end of the input control module, and the second control end of the switch module is connected with the second output end of the input control module; the timing control circuit and the timing control system provided by the invention do not use a high-frequency clock circuit as a basic timing unit, thereby reducing the noise coupling, interference and power consumption of the high-frequency clock circuit to an analog circuit.
Description
Technical Field
The present invention relates to timing control, and more particularly to a timing control circuit and a timing control system.
Background
The timing control circuit is widely applied to various digital-analog hybrid circuits, for example, in a weak signal detection system of a sensor, the timing control circuit is applied to closed-loop feedback control, and can be matched with a variable gain module to form a closed-loop automatic gain control circuit, so that the circuit automatically adjusts the gain with a certain time constant or frequency according to the existing environmental interference and noise level, and the detection sensitivity is improved. In digital circuitry applications, it is sometimes desirable to have the system memorize the time spent in the previous state in order to later adjust the timing. A timing control circuit is also required at this time.
The traditional timing control circuit mostly adopts a digital mode, namely, an accurate clock source circuit is provided, and a complex timing function is realized through a digital logic mode. In the case of low timing accuracy, a certain timing control function may be realized by using an analog circuit to avoid using a high-frequency clock circuit.
In a conventional digital logic type timing control circuit, a high-frequency clock circuit is required to be used as a timing counting basic unit, and when the timing control circuit is applied to an analog circuit, noise coupling and interference to a high-performance analog circuit are easily caused due to substrate coupling and power supply coupling.
Disclosure of Invention
According to the timing control circuit and the timing control system provided by the embodiment of the invention, a high-frequency clock circuit is not used as a basic timing unit, so that the timing control circuit is not subjected to noise coupling and interference of the high-frequency clock circuit.
In a first aspect, an embodiment of the present invention provides a timing control circuit, including an input control module, a switch module, a storage capacitor, a constant current source charging module, a comparison module, and a triggering and latching module;
the input control module comprises a first input end, a second input end, a third input end, a first output end and a second output end, and the first input end of the input control module is used as the input end of the timing control circuit;
the switch module comprises a first control end, a second control end, a reference voltage input end, a grounding end and an input end; the first control end of the switch module is connected with the first output end of the input control module, the second control end of the switch module is connected with the second output end of the input control module, and the reference voltage input end of the switch module is connected with a reference voltage signal;
the storage capacitor is connected with the switch module and used for keeping the potentials at two ends of the switch module when the working state of the switch module is switched;
the constant current source charging module comprises a first power supply input end, a second power supply input end, a grounding end, a control end and a charging end; a first power supply input end of the constant current source charging module is connected with a first power supply, a second power supply input end of the constant current source charging module is connected with a second power supply, and a charging end of the constant current source charging module is connected with an input end of the switch module; the constant current source charging module is used for charging the charging end under the control of the control end of the constant current source charging module;
the comparison module comprises a first input end, a second input end, a first output end and a second output end, the first input end of the comparison module is connected with the reference voltage signal, the second input end of the comparison module is connected with the charging end of the constant current source charging module, the first output end of the comparison module is used as the output end of the timing control circuit, and the second output end of the comparison module is opposite to the first output end of the comparison module in potential;
the trigger and latch module comprises a trigger end, a first output end and a second output end, the trigger end of the trigger and latch module is connected with the second output end of the comparison module, the first output end of the trigger and latch module is connected with the second input end of the input control module, and the second output end of the trigger and latch module is connected with the third input end of the input control module.
Optionally, the constant current source charging module further includes a first transistor and a second transistor;
the first power supply is connected with a first power supply input end of the constant current source charging module, and the second power supply is connected with a second power supply input end of the constant current source charging module;
the grid electrode of the first transistor is connected with the first output end of the comparison module, the first pole of the first transistor is connected with the first pole of the second transistor, and the second pole of the first transistor is the control end of the constant current source charging module and is connected with the first power supply;
the grid electrode of the second transistor is connected with the second pole of the first transistor, the second pole of the second transistor is the charging end of the constant current source charging module, and the first pole of the second transistor is grounded.
Optionally, the switch module includes a first switch, a second switch, a third switch and a fourth switch;
a first end of the first switch is used as an input end of the switch module, a second end of the first switch is respectively connected with a first end of the storage capacitor and a first end of the second switch, and a control end of the first switch is connected with a second output end of the input control module;
a second end of the second switch is connected with a reference voltage signal, and a control end of the second switch is connected with a first output end of the input control module;
a first end of the third switch is connected with a first end of the first switch, a second end of the third switch is respectively connected with a second end of the storage capacitor and a first end of the fourth switch, and a control end of the third switch is connected with a first output end of the input control module;
and the second end of the fourth switch is grounded, and the control end of the fourth switch is connected with the second output end of the input control module.
Optionally, the first switch, the second switch, the third switch, and the fourth switch are transistors.
Optionally, the triggering and latching module includes a trigger and a latch; the first end of the trigger is the trigger end of the trigger and latch module, and the second end of the trigger is respectively connected with the first input end and the second input end of the latch.
Optionally, the flip-flop is a D flip-flop, a first end of the flip-flop is connected to the second output end of the comparison module, a second end of the flip-flop is connected to the input end of the latch, and a third end of the flip-flop is connected to the fourth end of the flip-flop.
Optionally, the latch includes a third inverter, a first nor gate, and a second nor gate;
the input end of the third inverter is connected with the second end of the trigger, and the output end of the third inverter is connected with the first input end of the second NOR gate;
a first input end of the first nor gate is connected with a second end of the trigger, a second input end of the first nor gate is connected with an output end of the second nor gate, and an output end of the first nor gate is connected with a second input end of the input control module;
and the second input end of the second NOR gate is connected with the output end of the first NOR gate, and the output end of the second NOR gate is connected with the third input end of the input control module.
Optionally, the input control module includes a fourth inverter, a fifth inverter, a first nand gate, a second nand gate, a third nand gate, a fourth nand gate, a fifth nand gate, and a sixth nand gate;
the input end of the fourth inverter is the input end of the timing control circuit, and the output end of the fourth inverter is connected with the input end of the fifth inverter;
the first input end of the first nand gate is connected with the output end of the first nor gate, the second input end of the first nand gate is connected with the output end of the fourth inverter, the first input end of the second nand gate is connected with the output end of the second nor gate, the second input end of the second nand gate is connected with the output end of the fifth inverter, the first input end of the third nand gate is connected with the output end of the first nand gate, the second input end of the third nand gate is connected with the output end of the second nand gate, and the output end of the third nand gate is connected with the first control end of the switch module;
the first input end of the fourth nand gate is connected with the output end of the first nor gate, the second input end of the fourth nand gate is connected with the output end of the fifth inverter, the first input end of the fifth nand gate is connected with the output end of the second nor gate, the second input end of the fifth nand gate is connected with the output end of the fourth inverter, the first input end of the sixth nand gate is connected with the output end of the fourth nand gate, the second input end of the sixth nand gate is connected with the output end of the fifth nand gate, and the output end of the sixth nand gate is connected with the second control end of the switch module.
Optionally, the comparing module includes a comparator, a first inverter and a second inverter;
a first input end of the comparator is connected with the reference voltage signal, a second input end of the comparator is connected with a charging end of the constant current source charging module, and an output end of the comparator is connected with an input end of the first inverter;
the output end of the first phase inverter is respectively connected with the trigger end of the trigger and latch module and the input end of the second phase inverter;
and the output end of the second phase inverter is the output end of the timing control circuit.
In a second aspect, an embodiment of the present invention further provides a timing control system, including the timing control circuit provided in the first aspect.
The timing control circuit and the timing control system provided by the embodiment of the invention control the first output end and the second output end of the trigger and latch module through the second output end of the comparison module, thereby controlling the first output end and the second output end of the input control module, further controlling the first control end and the second control end of the switch module, controlling the connection between the first end or the second end of the storage capacitor and the charging end of the constant current source charging module through the disconnection and the closing of the first control end and the second control end of the switch module, further controlling the potential of the charging end of the constant current source charging module according to the property of keeping the electric quantity of the storage capacitor unchanged, simultaneously controlling the charging condition of the charging end by the control end of the constant current source charging module through the output level signal of the first output end of the comparison module, and deriving the last charging time through calculating the last charging time because the electric quantity of the current charging is equal to the last charging electric quantity, thereby playing a timing role. According to the timing control circuit and the timing control system provided by the embodiment of the invention, a high-frequency clock circuit is not used as a basic timing unit, so that the timing control circuit is not subjected to noise coupling and interference of the high-frequency clock circuit.
Drawings
Fig. 1 is a schematic structural diagram of a timing control circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another timing control circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another timing control circuit according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad invention. It should be further noted that, for convenience of description, only some structures, not all structures, relating to the embodiments of the present invention are shown in the drawings.
Fig. 1 is a schematic structural diagram of a timing control circuit according to an embodiment of the present invention, and referring to fig. 1, the timing control circuit according to the embodiment of the present invention includes an input control module 110, a switch module 120, a storage capacitor C, a constant current source charging module 130, a comparison module 140, and a trigger and latch module 150; the input control module 110 includes a first input end, a second input end, a third input end, a first output end and a second output end, and the first input end of the input control module 110 is used as the input end of the timing control circuit; the switch module 120 includes a first control terminal, a second control terminal, a reference voltage input terminal, a ground terminal, and an input terminal; a first control end of the switch module 120 is connected with a first output end of the input control module 110, a second control end of the switch module 120 is connected with a second output end of the input control module 110, and a reference voltage input end of the switch module 120 is connected with a reference voltage signal Vref; the storage capacitor C is connected to the switch module 120, and is configured to maintain the potentials at two ends of the storage capacitor C when the operating state of the switch module 120 is switched; the constant current source charging module 130 includes a first power input terminal, a second power input terminal, a ground terminal, a control terminal, and a charging terminal; a first power supply input end of the constant current source charging module 130 is connected with a first power supply, a second power supply input end of the constant current source charging module 130 is connected with a second power supply, and a charging end of the constant current source charging module 130 is connected with an input end of the switch module 120; the constant current source charging module 130 is used for charging the charging terminal under the control of the control terminal thereof; the comparison module 140 includes a first input end, a second input end, a first output end and a second output end, the first input end of the comparison module 140 is connected to the reference voltage signal Vref, the second input end of the comparison module 140 is connected to the charging end of the constant current source charging module 130, the first output end of the comparison module 140 is used as the output end of the timing control circuit, and the second output end of the comparison module 140 is opposite in potential to the first output end of the comparison module 140; the trigger and latch module 150 includes a trigger terminal, a first output terminal and a second output terminal, the trigger terminal of the trigger and latch module 150 is connected to the second output terminal of the comparison module 140, the first output terminal of the trigger and latch module 150 is connected to the second input terminal of the input control module 110, and the second output terminal of the trigger and latch module 150 is connected to the third input terminal of the input control module 110.
Specifically, the level signals output by the first output terminal and the second output terminal of the input control module 110 are opposite and controlled by the level signals input by the first input terminal, the second input terminal, and the third input terminal of the input control module 110, and when the timing control circuit is initialized, the first control terminal of the switch module 120 is turned off and the second control terminal is turned on. Illustratively, when a low level signal is input to the first input terminal of the control module 110 and an electrical signal input to the second input terminal of the comparison module 140 is 0V, the voltage of the charging terminal of the constant current source charging module 130 is also 0V, which is lower than the reference voltage signal Vref input to the first input terminal of the comparison module 140, then the first output terminal of the comparison module 140 outputs a high level signal, the control terminal of the constant current source charging module 130 controls the second power source to start charging the charging terminal until the electrical signal input to the second input terminal of the comparison module 140 is equal to the reference voltage signal Vref input to the first input terminal of the comparison module 140, the first terminal of the storage capacitor C is connected to the charging terminal of the constant current source charging module 130 when the first control terminal of the switch module 120 is opened and the second control terminal is closed, the second terminal of the storage capacitor is grounded, so that when the charging terminal is charged to Vref by the second power source, the stored electric quantity of the storage capacitor C is also Vref, the second output terminal of the comparison module 140 outputs a high level signal, so that the first output terminal of the trigger and latch module 150 is converted from a low level signal to a high level signal, the second output terminal of the trigger and latch module 150 is converted from a high level signal to a low level signal, at this time, the level signal output by the first output terminal of the input control module 110 can close the first control terminal of the switch module 120, the level signal output by the second output terminal of the input control module 110 can open the second control terminal of the switch module 120, at this time, the first terminal of the storage capacitor C is connected to the reference voltage signal Vref, the second terminal of the storage capacitor C is connected to the charging terminal of the constant current source charging module 130, in order to keep the stored electric quantity unchanged, the potential of the second terminal of the storage capacitor C is 0V, at this time, the potential of the charging terminal of the constant current source charging module 130 is, at this time, the control terminal of the constant current source charging module 130 continues to control the second power source to charge the charging terminal until the electrical signal input by the second input terminal of the comparing module 140 is equal to the reference voltage signal Vref input by the first input terminal, and the amount of electricity charged at this time is equal to the amount of electricity charged at the last time, so that the first charging time can be obtained by calculating the second charging time.
The timing control circuit provided by the embodiment of the invention controls the first output end and the second output end of the trigger and latch module through the second output end of the comparison module, thereby controlling the first output end and the second output end of the input control module, further controlling the first control end and the second control end of the switch module, controlling the connection between the first end or the second end of the storage capacitor and the charging end of the constant current source charging module through the disconnection and the closing of the first control end and the second control end of the switch module, further controlling the potential of the charging end of the constant current source charging module according to the property of keeping the electric quantity unchanged of the storage capacitor, and simultaneously enabling the control end of the constant current source charging module to control the charging condition of the charging end through the output level signal of the first output end of the comparison module, wherein the charging electric quantity of the current time is equal to the charging quantity of the last time, therefore, the charging time of the, thereby playing a timing role. The timing control circuit provided by the embodiment of the invention does not use a high-frequency clock circuit as a basic timing unit, so that the timing control circuit is not subjected to noise coupling and interference of the high-frequency clock circuit.
Fig. 2 is a schematic structural diagram of another timing control circuit according to an embodiment of the present invention, and optionally, referring to fig. 2, the constant current source charging module 130 further includes a first transistor N1 and a second transistor N2; the first power supply is connected with the first power supply input end of the constant current source charging module 130, and the second power supply is connected with the second power supply input end of the constant current source charging module 130; the gate of the first transistor N1 is connected to the first output terminal of the comparing module 140, the first pole of the first transistor N1 is connected to the first pole of the second transistor N2, and the second pole of the first transistor N1 is the control terminal of the constant current source charging module 130 and is connected to the first power supply; the gate of the second transistor N2 is connected to the second pole of the first transistor N1, the second pole of the second transistor N2 is the charging terminal of the constant current source charging module 130, and the first pole of the second transistor N2 is grounded.
Specifically, the first transistor N1 and the second transistor N2 may be both N-type transistors or both P-type transistors, and the embodiment of the invention is described by taking N-type transistors as an example. Illustratively, the first transistor N1 and the second transistor N2 are both N-type transistors, when the reference voltage signal Vref input by the first input terminal of the comparison module 140 is greater than the voltage signal input by the second input terminal of the comparison module 140, the first output terminal of the comparison module 140 outputs a high level signal, since the gate of the first transistor N1 is connected to the first output terminal of the comparison module 140, the first transistor N1 is turned on, the gate voltage of the second transistor is grounded after the first transistor N1 is turned on, the second transistor N2 is turned off, and the second power source charges the charging terminal.
Optionally, with continued reference to fig. 2, the switch module 120 includes a first switch M1, a second switch M2, a third switch M3, and a fourth switch M4; a first terminal of the first switch M1 is connected to the second pole of the second transistor N2, a second terminal of the first switch M1 is connected to the first terminal of the storage capacitor C and the first terminal of the second switch M2, respectively, and a control terminal of the first switch M1 is connected to the second output terminal of the input control module 110; a second end of the second switch M2 is connected to the reference voltage signal Vref, and a control end of the second switch M2 is connected to the first output end of the input control module 110; a first end of the third switch M3 is connected to a first end of the first switch M1, a second end of the third switch M3 is connected to a second end of the storage capacitor C and a first end of the fourth switch M4, respectively, and a control end of the third switch M3 is connected to a first output end of the input control module 110; the second terminal of the fourth switch M4 is grounded, and the control terminal of the fourth switch M4 is connected to the second output terminal of the input control module 110.
Specifically, when a low level signal is input to the first control terminal of the switch module 120 and a high level signal is input to the second control terminal, the first switch M1 and the fourth switch M4 are closed, the second switch M2 and the third switch M3 are opened, the first terminal of the storage capacitor C is connected to the charging terminal of the constant current source charging module 130, the second terminal of the storage capacitor C is grounded, when a voltage signal input to the second input terminal of the comparison module 140 is equal to a reference voltage signal Vref input to the first input terminal of the comparison module 140, the stored power of the storage capacitor C is Vref, and a level signal output from the second output terminal of the comparison module 140 changes, when level signals output from the first output terminal and the second output terminal of the trigger and latch module 150 make the first control terminal of the switch module 120 high level and the second control terminal low level, when the first switch M1 and the fourth switch M4 are opened, after the third switch M3 and the second switch M2 are closed, and the second switch M2 is closed, the first end of the storage capacitor C is connected to the reference voltage signal Vref, since the stored energy of the storage capacitor C cannot change immediately, the second end of the storage capacitor C is forced to be 0V, since the charging end of the constant current source charging module 130 is connected to the first end of the third switch M3, the voltage of the charging end of the constant current source charging module 130 is forced to be 0V, at this time, the voltage signal input from the second end of the comparison module 140 is still smaller than the voltage signal input from the first input end of the comparison module 140, the second power source continues to be the charging end of the constant current source charging module 130, and the charging time at this time is calculated according to the charging time calculation formula:
wherein C is the size of the storage capacitor C, VREF is the amount of electricity charged by the storage capacitor C, I charge VREF is equal to the reference voltage signal VREF for the current passing in the storage capacitor C.
The last time the second input of the comparator module 140 increased from 0V to Vref charge was known by recording the charge time that the second input of the comparator module 140 increased from 0V to Vref charge at that time. Therefore, it can be known that the time when the level signal output from the first output terminal of the comparing module 140 is inverted is T1 when the level signal of the timing control circuit is not changed.
Optionally, the first switch, the second switch, the third switch and the fourth switch are transistors.
Specifically, the first switch, the second switch, the third switch and the fourth switch are N-type transistors, and are turned on under the control of a high level and turned off under the control of a low level signal.
Optionally, fig. 3 is a schematic structural diagram of another timing control circuit according to an embodiment of the present invention, and referring to fig. 3, the flip-flop and latch module includes a flip-flop 151 and a latch 152, a first end of the flip-flop 151 is a trigger end of the flip-flop and latch module 150, and a second end of the flip-flop 151 is respectively connected to a first input end and a second input end of the latch 152.
Specifically, the flip-flop 151 is a D flip-flop, and the latch 152 includes one inverter and two nor gates.
Optionally, with continued reference to fig. 3, a first terminal of the flip-flop 151 is connected to the second output terminal of the comparing module 140, a second terminal of the flip-flop 151 is connected to the input terminal of the latch 152, and a third terminal of the flip-flop 151 is connected to the fourth terminal of the flip-flop 151.
Specifically, when the output signal of the second terminal of the flip-flop 151 is a high level signal, the first terminal of the flip-flop 151 is a clock signal terminal of the flip-flop 151, and the second terminal of the flip-flop 151 is an output terminal of the flip-flop 151, when the level signal output by the second output terminal of the comparison module 140 is converted from a low level signal to a high level signal, the first terminal of the flip-flop 151 provides the clock signal for the flip-flop 151, and the level signal output by the second terminal of the flip-flop 151 is inverted and changed from the original high level signal to the low level signal.
Optionally, with continued reference to fig. 3, the comparison module 140 includes a comparator, a first inverter F1, and a second inverter F2; a first input end of the comparator is connected with a reference voltage signal Vref, a second input end of the comparator is connected with a second pole of the second transistor N2, and an output end of the comparator is connected with an input end of the first inverter F1; an output terminal of the first inverter F1 is connected to a first terminal of the flip-flop 151 and an input terminal of the second inverter F2, respectively; the output terminal of the second inverter F2 is connected to the gate of the first transistor N1.
Specifically, the positive electrode of the comparator is the first input end of the comparator, and the negative electrode of the comparator is the second input end of the comparator. When the reference voltage signal Vref input by the first input end of the comparator is larger than the electric signal input by the second input end of the comparator, the output end of the comparator outputs a high-level signal. The level signal output from the output terminal of the second inverter F2 is of the same type as the level signal output from the output terminal of the comparator, but the level signal output from the output terminal of the second inverter F2 has a driving capability stronger than that of the level signal output from the output terminal of the comparator. The second input terminal of the comparator is connected to the second pole of the second transistor N2, and when the second power supply charges the charging terminal of the constant current source charging module 130, the potential of the second input terminal of the comparator rises.
Optionally, with continued reference to fig. 3, latch 152 includes a third inverter F3, a first nor gate H1, and a second nor gate H2; an input terminal of the third inverter F3 is connected to the second terminal of the flip-flop 151, and an output terminal of the third inverter F3 is connected to a first input terminal of the second nor gate H2; a first input terminal of the first nor gate H1 is connected to the second terminal of the flip-flop 151, a second input terminal of the first nor gate H1 is connected to the output terminal of the second nor gate H2, and an output terminal of the first nor gate H1 is connected to the second input terminal of the input control module 110; a second input of the second nor gate H2 is connected to the output of the first nor gate H1 and an output of the second nor gate H2 is connected to a third input of the input control module 110.
Specifically, the input terminal of the third inverter F3 is connected to the first input terminal of the first nor gate H1, and the output terminal of the third inverter F3 is connected to the first input terminal of the second nor gate H2, so as to ensure that the level signals output by the first output terminal and the second output terminal of the latch 152 are different.
Optionally, with continued reference to fig. 3, the input control module 110 includes a fourth inverter F4, a fifth inverter F5, a first nand gate Y1, a second nand gate Y2, a third nand gate Y3, a fourth nand gate Y4, a fifth nand gate Y5, and a sixth nand gate Y6; the input end of the fourth inverter F4 is the input end of the timing control circuit, and the output end of the fourth inverter F4 is connected with the input end of the fifth inverter F5; a first input end of a first nand gate Y1 is connected with an output end of a first nor gate H1, a second input end of a first nand gate Y1 is connected with an output end of a fourth inverter F4, a first input end of a second nand gate Y2 is connected with an output end of a second nor gate H2, a second input end of a second nand gate Y2 is connected with an output end of a fifth inverter F5, a first input end of a third nand gate Y3 is connected with an output end of a first nand gate Y1, a second input end of the third nand gate Y3 is connected with an output end of a second nand gate Y2, and an output end of the third nand gate Y3 is connected with a first control end of the switch module 120; a first input end of the fourth nand gate Y4 is connected to an output end of the first nor gate H1, a second input end of the fourth nand gate Y4 is connected to an output end of the fifth inverter F5, a first input end of the fifth nand gate Y5 is connected to an output end of the second nor gate H2, a second input end of the fifth nand gate Y5 is connected to an output end of the fourth inverter F4, a first input end of the sixth nand gate Y6 is connected to an output end of the fourth nand gate Y4, a second input end of the sixth nand gate Y6 is connected to an output end of the fifth nand gate Y5, and an output end of the sixth nand gate Y6 is connected to the second control end of the switch module 120.
Illustratively, when the level signal input to the first input terminal of the input control module 110 is a low level signal, the first switch M1 and the fourth switch M4 are closed, the second switch M2 and the third switch M3 are opened, and the charging terminal of the constant current source charging module 130 is charged to 0.3Vref, the level signal input to the first input terminal of the input control module 110 is changed from the low level signal to a high level signal, it is deduced that the first output terminal of the input control module 110 outputs a high level signal according to the connection relationship of the fourth inverter F4, the fifth inverter F5, the first nand gate Y1, the second nand gate Y2, the third nand gate Y3, the fourth nand gate Y4, the fifth nand gate Y5 and the sixth nand gate Y6, the first switch M1 and the fourth switch M4 are opened, the second switch M2 and the third switch M3 are closed, since the power of the storage capacitor C of the upper stage is 0.3Vref, after the second switch M2 is closed, the first end of the storage capacitor C is connected to the reference voltage signal Vref, because the electric quantity of the storage capacitor C cannot be suddenly changed, in order to ensure that the electric quantity of the storage capacitor C is still 0.3Vref, the second end of the storage capacitor C is forced to be 0.7Vref, the electric potential of the charging end of the constant current source charging module 130 is 0.7Vref at this time, the second power supply continues to charge the charging end until the voltage signals input by the first input end and the second input end of the comparator are equal, in this process, the second power supply charges the second input end of the comparator from 0.7Vref to Vref, the electric quantity of 0.3Vref is charged in total, and the electric quantity is equal to the electric quantity charged by the second power supply to 0.3Vref when the first input end of the control module 110 is a low level signal at the last time.
Calculating the last charging time according to a charging time calculation formula as follows:
calculating the charging time at this time according to a charging time calculation formula as follows:
as can be seen, T2 = T3. After the level signal at the input end of the timing control circuit changes, the timing control circuit provided by the embodiment of the invention can still record the last charging time.
Compared with the traditional digital timing circuit, the timing control circuit provided by the embodiment of the invention omits a digital high-frequency clock circuit, and can greatly reduce the noise coupling and interference of the high-frequency digital circuit to the high-performance analog circuit. Compared with the traditional analog implementation scheme, the timing control circuit provided by the embodiment of the invention has a simple structure, can realize a complex timing function by only using one comparator, has the characteristics of low power consumption and low cost because other circuit parts are digital gate circuits, and is very suitable for a low-power consumption analog closed-loop control circuit.
The embodiment of the invention also provides a timing control system which comprises the timing control circuit provided by any one of the embodiments.
The timing control system provided by the embodiment and the timing control circuit provided by any embodiment of the invention belong to the same inventive concept, have corresponding beneficial effects, and the technical details not detailed in the embodiment and the timing control circuit provided by any embodiment of the invention are detailed.
It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will appreciate that the embodiments of the present invention are not limited to the specific embodiments described herein, and that various obvious changes, adaptations, and substitutions are possible, without departing from the scope of the embodiments of the present invention. Therefore, although the embodiments of the present invention have been described in more detail through the above embodiments, the embodiments of the present invention are not limited to the above embodiments, and many other equivalent embodiments may be included without departing from the concept of the embodiments of the present invention, and the scope of the embodiments of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A timing control circuit is characterized by comprising an input control module, a switch module, a storage capacitor, a constant current source charging module, a comparison module and a triggering and latching module;
the input control module comprises a first input end, a second input end, a third input end, a first output end and a second output end, and the first input end of the input control module is used as the input end of the timing control circuit;
the switch module comprises a first control end, a second control end, a reference voltage input end, a grounding end and an input end; the first control end of the switch module is connected with the first output end of the input control module, the second control end of the switch module is connected with the second output end of the input control module, and the reference voltage input end of the switch module is connected with a reference voltage signal;
the storage capacitor is connected with the switch module and used for keeping the potentials at two ends of the switch module when the working state of the switch module is switched;
the constant current source charging module comprises a first power supply input end, a second power supply input end, a grounding end, a control end and a charging end; a first power supply input end of the constant current source charging module is connected with a first power supply, a second power supply input end of the constant current source charging module is connected with a second power supply, and a charging end of the constant current source charging module is connected with an input end of the switch module; the constant current source charging module is used for charging the charging end under the control of the control end of the constant current source charging module;
the comparison module comprises a first input end, a second input end, a first output end and a second output end, the first input end of the comparison module is connected with the reference voltage signal, the second input end of the comparison module is connected with the charging end of the constant current source charging module, the first output end of the comparison module is used as the output end of the timing control circuit, and the second output end of the comparison module is opposite to the first output end of the comparison module in potential;
the trigger and latch module comprises a trigger end, a first output end and a second output end, the trigger end of the trigger and latch module is connected with the second output end of the comparison module, the first output end of the trigger and latch module is connected with the second input end of the input control module, and the second output end of the trigger and latch module is connected with the third input end of the input control module.
2. The timing control circuit according to claim 1, wherein the constant current source charging module further comprises a first transistor and a second transistor;
the first power supply is connected with a first power supply input end of the constant current source charging module, and the second power supply is connected with a second power supply input end of the constant current source charging module;
the grid electrode of the first transistor is connected with the first output end of the comparison module, the first pole of the first transistor is connected with the first pole of the second transistor, and the second pole of the first transistor is the control end of the constant current source charging module and is connected with the first power supply;
the grid electrode of the second transistor is connected with the second pole of the first transistor, the second pole of the second transistor is the charging end of the constant current source charging module, and the first pole of the second transistor is grounded.
3. The timing control circuit of claim 1, wherein the switch module comprises a first switch, a second switch, a third switch, and a fourth switch;
a first end of the first switch is used as an input end of the switch module, a second end of the first switch is respectively connected with a first end of the storage capacitor and a first end of the second switch, and a control end of the first switch is connected with a second output end of the input control module;
a second end of the second switch is connected with a reference voltage signal, and a control end of the second switch is connected with a first output end of the input control module;
a first end of the third switch is connected with a first end of the first switch, a second end of the third switch is respectively connected with a second end of the storage capacitor and a first end of the fourth switch, and a control end of the third switch is connected with a first output end of the input control module;
and the second end of the fourth switch is grounded, and the control end of the fourth switch is connected with the second output end of the input control module.
4. The timing control circuit of claim 3, wherein the first switch, the second switch, the third switch, and the fourth switch are transistors.
5. The timing control circuit of claim 1, wherein the trigger and latch module comprises a flip-flop and a latch;
the first end of the trigger is the trigger end of the trigger and latch module, and the second end of the trigger is respectively connected with the first input end and the second input end of the latch.
6. The timing control circuit of claim 5, wherein the flip-flop is a D flip-flop, a first terminal of the flip-flop is connected to the second output terminal of the comparison module, a second terminal of the flip-flop is connected to the input terminal of the latch, and a third terminal of the flip-flop is connected to the fourth terminal of the flip-flop.
7. The timing control circuit of claim 5, wherein the latch comprises a third inverter, a first NOR gate, and a second NOR gate;
the input end of the third inverter is connected with the second end of the trigger, and the output end of the third inverter is connected with the first input end of the second NOR gate;
a first input end of the first nor gate is connected with a second end of the trigger, a second input end of the first nor gate is connected with an output end of the second nor gate, and an output end of the first nor gate is connected with a second input end of the input control module;
and the second input end of the second NOR gate is connected with the output end of the first NOR gate, and the output end of the second NOR gate is connected with the third input end of the input control module.
8. The timing control circuit of claim 7, wherein the input control module comprises a fourth inverter, a fifth inverter, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, and a sixth NAND gate;
the input end of the fourth inverter is the input end of the timing control circuit, and the output end of the fourth inverter is connected with the input end of the fifth inverter;
the first input end of the first nand gate is connected with the output end of the first nor gate, the second input end of the first nand gate is connected with the output end of the fourth inverter, the first input end of the second nand gate is connected with the output end of the second nor gate, the second input end of the second nand gate is connected with the output end of the fifth inverter, the first input end of the third nand gate is connected with the output end of the first nand gate, the second input end of the third nand gate is connected with the output end of the second nand gate, and the output end of the third nand gate is connected with the first control end of the switch module;
the first input end of the fourth nand gate is connected with the output end of the first nor gate, the second input end of the fourth nand gate is connected with the output end of the fifth inverter, the first input end of the fifth nand gate is connected with the output end of the second nor gate, the second input end of the fifth nand gate is connected with the output end of the fourth inverter, the first input end of the sixth nand gate is connected with the output end of the fourth nand gate, the second input end of the sixth nand gate is connected with the output end of the fifth nand gate, and the output end of the sixth nand gate is connected with the second control end of the switch module.
9. The timing control circuit of claim 1, wherein the comparison module comprises a comparator, a first inverter, and a second inverter;
a first input end of the comparator is connected with the reference voltage signal, a second input end of the comparator is connected with a charging end of the constant current source charging module, and an output end of the comparator is connected with an input end of the first inverter;
the output end of the first phase inverter is respectively connected with the trigger end of the trigger and latch module and the input end of the second phase inverter;
and the output end of the second phase inverter is the output end of the timing control circuit.
10. A timing control system comprising the timing control circuit of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110190710.5A CN112558673B (en) | 2021-02-20 | 2021-02-20 | Timing control circuit and timing control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110190710.5A CN112558673B (en) | 2021-02-20 | 2021-02-20 | Timing control circuit and timing control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112558673A true CN112558673A (en) | 2021-03-26 |
| CN112558673B CN112558673B (en) | 2021-05-04 |
Family
ID=75036018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110190710.5A Active CN112558673B (en) | 2021-02-20 | 2021-02-20 | Timing control circuit and timing control system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112558673B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5990669A (en) * | 1997-12-15 | 1999-11-23 | Dell Usa, L.P. | Voltage supply regulation using master/slave timer circuit modulation |
| JP2002091575A (en) * | 2000-09-14 | 2002-03-29 | Seiko Epson Corp | Constant voltage output device |
| CN2609280Y (en) * | 2003-02-17 | 2004-03-31 | 宁波百年电器有限公司 | Analog mechanical electronic timer |
| CN104821716A (en) * | 2014-01-30 | 2015-08-05 | 登丰微电子股份有限公司 | Constant turn-on time controller |
| CN106289333A (en) * | 2015-05-29 | 2017-01-04 | 苏州坤元微电子有限公司 | Capacitor charge and discharge control module and power frequency change-over circuit |
| CN110286706A (en) * | 2019-07-15 | 2019-09-27 | 杭州必易微电子有限公司 | Control circuit and control method |
-
2021
- 2021-02-20 CN CN202110190710.5A patent/CN112558673B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5990669A (en) * | 1997-12-15 | 1999-11-23 | Dell Usa, L.P. | Voltage supply regulation using master/slave timer circuit modulation |
| JP2002091575A (en) * | 2000-09-14 | 2002-03-29 | Seiko Epson Corp | Constant voltage output device |
| CN2609280Y (en) * | 2003-02-17 | 2004-03-31 | 宁波百年电器有限公司 | Analog mechanical electronic timer |
| CN104821716A (en) * | 2014-01-30 | 2015-08-05 | 登丰微电子股份有限公司 | Constant turn-on time controller |
| CN106289333A (en) * | 2015-05-29 | 2017-01-04 | 苏州坤元微电子有限公司 | Capacitor charge and discharge control module and power frequency change-over circuit |
| CN110286706A (en) * | 2019-07-15 | 2019-09-27 | 杭州必易微电子有限公司 | Control circuit and control method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112558673B (en) | 2021-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102130666B (en) | Duty ratio regulation circuit and method | |
| US20100176892A1 (en) | Ultra Low Power Oscillator | |
| CN110045774A (en) | A kind of digital LDO circuit of fast transient response | |
| JP6346967B2 (en) | Reference voltage circuit | |
| CN101097456B (en) | Voltage regulator | |
| US20080266917A1 (en) | Dc/dc converting system | |
| US20070252640A1 (en) | Voltage regulator outputting positive and negative voltages with the same offsets | |
| CN108768142A (en) | A kind of boostrap circuit | |
| CN108322199B (en) | Dynamic comparison method | |
| CN105119604A (en) | Bootstrap switch circuit suitable for sampling of an analog-to-digital converter in a low power and voltage condition | |
| CN102970008B (en) | Rapid transient response pulse duration modulation circuit | |
| CN108055024B (en) | Compact delay circuit | |
| CN208571909U (en) | A kind of boostrap circuit | |
| CN112558673B (en) | Timing control circuit and timing control system | |
| CN109617544A (en) | A kind of novel electrifying timing sequence control equipment, system and method | |
| CN110601528B (en) | Charge pump and storage device | |
| CN106160460A (en) | The charge pump circuit of quick charge | |
| CN107422773B (en) | Digital low-dropout regulator | |
| CN112532047B (en) | Switching power supply chip and system | |
| CN105511542A (en) | Voltage buffer applied to SAR (Successive Approximation Register) ADC (Analog to Digital Converter) | |
| CN112968427B (en) | Time delay compensation circuit and lithium battery protection system thereof | |
| CN202003253U (en) | Voltage multiplying circuit for CMOS (Complementary Metal Oxide Semiconductor) circuit | |
| CN103336546A (en) | Low-voltage difference voltage stabilizing circuit with current-limiting protection function under double high power supply voltage input | |
| TW202042476A (en) | Pwm/pfm dual mode charging system | |
| CN220795346U (en) | Bootstrap capacitor undervoltage protection detection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |