CN110286706A - Control circuit and control method - Google Patents
Control circuit and control method Download PDFInfo
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- CN110286706A CN110286706A CN201910635343.8A CN201910635343A CN110286706A CN 110286706 A CN110286706 A CN 110286706A CN 201910635343 A CN201910635343 A CN 201910635343A CN 110286706 A CN110286706 A CN 110286706A
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- 239000003990 capacitor Substances 0.000 claims description 57
- 238000005070 sampling Methods 0.000 claims description 29
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- 238000010168 coupling process Methods 0.000 claims description 15
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- 235000003140 Panax quinquefolius Nutrition 0.000 claims description 3
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
Present invention discloses a kind of control circuit and control methods, the control circuit includes control circuit of releasing, to obtain input voltage sampled signal, and the setting time before the lowest point position of input voltage sampled signal is arrived sends the signal opened of control leadage circuit to leadage circuit, sends the signal that control leadage circuit turns off to leadage circuit in the setting time before the lowest point position of input voltage sampled signal terminates or the setting time after position of the lowest point.Control circuit and control method proposed by the present invention can greatly reduce system loss brought by leakage current.Especially in underloading or zero load, the increased loss of system reduces particularly evident；The present invention can reduce no-load standby loss, while improve chip load capacity.The simple circuit that the present invention designs is reliable；Delay time may be set according to actual conditions in the present invention, and flexibility ratio is larger.
Description
Technical field
The invention belongs to electronic circuit technology fields, are related to a kind of control circuit more particularly to a kind of power control circuit
And control method.
Background technique
Fig. 1-1 is the circuit diagram of an existing power circuit, please refers to Fig. 1-1, and input AC voltage passes through two poles of rectification
Pipe D1, D2 obtain input voltage sampled signal Va, and ideally, Va is the steamed bun wave after sine wave arranges, the lowest point position electricity
Pressure is zero (as shown in the top half waveform of Fig. 2).And actually due to the presence of parasitic capacitance C1, cause Va voltage thorough
Bottom electric discharge, therefore the lowest point position is elevated (as shown in the lower half portion waveform of Fig. 2), to make Va voltage that can not really react defeated
Enter the voltage value of voltage Vac.
Fig. 1-2 is the circuit diagram of existing another power circuit, referring to FIG. 1-2, since the second capacitor C2 is smaller, and
Since circuit itself requires, it is desirable to which ideal steamed bun wave is presented in the second capacitor C2 voltage, but in underloading or zero load, the second electricity
The lowest point position for holding C2 waveform can not pull down near zero potential.
In order to make Va waveform close to ideal steamed bun wave, need to increase leadage circuit appropriate on Va, such as Fig. 1-1, figure
Shown in 1-2.Due to the presence of leakage current, system will increase certain loss, especially in underloading or zero load, the increased damage of system
Consumption becomes apparent, and no-load loss is difficult to meet efficiency requirement.In addition, the fever that leadage circuit will also result in chip rises, limitation
The maximum load capacity of chip.
In view of this, nowadays there is an urgent need to design a kind of leadage circuit control mode, to overcome existing leadage circuit control
Drawbacks described above existing for mode processed.
Summary of the invention
The present invention provides a kind of control circuit and control method, the time that the leadage circuit that can be greatly reduced is opened, loss
Sharp fall reduces circuit no-load loss, improves circuit load capacity.
In order to solve the above technical problems, according to an aspect of the present invention, adopting the following technical scheme that
A kind of control circuit, the control circuit include control circuit of releasing, and the control circuit of releasing includes the first ratio
Compared with device U1 and timer；
The first comparator U1 is for obtaining input voltage sampled signal, when the input voltage sampled signal is greater than the
When one reference voltage, the first level signal is exported；
The timer and the first comparator U1 are coupled, based on starting when receiving first level signal
When, and open signal is exported after preset time, the open signal carries out leakage current to control leadage circuit；The meter
When device be used for before the lowest point position of input voltage sampled signal terminates or the lowest point position terminate after to leadage circuit send control
The signal of leadage circuit shutdown.
As one embodiment of the present invention, the timer includes the second comparator U2, to control preset time
Length.
As one embodiment of the present invention, the timer includes first switch tube Q1, the first current source I1, first
Capacitor C1, the second comparator U2；
The inverting input terminal of the first comparator U1 couples input voltage sampled signal Va0, and first comparator U1 is just
Phase input terminal couples the first reference voltage Vth, the grid of the output end coupling first switch tube Q1 of first comparator U1；
The output of the first current source I1 be respectively coupled to the drain electrode of first switch tube Q1, first capacitor C1 first end,
The inverting input terminal of the normal phase input end of second comparator U2, the second comparator U2 couples the second reference voltage V-, and second compares
The output end of device U2 couples leadage circuit；The source electrode of first switch tube Q1, the second end of first capacitor C1 are grounded respectively.
As one embodiment of the present invention, first comparator U1 compares the ginseng of input voltage sampled signal Va0 and first
The size for examining voltage Vth, when input voltage sampled signal Va0 is greater than the first reference voltage Vth, first comparator U1 output is low
Level, first switch tube Q1 shutdown, the first current source I1 charge to first capacitor C1；
Second comparator compares the size of the voltage V+ and the second reference voltage V- of first capacitor C1, when first capacitor C1's
When voltage V+ is greater than the second reference voltage V-, leadage circuit is opened, the second electric current that input voltage sampled signal Va0 passes through setting
Source Ib discharges over the ground.
As one embodiment of the present invention, the control circuit further includes leadage circuit；The leadage circuit includes
Second current source Ib, second switch Q2；The output of the second current source Ib couples second switch Q2.
As one embodiment of the present invention, the control circuit further includes timer delay time acquisition unit, institute
The delay time that timer delay time acquisition unit determines timer according to the frequency of input voltage sampled signal is stated, and will be obtained
The data taken are sent to the control circuit of releasing；
The control circuit further includes AC frequency sampling circuit, and AC frequency sampling circuit is to obtain input voltage sampling letter
The frequency of number Va0；Timer delay time acquisition unit described in the AC frequency sampling circuit connection, when the timer delay
Between acquiring unit the timer delay time determined according to the frequency of the input voltage sampled signal Va0 received.
As one embodiment of the present invention, if input voltage sampled signal Va0 is that fixed input frequency or frequency become
Change range and be less than setting value, the counter delay time is set as at the first time by the timer delay time acquisition unit；
If the frequency variation of input voltage sampled signal Va0 is greater than the set value, the timer delay time acquisition unit
The frequency for determining input voltage sampled signal Va0 is sampled by crest voltage, and adjusts the second reference voltage V-'s according to frequency
Value, makes the timer delay time meet sets requirement.
As one embodiment of the present invention, the AC frequency sampling circuit include: third comparator U3, d type flip flop,
Third current sources la, first switch S1, second switch S2, the second capacitor C2, average voltage generation module；
The inverting input terminal of the third comparator U3 couples input voltage sampled signal Va0, and third comparator U3 is just
Phase input terminal couples third reference voltage Vb, the end first end dk of the output end coupling d type flip flop of third comparator U3；
The end second end Q of the d type flip flop couples first switch S1, and it is logical to send control first switch S1 to first switch S1
Disconnected control signal；The third end of the d type flip flopEnd and the 4th end end D are respectively coupled to second switch S2, to second switch
S2 sends the control signal of control second switch S2 on-off；
The first end of the output coupling first switch S1 of the third current sources la, the second end of first switch S1 distinguish coupling
Connect the first end of second switch S2, the first end of the second capacitor C2, the first end of average voltage generation module；Average voltage generates
The second end of module is the second reference voltage V-, and the voltage change of the first end of the second capacitor C2 is averaged to obtain the second reference
Voltage V-.
A kind of control method, the control method include:
Obtain input voltage sampled signal；
The input voltage sampled signal that will acquire is compared with the first reference voltage, when the input voltage sampled signal
When greater than the first reference voltage, the first level signal is exported；
Start timing when receiving first level signal, and exports open signal after preset time, it is described to open
Messenger carries out leakage current to control leadage circuit；Before the lowest point position of input voltage sampled signal terminates or the lowest point position
It sets and sends the signal that control leadage circuit turns off to leadage circuit after terminating.
As one embodiment of the present invention, the control method includes: to compare input voltage sampled signal Va0 and
The size of one reference voltage Vth, when input voltage sampled signal Va0 is greater than the first reference voltage Vth, first comparator U1 is defeated
Low level out, first switch tube Q1 shutdown charge to first capacitor C1 by the first current source I1；
The size for comparing the voltage V+ and the second reference voltage V- of first capacitor C1, when the voltage V+ of first capacitor C1 is greater than
When the second reference voltage V-, leadage circuit is opened, and input voltage sampled signal Va0 is put over the ground by the second current source Ib of setting
Electricity.
As one embodiment of the present invention, the control method includes: the frequency for obtaining input voltage sampled signal Va0
Rate, and the timer delay time is determined according to the frequency of input voltage sampled signal Va0.
As one embodiment of the present invention, if input voltage sampled signal Va0 is that fixed input frequency or frequency become
Change range and be less than setting value, the counter delay time is set as at the first time；
If the frequency variation of input voltage sampled signal Va0 is greater than the set value, is sampled by crest voltage and determine input electricity
The frequency of sampled signal Va0 is pressed, and adjusts the value of the second reference voltage V- according to frequency, the timer delay time is made to meet setting
It is required that.
As one embodiment of the present invention, the control method includes: that input voltage sampled signal Va0 and third are joined
It examines voltage Vb and compares and generate a square-wave signal, rising edge signal is sampled by d type flip flop, when the output high level of d type flip flop
Between be sampling the AC input period, d type flip flop the end Q export high period between, first switch S1 is open-minded, second switch S2
It closes, third current sources la charges to the second capacitor C2, the size i.e. table for the ceiling voltage VC2max of the second capacitor C2 reached
Levy the length in input voltage sampled signal Va0 input period；Keep signal that the average value of VC2max is transferred to the by sampling
Two reference voltage V-, the i.e. inverting input terminal of the second comparator U2；When the AC period is longer, VC2max is bigger, and corresponding second
The value of reference voltage V- is bigger, to keep timer delay time td longer, realizes the self adaptive control of delay time.
The beneficial effects of the present invention are: control circuit and control method proposed by the present invention can greatly reduce vent discharge
System loss brought by flowing.Especially in underloading or zero load, the increased loss of system reduces particularly evident；The present invention can reduce
No-load standby loss, while improving chip load capacity.The simple circuit that the present invention designs is reliable；The present invention can be according to reality
Situation sets delay time, and flexibility ratio is larger.
Detailed description of the invention
Fig. 1-1 is the circuit diagram of an existing power circuit.
Fig. 1-2 is the circuit diagram of existing another power circuit.
Fig. 2 is the waveform diagram of existing power circuit Va ideally and under actual conditions.
Fig. 3 is the circuit diagram of control circuit in one embodiment of the invention.
Fig. 4 is each relevant point waveform diagram in control circuit in one embodiment of the invention.
Fig. 5 is the circuit diagram of AC frequency sampling circuit in one embodiment of the invention.
Fig. 6 is each relevant point waveform diagram in AC frequency sampling circuit in one embodiment of the invention.
Specific embodiment
The preferred embodiment that the invention will now be described in detail with reference to the accompanying drawings.
For a further understanding of the present invention, the preferred embodiment of the invention is described below with reference to embodiment, still
It should be appreciated that these descriptions are only further explanation the features and advantages of the present invention, rather than to the claims in the present invention
Limitation.
Just for several typical embodiments, the present invention is not limited merely to the model of embodiment description for the description of the part
It encloses.Some technical characteristics in same or similar prior art means and embodiment, which are replaced mutually, also to be described in the present invention
In the range of protection.
" coupling " or connection in specification, also comprising being indirectly connected with, such as pass through some active devices both comprising being directly connected to
The connection that part, passive device or electrically-conducting medi carry out；May also include well known to a person skilled in the art can be achieved it is identical or
By the connection of other active devices or passive device on the basis of identity function purpose, such as by switching, following circuit electricity
The connection of road or component.
In addition, " the input voltage sampled signal " in specification can be AC voltage it is rectified after obtained voltage signal,
It is also possible to its voltage division signal.
Present invention discloses a kind of control circuit, the control circuit includes control circuit of releasing, to obtain input electricity
Sampled signal is pressed, and the setting time before the lowest point position of input voltage sampled signal is arrived sends control to leadage circuit and lets out
The signal for putting circuit debugging, in the setting time before the lowest point position of input voltage sampled signal terminates or after the position of the lowest point
Setting time to leadage circuit send control leadage circuit turn off signal.
In one embodiment of this invention, the control circuit of releasing includes first comparator U1 and timer；Described
One comparator U1 is for obtaining input voltage sampled signal, when the input voltage sampled signal is greater than the first reference voltage,
Export the first level signal；The timer and the first comparator U1 are coupled, and receive the first level letter for working as
Number when start timing, and open signal is exported after preset time, the open signal is released to control leadage circuit
Electric current；The timer is used for before the lowest point position of input voltage sampled signal terminates or the lowest point position terminate after to vent discharge
Road sends the signal of control leadage circuit shutdown.
In one embodiment of this invention, the timer includes the second comparator U2, to control the length of preset time
It is short.
Fig. 3 is the circuit diagram of control circuit in one embodiment of the invention；Referring to Fig. 3, in an implementation of the invention
In example, the control circuit of releasing includes first comparator U1, timer 10, the first input end coupling of the first comparator U1
Input voltage sampled signal is connect, the second input terminal of first comparator U1 couples the first reference voltage, and first comparator U1's is defeated
Outlet couples the timer 10.The first comparator U1 to compare input voltage sampled signal and the first reference voltage,
And comparison result is fed back into the timer 10；The timer 10 is exported according to the comparison result of the first comparator U1
Control the signal that the leadage circuit is switched on or off.
In one embodiment of this invention, the timer includes first switch tube Q1, the first current source I1, first capacitor
C1, the second comparator U2.The inverting input terminal of the first comparator U1 couples Va0 (in one embodiment of this invention, Va0
For the voltage division signal of input voltage sampled signal Va), the normal phase input end of first comparator U1 couples the first reference voltage Vth,
The grid of the output end coupling first switch tube Q1 of first comparator U1.The output of the first current source I1 is respectively coupled to first
The drain electrode of switching tube Q1, the first end of first capacitor C1, the second comparator U2 normal phase input end, the reverse phase of the second comparator U2
The output end that input terminal couples the second reference voltage V-, the second comparator U2 couples leadage circuit；The source electrode of first switch tube Q1,
The second end of first capacitor C1 is grounded respectively.
In one embodiment of this invention, first comparator U1 compares the big of voltage division signal Va0 and the first reference voltage Vth
Small, when Va0 is greater than the first reference voltage Vth, first comparator U1 exports low level, first switch tube Q1 shutdown, timer
It is charged by the first current source I1 to first capacitor C1；Second comparator compares the voltage V+ and second of first capacitor C1 with reference to electricity
The size for pressing V-, when the voltage V+ of first capacitor C1 is greater than the second reference voltage V-, leadage circuit is opened, input voltage sampling
Signal Va is discharged over the ground by the second current source Ib of setting.
Fig. 4 is each relevant point waveform diagram in control circuit in one embodiment of the invention；Each phase in the control circuit
The point digit wave form of pass is as shown in Figure 4.Select suitable first reference voltage Vth, first capacitor C1, the first current source I1 and
Two reference voltage V- values, can be such that leadage circuit is opened or closed according to scheduled time point.
Please continue to refer to Fig. 3, in one embodiment of this invention, the control circuit further includes leadage circuit 20；It is described
Leadage circuit 20 includes the second current source Ib, second switch Q2；The output of the second current source Ib couples second switch
Q2.In one embodiment of this invention, the grid of the output end coupling second switch Q2 of the second comparator U2, the second electricity
The input of stream source Ib couples input voltage sampled signal Va, and the output of the second current source Ib couples the drain electrode of second switch Q2,
The source electrode of second switch Q2 is grounded.
In one embodiment of this invention, the selection about the counter td time in Fig. 4, can be depending on specific requirement: (1)
If input voltage sampled signal Va is fixed input frequency or frequency range is less than setting value, when the timer delay
Between acquiring unit by the counter delay time be set as at the first time.Such as 50Hz AC input when, half wave cycles 10ms takes
Suitable system parameter makes in Fig. 4, and the counter td time is 8ms.The program is realized simple, reliable.(2) if input voltage samples
The frequency variation of signal Va is greater than the set value, and the frequency for determining input voltage sampled signal Va, and root are sampled by crest voltage
The value that the second reference voltage V- is adjusted according to frequency, makes the timer delay time meet sets requirement.
In one embodiment of this invention, the control circuit further includes timer delay time acquisition unit, the meter
When device delay time acquiring unit determine the delay time of timer according to the frequency of input voltage sampled signal, and will acquire
Data are sent to the control circuit of releasing.
Fig. 5 is the circuit diagram of AC frequency sampling circuit in one embodiment of the invention；Referring to Fig. 5, of the invention
In one embodiment, the control circuit further includes AC frequency sampling circuit, and AC frequency sampling circuit is adopted to obtain input voltage
The frequency of sample signal Va；Timer delay time acquisition unit described in the AC frequency sampling circuit connection, the timer prolong
Slow time acquisition unit determines the timer delay time according to the frequency of the input voltage sampled signal Va received；The AC frequency
Rate sample circuit includes: third comparator U3, d type flip flop, third current sources la, first switch S1, second switch S2, the second electricity
Hold C2, average voltage generation module 10.
The inverting input terminal of the third comparator U3 couples voltage division signal Va0, the normal phase input end of third comparator U3
Couple third reference voltage Vb, the end first end dk of the output end coupling d type flip flop of third comparator U3.The d type flip flop
The end second end Q couples first switch S1, and the control signal of control first switch S1 on-off is sent to first switch S1；The D touching
Send out the third end of deviceEnd and the 4th end end D are respectively coupled to second switch S2, send control second switch S2 to second switch S2
The control signal of on-off.The first end of the output coupling first switch S1 of the third current sources la, the second of first switch S1
End is respectively coupled to the first end of second switch S2, the first end of the second capacitor C2, the first end of average voltage generation module 10；The
The second end of two switch S2, the second end of the second capacitor C2 are grounded respectively.
In one embodiment of this invention, average voltage generation module 10 includes third switch S3, the 4th switch S4, third
Resistance R3, third capacitor C3, the 4th capacitor C4, the 4th diode D4.The cathode of the 4th diode D4 is respectively coupled to third
The first end of switch S3, the first end of third capacitor C3, the first end of the 4th switch S4；Second end, the third of third switch S3
The second end of capacitor C3 is grounded respectively；The second end of 4th switch S4 couples the first end of the 4th capacitor C4, the 4th capacitor C4's
Second end ground connection.
In one embodiment of this invention, the implementation method about sampling AC frequency: as shown in figure 5, (Va0 sampling is defeated by Va0
Enter the voltage signal of voltage VAC) square-wave signal is generated compared with third reference voltage Vb, it is sampled by the d type flip flop
The output high level time of rising edge signal, d type flip flop is the AC input period sampled, the high electricity of output at the end Q of d type flip flop
During flat, first switch S1 is open-minded, and second switch S2 is closed, and third current sources la charges to the second capacitor C2, the second capacitor C2
The ceiling voltage VC2max reached size characterize input voltage sampled signal Va input the period length；By relevant
Sampling keeps signal that the average value of VC2max is transferred to the second reference voltage V-, i.e. the reverse phase of the second comparator U2 is defeated in Fig. 3
Enter end.When the AC period is longer, VC2max is bigger, and the value of corresponding second reference voltage V- is bigger, to make timer delay
Time, td was longer, realized the self adaptive control of delay time；Waveform correlation is as shown in Figure 6.
The present invention also discloses a kind of control method, and the control method includes: to obtain input voltage sampled signal, is inputting
Setting time before the lowest point position of voltage sampling signal is arrived sends the signal that control leadage circuit is opened to leadage circuit；?
The lowest point position of input voltage sampled signal terminate before setting time or setting time after the position of the lowest point to vent discharge
Road sends the signal of control leadage circuit shutdown.
In one embodiment of this invention, the control method includes: to compare input voltage sampled signal and the first reference
Voltage, and comparison result is fed back into a timer；The timer is according to obtained comparison result output control leadage circuit
The signal being switched on or off.
In one embodiment of this invention, the control method includes: to obtain input voltage sampled signal；What be will acquire is defeated
Enter voltage sampling signal to be compared with the first reference voltage, when the input voltage sampled signal is greater than the first reference voltage
When, export the first level signal；Start timing when receiving first level signal, and exports after preset time open-minded
Signal, the open signal carry out leakage current to control leadage circuit；It is tied in the lowest point position of input voltage sampled signal
Before beam or the lowest point position sends the signal of control leadage circuit shutdown to leadage circuit after terminating.
In one embodiment of this invention, the control method includes: to compare the ginseng of input voltage sampled signal Va0 and first
The size for examining voltage Vth, when input voltage sampled signal Va0 is greater than the first reference voltage Vth, first comparator U1 output is low
Level, first switch tube Q1 shutdown charge to first capacitor C1 by the first current source I1；Compare the voltage V+ of first capacitor C1
With the size of the second reference voltage V-, when the voltage V+ of first capacitor C1 is greater than the second reference voltage V-, leadage circuit is opened,
AC signal Va is discharged over the ground by the second current source Ib of setting.
In one embodiment of this invention, the control method includes: input voltage sampled signal Va0 and third with reference to electricity
Pressure Vb, which compares, generates a square-wave signal, samples rising edge signal by d type flip flop, the output high level time of d type flip flop is
For the AC input period of sampling, between the end Q of d type flip flop exports high period, first switch S1 is open-minded, and second switch S2 is closed
It closes, third current sources la charges to the second capacitor C2, and the size for the ceiling voltage VC2max of the second capacitor C2 reached characterizes
The length in AC signal input period；Keep signal that the average value of VC2max is transferred to the second reference voltage V- by sampling, i.e.,
The inverting input terminal of second comparator U2；When the AC period is longer, VC2max is bigger, and the value of corresponding second reference voltage V- is got over
Greatly, to keep timer delay time td longer, the self adaptive control of delay time is realized.
In one embodiment of this invention, the control method includes: the frequency of acquisition input voltage sampled signal Va, and
The timer delay time is determined according to the frequency of input voltage sampled signal Va.(1) if input voltage sampled signal Va (is inputted
Voltage AC signal) it is that fixed input frequency or frequency range are less than setting value, the timer delay time acquisition unit
The counter delay time is set as at the first time.Such as 50Hz AC input when, half wave cycles 10ms takes suitable system
Parameter makes in Fig. 4, and the counter td time is 8ms.The program implements simple, reliable.(2) if input voltage sampled signal Va
Frequency variation be greater than the set value, the frequency for determining input voltage sampled signal Va is sampled by crest voltage, and according to frequency
The value for adjusting the second reference voltage V-, makes the timer delay time meet sets requirement.
In one embodiment of this invention, the control method is realized by a control circuit；The group of the control circuit
At the description that can be found in above each embodiment.
In one embodiment of this invention, the size for comparing voltage division signal Va0 and the first reference voltage Vth, when Va0 is greater than
When the first reference voltage Vth, first comparator U1 exports low level, and first switch tube Q1 shutdown passes through I1 pairs of the first current source
First capacitor C1 charging；The size for comparing the voltage V+ and the second reference voltage V- of first capacitor C1, when the electricity of first capacitor C1
When V+ being pressed to be greater than the second reference voltage V-, leadage circuit is opened, the second current source that input voltage sampled signal Va passes through setting
Ib discharges over the ground.
In one embodiment of this invention, the control method includes adjusting the timer delay time according to AC frequency sampling
The step of, specifically include: voltage division signal Va0 generates a square-wave signal compared with third reference voltage Vb, is triggered by the D
Device samples rising edge signal, and the output high level time of d type flip flop is the AC input period sampled, defeated at the end Q of d type flip flop
Out between high period, first switch S1 is open-minded, and second switch S2 is closed, and third current sources la charges to the second capacitor C2, and second
The size for the ceiling voltage VC2max of capacitor C2 reached characterizes the length in input voltage sampled signal Va input period；Pass through
Relevant sampling keeps signal that the average value of VC2max is transferred to the second reference voltage V-, i.e. the reverse phase of the second comparator U2 is defeated
Enter end；When the AC period is longer, VC2max is bigger, and the value of corresponding second reference voltage V- is bigger, to make timer delay
Time, td was longer, realized the self adaptive control of delay time.
In conclusion control circuit proposed by the present invention and control method, can greatly reduce system brought by leakage current
System loss.Especially in underloading or zero load, the increased loss of system reduces particularly evident；The present invention can reduce no-load standby damage
Consumption, while improving chip load capacity.The simple circuit that the present invention designs is reliable；The present invention, which may be set according to actual conditions, to prolong
Slow time, flexibility ratio are larger.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
Description and application of the invention herein are illustrative, is not wishing to limit the scope of the invention to above-described embodiment
In.The deformation and change of embodiments disclosed herein are possible, the realities for those skilled in the art
The replacement and equivalent various parts for applying example are well known.It should be appreciated by the person skilled in the art that not departing from the present invention
Spirit or essential characteristics in the case where, the present invention can in other forms, structure, arrangement, ratio, and with other components,
Material and component are realized.Without departing from the scope and spirit of the present invention, can to embodiments disclosed herein into
The other deformations of row and change.
Claims (13)
1. a kind of control circuit, which is characterized in that the control circuit includes control circuit of releasing, the control circuit packet of releasing
Include first comparator U1 and timer；
The first comparator U1 is for obtaining input voltage sampled signal, when the input voltage sampled signal is greater than the first ginseng
When examining voltage, the first level signal is exported；
The timer and the first comparator U1 are coupled, for starting timing when receiving first level signal,
And open signal is exported after preset time, the open signal carries out leakage current to control leadage circuit；The timing
Device be used for before the lowest point position of input voltage sampled signal terminates or the lowest point position terminate after to leadage circuit send control let out
The signal of electric discharge road shutdown.
2. control circuit according to claim 1, it is characterised in that:
The timer includes the second length of comparator U2, the second comparator U2 to control preset time.
3. control circuit according to claim 1, it is characterised in that:
The timer includes first switch tube Q1, the first current source I1, first capacitor C1, the second comparator U2；
The inverting input terminal of the first comparator U1 couples input voltage sampled signal Va0, and the positive of first comparator U1 is defeated
Enter the grid of the output end coupling first switch tube Q1 of end coupling the first reference voltage Vth, first comparator U1；
The output of the first current source I1 is respectively coupled to the drain electrode of first switch tube Q1, the first end of first capacitor C1, second
The inverting input terminal of the normal phase input end of comparator U2, the second comparator U2 couples the second reference voltage V-, the second comparator U2
Output end couple leadage circuit；The source electrode of first switch tube Q1, the second end of first capacitor C1 are grounded respectively.
4. control circuit according to claim 3, it is characterised in that:
First comparator U1 compares the size of input voltage sampled signal Va0 and the first reference voltage Vth, when input voltage samples
When signal Va0 is greater than the first reference voltage Vth, first comparator U1 exports low level, first switch tube Q1 shutdown, the first electric current
Source I1 charges to first capacitor C1；
Second comparator U2 compares the size of the voltage V+ and the second reference voltage V- of first capacitor C1, when the electricity of first capacitor C1
When V+ being pressed to be greater than the second reference voltage V-, leadage circuit is opened, the second current source that input voltage sampled signal Va0 passes through setting
Ib discharges over the ground.
5. control circuit according to any one of claims 1 to 4, it is characterised in that:
The control circuit further includes leadage circuit；The leadage circuit includes the second current source Ib, second switch Q2；It is described
The output of second current source Ib couples second switch Q2.
6. control circuit according to claim 1, it is characterised in that:
The control circuit further includes timer delay time acquisition unit, and the timer delay time acquisition unit is according to defeated
Enter the data that the frequency of voltage sampling signal determines the delay time of timer, and will acquire and be sent to described release to control electricity
Road；
The control circuit further includes AC frequency sampling circuit, and AC frequency sampling circuit is to obtain input voltage sampled signal
The frequency of Va0；Timer delay time acquisition unit described in the AC frequency sampling circuit connection, the timer delay time
Acquiring unit determines the timer delay time according to the frequency of the input voltage sampled signal Va0 received.
7. control circuit according to claim 6, it is characterised in that:
If input voltage sampled signal Va0 is that fixed input frequency or frequency range are less than setting value, the timer prolongs
The counter delay time is set as at the first time by slow time acquisition unit；
If the frequency variation of input voltage sampled signal Va0 is greater than the set value, the timer delay time acquisition unit passes through
Crest voltage samples the frequency for determining input voltage sampled signal Va0, and the value of the second reference voltage V- is adjusted according to frequency, makes
The timer delay time meets sets requirement.
8. control circuit according to claim 6, it is characterised in that:
The AC frequency sampling circuit includes: third comparator U3, d type flip flop, third current sources la, first switch S1, second
Switch S2, the second capacitor C2, average voltage generation module；
The inverting input terminal of the third comparator U3 couples input voltage sampled signal Va0, and the positive of third comparator U3 is defeated
Enter the end first end dk of the output end coupling d type flip flop of end coupling third reference voltage Vb, third comparator U3；
The end second end Q of the d type flip flop couples first switch S1, sends control first switch S1 on-off to first switch S1
Control signal；The third end of the d type flip flopEnd and the 4th end end D are respectively coupled to second switch S2, send to second switch S2
Control the control signal of second switch S2 on-off；
The first end of the output coupling first switch S1 of the third current sources la, the second end of first switch S1 are respectively coupled to the
The first end of two switch S2, the first end of the second capacitor C2, the first end of average voltage generation module；Average voltage generation module
Second end be the second reference voltage V-, the voltage change of the first end of the second capacitor C2 is averaged to obtain the second reference voltage
V-。
9. a kind of control method, which is characterized in that the control method includes:
Obtain input voltage sampled signal；
The input voltage sampled signal that will acquire is compared with the first reference voltage, when the input voltage sampled signal is greater than
When the first reference voltage, the first level signal is exported；
Start timing when receiving first level signal, and exports open signal after preset time, it is described to open letter
Number to control leadage circuit carry out leakage current；Before the lowest point position of input voltage sampled signal terminates or the lowest point position is tied
Shu Houxiang leadage circuit sends the signal of control leadage circuit shutdown.
10. control method according to claim 9, it is characterised in that:
The control method includes: to compare the size of input voltage sampled signal Va0 and the first reference voltage Vth, when input electricity
When sampled signal Va0 being pressed to be greater than the first reference voltage Vth, first comparator U1 exports low level, and first switch tube Q1 shutdown is led to
The first current source I1 is crossed to charge to first capacitor C1；
The size for comparing the voltage V+ and the second reference voltage V- of first capacitor C1, when the voltage V+ of first capacitor C1 is greater than second
When reference voltage V-, leadage circuit is opened, and input voltage sampled signal Va0 is discharged over the ground by the second current source Ib of setting.
11. control method according to claim 9, it is characterised in that:
The control method includes: the frequency of acquisition input voltage sampled signal Va0, and according to input voltage sampled signal Va0
Frequency determine the timer delay time.
12. control method according to claim 11, it is characterised in that:
If input voltage sampled signal Va0 is that fixed input frequency or frequency range are less than setting value, by counter delay
Time is set as at the first time；
If the frequency variation of input voltage sampled signal Va0 is greater than the set value, is sampled by crest voltage and determine that input voltage is adopted
The frequency of sample signal Va0, and according to the value of the second reference voltage V- of frequency adjustment, so that the timer delay time is met setting and wants
It asks.
13. control method according to claim 11 or 12, it is characterised in that:
The control method includes: that input voltage sampled signal Va0 generates a square-wave signal compared with third reference voltage Vb,
Rising edge signal is sampled by d type flip flop, the output high level time of d type flip flop is the AC input period sampled, is triggered in D
Between the end the Q output high period of device, first switch S1 is open-minded, and second switch S2 is closed, and third current sources la is to the second capacitor C2
Charging, the size for the ceiling voltage VC2max of the second capacitor C2 reached characterize the input voltage sampled signal Va0 input period
Length；Keep signal that the average value of VC2max is transferred to the second reference voltage V- by sampling, i.e. the second comparator U2's
Inverting input terminal；When the AC period is longer, VC2max is bigger, and the value of corresponding second reference voltage V- is bigger, to make timing
Device delay time td is longer, realizes the self adaptive control of delay time.
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