CN112542770B - Semiconductor device and preparation method thereof - Google Patents

Semiconductor device and preparation method thereof Download PDF

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CN112542770B
CN112542770B CN202011410736.8A CN202011410736A CN112542770B CN 112542770 B CN112542770 B CN 112542770B CN 202011410736 A CN202011410736 A CN 202011410736A CN 112542770 B CN112542770 B CN 112542770B
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gaalinp
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CN112542770A (en
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王俊
郭银涛
程洋
肖啸
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Suzhou Everbright Photonics Co Ltd
Suzhou Everbright Semiconductor Laser Innovation Research Institute Co Ltd
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Suzhou Everbright Photonics Co Ltd
Suzhou Everbright Semiconductor Laser Innovation Research Institute Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/34346—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser characterised by the materials of the barrier layers
    • H01S5/34373—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser characterised by the materials of the barrier layers based on InGa(Al)AsP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/3407—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers characterised by special barrier layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S2304/00—Special growth methods for semiconductor lasers
    • H01S2304/02—MBE
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S2304/00—Special growth methods for semiconductor lasers
    • H01S2304/04—MOCVD or MOVPE

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Abstract

The invention provides a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises: an undoped GaInP active layer; the semiconductor layer of P type GaAlInP, dope with Zn ion in the said P type GaAlInP semiconductor layer; a first diffusion cutoff layer between the P-type GaAlInP semiconductor layer and the undoped GaInP active layer, the first diffusion cutoff layer being made of (Ga)1‑ x1Alx1)1‑y1Iny1As1‑z1Pz1. The first diffusion cut-off layer can prevent Zn ions from diffusing from the P-type GaAlInP semiconductor layer to the non-doped GaInP active layer, the Al in the first diffusion cut-off layer can adjust the forbidden bandwidth of the diffusion cut-off layer, the energy level difference between the front layer and the rear layer of the first diffusion cut-off layer is reduced, and the performance of the semiconductor device can be improved.

Description

Semiconductor device and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
In1-xGaxThe P series compound semiconductor material can be used for manufacturing a series of photoelectric devices such as a Laser (LD), a Light Emitting Diode (LED), an Avalanche Photo Diode (APD), a solar cell and the like, wherein (Ga)1-xAlx)0.5In0.5The P series material can be used in red LED and 550nm-850nm laser as active region, waveguide layer, limiting layer, etc.
The P-type dopant being In1-xGaxOne technical difficulty of P series semiconductor materials for In1-xGaxThe P-type doping impurities of the P-series semiconductor material mainly comprise Zn, Mg and Cd, the Mg and Cd are used as doping impurities, and the doping level is low (less than or equal to 1X 10)18) A low-resistance P-type layer cannot be obtained, so that the oblique efficiency improvement of a high-power device is influenced; when Mg is used as doping impurities, a memory effect and a tailing effect exist, so that the doping is difficult to control; using Zn as doping impurity, up to 3X10 can be obtained18The doping level of (2) is high, but the diffusion coefficient is high, if the diffusion is carried out to a non-design region, the performance degradation can be caused, for example, in a laser, Zn diffuses the non-doped waveguide layer region, the absorption of a P-type layer to an optical field can be enhanced, and the output power is reduced; if diffused into the active region, non-radiative centers may form, resulting in a decrease in internal quantum efficiency.
For device performance, In1-xGaxP-series materials mainly use Zn as a doping impurity, but the problem of Zn diffusion has been hindering In1-xGaxThe performance of the P series material is improved.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the problem that the diffusion of the P-type GaAlInP semiconductor layer Zn is difficult to control in the prior art. Thus, a semiconductor device and a method of manufacturing are provided.
The present invention provides a semiconductor device including: an undoped GaInP active layer; the semiconductor layer of P type GaAlInP, dope with Zn ion in the said P type GaAlInP semiconductor layer; a first diffusion cutoff layer between the P-type GaAlInP semiconductor layer and the undoped GaInP active layer, the first diffusion cutoff layer being made of (Ga)1-x1Alx1)1- y1Iny1As1-z1Pz1。
Optionally, the (Ga) is1-x1Alx1)1-y1Iny1As1-z1Pz1Wherein x1 is 0.05-0.95, y1 is 0.3-0.7, and z is10.45 to 0.95.
Optionally, the thickness of the first diffusion cutoff layer is 0.5nm to 100 nm.
Optionally, the thickness of the first diffusion cutoff layer is 5nm to 25 nm.
Optionally, the P-type GaAlInP semiconductor layer includes a P-type GaAlInP confinement layer and a P-type GaAlInP waveguide layer, and the P-type GaAlInP waveguide layer is located between the undoped GaInP active layer and the P-type GaAlInP confinement layer.
Optionally, the method further includes: a second diffusion cutoff layer between the P-type GaAlInP waveguide layer and the P-type GaAlInP confinement layer, the second diffusion cutoff layer being made of (Ga)1-x2Alx2)1-y2Iny2As1-z2Pz2。
Optionally, the method further includes: the GaAs substrate layer is positioned on one side, back to the P-type GaAlInP semiconductor layer, of the non-doped GaInP active layer; an N-type GaAlInP confinement layer located between the GaAs substrate layer and the undoped GaInP active layer; an N-type GaAlInP waveguide layer between the N-type GaAlInP confinement layer and the undoped GaInP active layer; and the InGaP buffer layer is positioned between the N-type GaAlInP limiting layer and the GaAs substrate layer.
The invention also provides a preparation method of the semiconductor device, which comprises the following steps: forming an undoped GaInP active layer; forming a P-type GaAlInP semiconductor layer, wherein Zn ions are doped in the P-type GaAlInP semiconductor layer; forming a first diffusion cutoff layer between the step of forming the undoped GaInP active layer and the step of forming the P-type GaAlInP semiconductor layer, the first diffusion cutoff layer being made of (Ga) between the P-type GaAlInP semiconductor layer and the undoped GaInP active layer1-x1Alx1)1-y1Iny1As1-z1Pz1。
Optionally, after the undoped GaInP active layer is formed, a first diffusion cut-off layer is formed; after the first diffusion cutoff layer is formed, a P-type GaAlInP semiconductor layer is formed.
Optionally, the process of forming the first diffusion blocking layer includes: the first step is as follows: introducing a Ga source; the second step is as follows: synchronously introducing an As source, a P source, an Al source and an In source; the third step: closing the As source, the P source, the Al source and the In source; the fourth step: the Ga source was turned off.
Optionally, the process of forming the first diffusion blocking layer includes: the first step is as follows: introducing an Al source; the second step is as follows: synchronously introducing an As source, a P source, a Ga source and an In source; the third step: turning off the As source, the P source, the Ga source and the In source; the fourth step: the Al source was turned off.
Optionally, the process of forming the first diffusion blocking layer includes: the first step is as follows: introducing an Al source and a Ga source; the second step is as follows: synchronously introducing an As source, a P source and an In source; the third step: turning off the As source, the P source and the In source; the fourth step: the Al source and Ga source were turned off.
Optionally, the step of forming the P-type GaAlInP semiconductor layer includes: forming a P-type GaAlInP waveguide layer; forming a P-type GaAlInP confinement layer, the step of forming a P-type GaAlInP waveguide layer being performed between the step of forming the undoped GaInP active layer and the step of forming the P-type GaAlInP confinement layer; the preparation method of the semiconductor device further comprises the following steps: forming a second diffusion cutoff layer between the step of forming the P-type GaAlInP waveguide layer and the step of forming the P-type GaAlInP confinement layer, the second diffusion cutoff layer being made of (Ga)1-x2Alx2)1-y2Iny2As1-z2Pz2。
The invention has the following beneficial effects:
1. according to the semiconductor device provided by the technical scheme of the invention, the P-type GaAlInP semiconductor layer is doped with Zn ions, and a material (Ga) is arranged between the P-type GaAlInP semiconductor layer and the undoped GaInP active layer1-x1Alx1)1-y1Iny1As1- z1Pz1The first diffusion cut-off layer is used for adjusting the forbidden bandwidth of the first diffusion cut-off layer, and plays a role in transition of the forbidden bandwidth between the first diffusion cut-off layer and the P-type GaAlInP semiconductor layer as well as between the first diffusion cut-off layer and the undoped GaInP active layer, and the first diffusion cut-off layer can prevent Zn ions from diffusing from the P-type GaAlInP semiconductor layer to the undoped GaInP active layer, so that the performance of the semiconductor device can be improved.
2. Further, the semiconductor device includes a P-type GaAlInP confinement layer, a P-type GaAlInP waveguide layer, an N-type GaAlInP confinement layer, an N-type GaAlInP waveguide layer, and an InGaP buffer layer. The limiting layer is used for limiting the diffusion of carriers, so that the reduction of threshold current is facilitated; the N-type GaAlInP waveguide layer and the P-type GaAlInP waveguide layer are used for conducting the generated light and limiting the propagation of the light, so that the quality of the light beam emitted by the laser is improved; the InGaP buffer layer has the functions of reducing the surface stress of a substrate material, reducing defects generated by directly growing an epitaxial layer on the substrate and improving the surface quality of the epitaxial layer.
3. According to the preparation method of the semiconductor device, the first diffusion cut-off layer is formed after the undoped GaInP active layer is formed; forming a P-type GaAlInP semiconductor layer after forming the first diffusion cutoff layer; therefore, the first diffusion cut-off layer is positioned between the P-type GaAlInP semiconductor layer and the non-doped GaInP active layer, and can prevent Zn ions from diffusing from the P-type GaAlInP semiconductor layer to the non-doped GaInP active layer, so that the performance of the semiconductor device can be improved.
4. When the first diffusion cut-off layer is formed, the Ga source is firstly introduced, then the As source, the P source, the Al source and the In source are synchronously introduced, the As source, the P source, the Al source and the In source are firstly closed after the first diffusion cut-off layer grows, the Ga source is introduced for a period of time, the III group ion vacancy In the first diffusion cut-off layer can be reduced, the Zn ion diffusion path is blocked, and the Zn ion diffusion to the non-doped active region is prevented.
5. When the first diffusion cut-off layer is formed, the Al source is firstly introduced, then the As source, the P source, the Ga source and the In source are synchronously introduced, the As source, the P source, the Ga source and the In source are firstly closed, the Al source is introduced for a period of time, the III group ion vacancy In the first diffusion cut-off layer can be reduced, the Zn ion diffusion path is blocked, and the Zn ion diffusion to the non-doped active region is prevented.
6. When the first diffusion cut-off layer is formed, the Al source and the Ga source are firstly introduced, then the As source, the P source and the In source are synchronously introduced, the As source, the P source and the In source are firstly closed, and the Al source and the Ga source are introduced for a period of time, so that the III-group ion vacancy In the first diffusion cut-off layer can be reduced, the Zn ion diffusion path is blocked, and the diffusion of Zn ions to the non-doped active region is prevented.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 to 4 are schematic structural views illustrating a semiconductor device forming process according to an embodiment of the invention.
Description of reference numerals:
1. a GaAs substrate layer; 2. an InGaP buffer layer; 3. an N-type GaAlInP confinement layer; 4. an N-type GaAlInP waveguide layer; 5. an undoped GaInP active layer; 6. a first diffusion cutoff layer; 7. a P-type GaAlInP waveguide layer; 8. a second diffusion cutoff layer; 9. a P-type GaAlInP confinement layer.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
An embodiment of the present invention provides a semiconductor device, referring to fig. 4, including:
an undoped GaInP active layer 5;
the semiconductor layer of P type GaAlInP, dope with Zn ion in the said P type GaAlInP semiconductor layer;
a first diffusion cutoff layer 6 between the P-type GaAlInP semiconductor layer and the undoped GaInP active layer 5, the first diffusion cutoff layer 6 being made of (Ga)1-x1Alx1)1-y1Iny1As1-z1Pz1。
The Al in the first diffusion cutoff layer 6 is used to adjust the forbidden bandwidth of the semiconductor device, and plays a role in transition of the forbidden bandwidth between the first diffusion cutoff layer 6 and the P-type GaAlInP semiconductor layer and the undoped GaInP active layer 5. .
(Ga1-x1Alx1)1-y1Iny1As1-z1Pz1Wherein x1 is 0.05-0.95, y1 is 0.3-0.7, and z1 is 0.45-0.95. The x1 is mainly used for adjusting the forbidden bandwidth of the first diffusion cutoff layer, so that the forbidden bandwidth of the first diffusion cutoff layer is between the undoped GaInP active layer 5 and the P-type GaAlInP semiconductor layer to achieve the effect of balancing energy bands, and the x1 which is too large and too small cannot achieve the effect of balancing energy bands; the size of y1 is primarily used to adjust the lattice constant to ensure that the first diffusion stop layer does not introduce lattice defects due to too much attraction.
The thickness of the first diffusion cutoff layer 6 is 0.5nm to 100nm, preferably 5nm to 25nm, and may be, for example, 0.5nm, 5nm, 20nm, 25nm, 50nm, 80nm, 100nm, or the like. If the thickness of the first diffusion cutoff layer 6 is too small, the barrier effect against Zn diffusion decreases, and if the thickness of the first diffusion cutoff layer 6 is too large, the resistance of the semiconductor device increases.
The P-type GaAlInP semiconductor layer in this embodiment further includes a P-type GaAlInP waveguide layer 7, a second diffusion cutoff layer 8, and a P-type GaAlInP confinement layer 9 provided from the first diffusion cutoff layer 6 from bottom to top. The P-type GaAlInP waveguide layer 7 is doped with Zn ions, and the P-type GaAlInP confinement layer 9 is doped with Zn ions.
Wherein the material of the second diffusion cutoff layer 8 is (Ga)1-x2Alx2)1-y2Iny2As1-z2Pz2The second diffusion cut-off layer 8 can prevent the Zn element from diffusing from the P-type GaAlInP limiting layer 9 to the P-type GaAlInP waveguide layer 7, and reduce the performance degradation caused by the high absorption of light due to the doping of Zn in the P-type GaAlInP waveguide layer. Wherein x2 is 0.05-0.95, y2 is 0.3-0.7, and z2 is 0.45-0.95.
In one embodiment, x2 > x1, y1 is y2, and z1 is z2, so that the forbidden bandwidth of the second diffusion cutoff layer 8 is greater than that of the first diffusion cutoff layer 6, and stress variation in the second diffusion cutoff layer 8 and the first diffusion cutoff layer 6 can be avoided.
As a modified embodiment of this embodiment, the P-type GaAlInP semiconductor layer may not be provided with the second diffusion cutoff layer.
In this embodiment, an N-type GaAlInP waveguide layer 4 and an N-type GaAlInP confinement layer 3 are further sequentially disposed below the undoped GaInP active layer 5.
The use of the N-type GaAlInP confinement layer 3 and the P-type GaAlInP confinement layer 9 plays a role in limiting the diffusion of carriers, thereby being beneficial to the reduction of threshold current; the P-type GaAlInP waveguide layer 7 and the N-type GaAlInP waveguide layer 4 serve to conduct the generated light and to limit its propagation, thereby improving the quality of the light beam emitted by the laser.
In this embodiment, an InGaP buffer layer 2 is provided below the N-type GaAlInP confinement layer 3, and the semiconductor device is connected to the GaAs substrate layer 1 through the InGaP buffer layer 2.
The buffer layer has the functions of reducing the surface stress of the substrate material, reducing the defects generated by directly growing the epitaxial layer on the substrate and improving the surface quality of the epitaxial layer.
A process of forming a semiconductor device is described in detail with reference to fig. 1 to 4.
Referring to fig. 1, a GaAs substrate layer 1 is provided having opposing upper and lower surfaces.
With continued reference to fig. 1, an InGaP buffer layer 2 is formed on the upper surface of GaAs substrate layer 1 using a Metal-organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE) apparatus.
Continuing to refer to fig. 1, an epitaxial growth process is adopted to form an N-type GaAlInP confinement layer 3 on the side of the InGaP buffer layer 2 facing away from the GaAs substrate layer 1.
With continued reference to fig. 1, an epitaxial growth process is used to form an N-type GaAlInP waveguide layer 4 on a side of the N-type GaAlInP confinement layer 3 facing away from the InGaP buffer layer 2. The forbidden band width of the N-type GaAlInP waveguide layer 4 is smaller than that of the N-type GaAlInP limiting layer 3.
Referring to fig. 2, an undoped GaInP active layer 5 is formed on the side of the N-type gaiinp waveguide layer 4 facing away from the N-type gaiinp confinement layer 3 using an epitaxial growth process. The energy gap of the undoped GaInP active layer 5 is smaller than that of the N-type GaAlInP waveguide layer 4.
Referring to fig. 3, a first diffusion cutoff layer 6 is formed on a side of the undoped GaInP active layer 5 facing away from the N-type gaiinp waveguide layer 4 using an epitaxial growth process.
In the step of specifically forming the first diffusion cutoff layer 6, three possible embodiments are included:
the first embodiment: the process of forming the first diffusion cutoff layer 6 includes: the first step is as follows: introducing a Ga source; the second step is as follows: synchronously introducing an As source, a P source, an Al source and an In source; the third step: closing the As source, the P source, the Al source and the In source; the fourth step: the Ga source was turned off.
By the above embodiment, the group III ion vacancy in the first diffusion cutoff layer 6 can be reduced, the path of Zn ion diffusion is blocked, and the diffusion of Zn ions to the undoped active region 5 can be prevented.
The second embodiment: the process of forming the first diffusion cutoff layer 6 includes: the first step is as follows: introducing an Al source; the second step is as follows: synchronously introducing an As source, a P source, a Ga source and an In source; the third step: turning off the As source, the P source, the Ga source and the In source; the fourth step: the Al source was turned off.
By the above embodiment, the group III ion vacancy in the first diffusion cutoff layer 6 can be reduced, the path of Zn ion diffusion is blocked, and the diffusion of Zn ions to the undoped active region 5 can be prevented.
Third embodiment: the process of forming the first diffusion cutoff layer 6 includes: the first step is as follows: introducing an Al source and a Ga source; the second step is as follows: synchronously introducing an As source, a P source and an In source; the third step: turning off the As source, the P source and the In source; the fourth step: the Al source and Ga source were turned off.
By the above embodiment, the group III ion vacancy in the first diffusion cutoff layer 6 can be reduced, the path of Zn ion diffusion is blocked, and the diffusion of Zn ions to the undoped active region 5 can be prevented.
Wherein, the As source can be arsine (AsH3), tert-butyl dihydroarsenic (TBAs), the Al source can be trimethyl aluminum (TMAl), triethyl aluminum (TEAL), the Ga source can be trimethyl gallium (TMGa), triethyl gallium (TEGa), the In source can be trimethyl indium (TMIn), triethyl indium (TEIn), the P source can be phosphine (PH3), tert-butyl dihydrophosphorus (TBP), and the Zn source can be dimethyl zinc (DMZn), diethyl zinc (DEZn).
In this embodiment, the energy gap of the undoped GaInP active layer 5 is smaller than the energy gap of the first diffusion cutoff layer 6.
Referring to fig. 4, a P-type GaAlInP waveguide layer 7 is formed on the side of the first diffusion cut-off layer 6 facing away from the undoped GaInP active layer 5 using an epitaxial growth process. The P-type GaAlInP waveguide layer 7 has a larger band gap than the first diffusion cutoff layer 6.
With continued reference to fig. 4, a second diffusion stop layer 8 is formed by an epitaxial growth process on the side of the P-type GaAlInP waveguide layer 7 facing away from the first diffusion stop layer 6. The second diffusion cutoff layer 8 has a band gap larger than that of the P-type GaAlInP waveguide layer 7.
With continued reference to fig. 4, an epitaxial growth process is used to form a P-type GaAlInP confinement layer 9 on the side of the second diffusion stop layer 8 facing away from the P-type GaAlInP waveguide layer 7. The band gap of the P-type GaAlInP confinement layer 9 is larger than that of the second diffusion cutoff layer 8.
As a modified embodiment of this example, the P-type GaAlInP confinement layer 9 may be formed directly after the formation of the P-type GaAlInP waveguide layer 7, without growing the second diffusion cutoff layer 8.
In the method for manufacturing a semiconductor device provided in this embodiment, after forming an undoped GaInP active layer, a first diffusion cutoff layer is formed; forming a P-type GaAlInP semiconductor layer after forming the first diffusion cutoff layer; therefore, the first diffusion cut-off layer is positioned between the P-type GaAlInP semiconductor layer and the non-doped GaInP active layer, and can prevent Zn ions from diffusing from the P-type GaAlInP semiconductor layer to the non-doped GaInP active layer, thereby improving In1-xGaxPerformance of P-series semiconductors.
It should be noted that, in other structures, the first diffusion cutoff layer may be formed between the step of forming the undoped GaInP active layer and the step of forming the P-type gaiinp semiconductor layer, and the steps of forming the P-type gaiinp semiconductor layer and forming the undoped GaInP active layer may be interchanged.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims (21)

1. A method for manufacturing a semiconductor device, comprising the steps of:
forming an undoped GaInP active layer;
forming a P-type GaAlInP semiconductor layer, wherein Zn ions are doped in the P-type GaAlInP semiconductor layer;
forming a first diffusion cut-off layer between the step of forming the undoped GaInP active layer and the step of forming the P-type GaAlInP semiconductor layer, the first diffusion cut-off layer being located between the P-type GaAlInP semiconductor layer and the undoped GaInP active layerThe material of the first diffusion cutoff layer is (Ga)1-x1Alx1)1-y1Iny1As1-z1Pz1；
The process for forming the first diffusion cutoff layer comprises the following steps: the first step is as follows: introducing a Ga source; the second step is as follows: synchronously introducing an As source, a P source, an Al source and an In source; the third step: closing the As source, the P source, the Al source and the In source; the fourth step: the Ga source was turned off.
2. The method of manufacturing a semiconductor device according to claim 1, wherein after the undoped GaInP active layer is formed, a first diffusion cutoff layer is formed; after the first diffusion cutoff layer is formed, a P-type GaAlInP semiconductor layer is formed.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the P-type GaAlInP semiconductor layer includes: forming a P-type GaAlInP waveguide layer; forming a P-type GaAlInP confinement layer, the step of forming a P-type GaAlInP waveguide layer being performed between the step of forming the undoped GaInP active layer and the step of forming the P-type GaAlInP confinement layer;
the preparation method of the semiconductor device further comprises the following steps: forming a second diffusion cutoff layer between the step of forming the P-type GaAlInP waveguide layer and the step of forming the P-type GaAlInP confinement layer, the second diffusion cutoff layer being made of (Ga)1- x2Alx2)1-y2Iny2As1-z2Pz2。
4. The method for manufacturing a semiconductor device according to claim 1, wherein the (Ga)1-x1Alx1)1- y1Iny1As1-z1Pz1Wherein x1 is 0.05-0.95, y1 is 0.3-0.7, and z is10.45 to 0.95.
5. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the first diffusion cutoff layer is 0.5nm to 100 nm.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the thickness of the first diffusion cutoff layer is 5nm to 25 nm.
7. The method for manufacturing a semiconductor device according to claim 1, further comprising: forming a GaAs substrate layer, wherein the GaAs substrate layer is positioned on one side, back to the P-type GaAlInP semiconductor layer, of the non-doped GaInP active layer; forming an N-type GaAlInP confinement layer between the GaAs substrate layer and the undoped GaInP active layer; forming an N-type GaAlInP waveguide layer between the N-type GaAlInP confinement layer and the undoped GaInP active layer; forming an InGaP buffer layer between the N-type GaAlInP confinement layer and the GaAs substrate layer.
8. A method for manufacturing a semiconductor device, comprising the steps of:
forming an undoped GaInP active layer;
forming a P-type GaAlInP semiconductor layer, wherein Zn ions are doped in the P-type GaAlInP semiconductor layer;
forming a first diffusion cutoff layer between the step of forming the undoped GaInP active layer and the step of forming the P-type GaAlInP semiconductor layer, the first diffusion cutoff layer being made of (Ga) between the P-type GaAlInP semiconductor layer and the undoped GaInP active layer1-x1Alx1)1-y1Iny1As1-z1Pz1；
The process for forming the first diffusion cutoff layer comprises the following steps: the first step is as follows: introducing an Al source; the second step is as follows: synchronously introducing an As source, a P source, a Ga source and an In source; the third step: turning off the As source, the P source, the Ga source and the In source; the fourth step: the Al source was turned off.
9. The method of manufacturing a semiconductor device according to claim 8, wherein after the undoped GaInP active layer is formed, a first diffusion cutoff layer is formed; after the first diffusion cutoff layer is formed, a P-type GaAlInP semiconductor layer is formed.
10. The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming the P-type GaAlInP semiconductor layer includes: forming a P-type GaAlInP waveguide layer; forming a P-type GaAlInP confinement layer, the step of forming a P-type GaAlInP waveguide layer being performed between the step of forming the undoped GaInP active layer and the step of forming the P-type GaAlInP confinement layer;
the preparation method of the semiconductor device further comprises the following steps: forming a second diffusion cutoff layer between the step of forming the P-type GaAlInP waveguide layer and the step of forming the P-type GaAlInP confinement layer, the second diffusion cutoff layer being made of (Ga)1- x2Alx2)1-y2Iny2As1-z2Pz2。
11. The method for manufacturing a semiconductor device according to claim 8, wherein the (Ga)1-x1Alx1)1- y1Iny1As1-z1Pz1Wherein x1 is 0.05-0.95, y1 is 0.3-0.7, and z is10.45 to 0.95.
12. The method for manufacturing a semiconductor device according to claim 8, wherein a thickness of the first diffusion cutoff layer is 0.5nm to 100 nm.
13. The method for manufacturing a semiconductor device according to claim 12, wherein a thickness of the first diffusion cutoff layer is 5nm to 25 nm.
14. The method for manufacturing a semiconductor device according to claim 8, further comprising: forming a GaAs substrate layer, wherein the GaAs substrate layer is positioned on one side, back to the P-type GaAlInP semiconductor layer, of the non-doped GaInP active layer; forming an N-type GaAlInP confinement layer between the GaAs substrate layer and the undoped GaInP active layer; forming an N-type GaAlInP waveguide layer between the N-type GaAlInP confinement layer and the undoped GaInP active layer; forming an InGaP buffer layer between the N-type GaAlInP confinement layer and the GaAs substrate layer.
15. A method for manufacturing a semiconductor device, comprising the steps of:
forming an undoped GaInP active layer;
forming a P-type GaAlInP semiconductor layer, wherein Zn ions are doped in the P-type GaAlInP semiconductor layer;
forming a first diffusion cutoff layer between the step of forming the undoped GaInP active layer and the step of forming the P-type GaAlInP semiconductor layer, the first diffusion cutoff layer being made of (Ga) between the P-type GaAlInP semiconductor layer and the undoped GaInP active layer1-x1Alx1)1-y1Iny1As1-z1Pz1；
The process for forming the first diffusion cutoff layer comprises the following steps: the first step is as follows: introducing an Al source and a Ga source; the second step is as follows: synchronously introducing an As source, a P source and an In source; the third step: turning off the As source, the P source and the In source; the fourth step: the Al source and Ga source were turned off.
16. The method of manufacturing a semiconductor device according to claim 15, wherein after the undoped GaInP active layer is formed, a first diffusion cutoff layer is formed; after the first diffusion cutoff layer is formed, a P-type GaAlInP semiconductor layer is formed.
17. The method of manufacturing a semiconductor device according to claim 15, wherein the step of forming the P-type GaAlInP semiconductor layer includes: forming a P-type GaAlInP waveguide layer; forming a P-type GaAlInP confinement layer, the step of forming a P-type GaAlInP waveguide layer being performed between the step of forming the undoped GaInP active layer and the step of forming the P-type GaAlInP confinement layer;
the preparation method of the semiconductor device further comprises the following steps: in the step of forming P-type GaAlInP waveguide layer and forming P-type GaAlIForming a second diffusion stop layer between the steps of the nP limiting layer, wherein the material of the second diffusion stop layer is (Ga)1- x2Alx2)1-y2Iny2As1-z2Pz2。
18. The method for manufacturing a semiconductor device according to claim 15, wherein the (Ga)1-x1Alx1)1- y1Iny1As1-z1Pz1Wherein x1 is 0.05-0.95, y1 is 0.3-0.7, and z is10.45 to 0.95.
19. The method for manufacturing a semiconductor device according to claim 15, wherein a thickness of the first diffusion cutoff layer is 0.5nm to 100 nm.
20. The method for manufacturing a semiconductor device according to claim 19, wherein a thickness of the first diffusion cutoff layer is 5nm to 25 nm.
21. The method for manufacturing a semiconductor device according to claim 15, further comprising: forming a GaAs substrate layer, wherein the GaAs substrate layer is positioned on one side, back to the P-type GaAlInP semiconductor layer, of the non-doped GaInP active layer; forming an N-type GaAlInP confinement layer between the GaAs substrate layer and the undoped GaInP active layer; forming an N-type GaAlInP waveguide layer between the N-type GaAlInP confinement layer and the undoped GaInP active layer; forming an InGaP buffer layer between the N-type GaAlInP confinement layer and the GaAs substrate layer.
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