CN112542464B - Manufacturing method of three-dimensional memory - Google Patents
Manufacturing method of three-dimensional memory Download PDFInfo
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- CN112542464B CN112542464B CN202011426699.XA CN202011426699A CN112542464B CN 112542464 B CN112542464 B CN 112542464B CN 202011426699 A CN202011426699 A CN 202011426699A CN 112542464 B CN112542464 B CN 112542464B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The application provides a manufacturing method of a three-dimensional memory, which can comprise the following steps: providing a substrate with a first sub-stack structure; etching the first sub-stack structure to form at least one first channel hole penetrating through the first sub-stack structure; forming a carbon layer within the first channel hole by at least two carbon deposition processes and at least one carbon annealing process, wherein the carbon annealing process is interposed between the two carbon deposition processes; a second sub-stack is formed over the first sub-stack. According to the manufacturing method of the three-dimensional memory, the defects that in the prior art, the carbon layer is shrunk in the subsequent high-temperature process, so that a carbon gap is formed and a layer structure in the carbon gap is damaged in the subsequent process are overcome by the means of forming the carbon layer for the first time, annealing the carbon layer formed for the first time and forming the carbon layer for the second time.
Description
Technical Field
The present disclosure relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a three-dimensional memory.
Background
The memory is a sequential logic circuit. As a memory, a random access memory (Random Access Memory, abbreviated as RAM) is one of memories, and as a semiconductor manufacturing process progresses, a memory density thereof becomes higher and a size thereof becomes smaller. While the structure of the memory also evolves from two dimensions to three dimensions. The three-dimensional memory includes a plurality of memory cells formed of a plurality of sub-stack structures stacked in a vertical direction.
Currently, polysilicon or carbon is commonly used as a sacrificial layer to fill the channel holes. When the first channel hole of the first sub-stack structure is filled with the polysilicon as the sacrificial layer, the epitaxial layer (Silicon Epitaxial Growth, referred to as SEG for short) or the stacked structure positioned on the side wall of the channel hole is easily damaged in the process of removing the polysilicon, so that the performance of the memory device is affected. In addition, a long time wet etching is required to remove the polysilicon, resulting in a decrease in productivity and an increase in cost.
In order to reduce the manufacturing cost and improve the performance of the device, carbon is used for replacing polysilicon as the material of the channel sacrificial layer. However, when carbon is used as the sacrificial layer, the carbon is shrunk in the subsequent high temperature process, resulting in carbon gaps. Thus, during a subsequent etching process, the etchant contacts other layer structures, such as oxide, nitride or stack junctions of the first channel, along the carbon gap, thereby causing damage to the oxide, nitride or stack junctions.
There is a need to improve the semiconductor manufacturing process to reduce or eliminate carbon seams resulting from carbon shrinkage.
Disclosure of Invention
An embodiment of the present disclosure provides a method for manufacturing a three-dimensional memory, so as to at least partially overcome the defect of a carbon gap caused by shrinkage of a carbon layer in a stacked structure in a subsequent high-temperature process.
To achieve the object, a method for manufacturing a three-dimensional memory is provided, which may include: providing a substrate with a first sub-stack structure; etching the first sub-stack structure to form at least one first channel hole penetrating through the first sub-stack structure; forming a carbon layer within the first channel hole by at least two carbon deposition processes and at least one carbon annealing process, wherein the carbon annealing process is interposed between the two carbon deposition processes; a second sub-stack is formed over the first sub-stack.
Wherein the step of forming the carbon layer in the first channel hole may include: performing a first carbon deposition process to form a first carbon layer within the first trench hole covering an inner wall of the first trench hole; performing the carbon annealing process such that the first carbon layer is contracted; and performing a second carbon deposition process to form a second carbon layer on the contracted first carbon layer so as to fill carbon gaps formed after the first carbon layer is contracted.
Wherein the density of the first carbon layer may be different from the density of the second carbon layer.
Wherein the density of the first carbon layer may be higher than the density of the second carbon layer.
Wherein the carbon annealing process may be performed at a temperature of 450-850 ℃.
Wherein the carbon annealing process may be performed for 10 to 60 minutes.
Wherein the step of forming the carbon layer in the first channel hole may include: the carbon layer is formed to close an upper opening of the first channel hole.
The method for manufacturing the three-dimensional memory can further comprise the following steps: and etching the second sub-stack structure to form a second channel hole penetrating through the second sub-stack structure, wherein the second channel hole is aligned with the first channel hole.
The method for manufacturing the three-dimensional memory can further comprise the following steps: the carbon layer within the first channel hole is removed via the second channel hole.
Wherein, before the at least two carbon deposition processes and the at least one carbon annealing process are performed, the manufacturing method of the three-dimensional memory may further include: and forming an epitaxial structure at the bottom of the first channel hole.
Wherein the removing of the carbon layer in the first channel hole via the second channel hole may include: and removing the carbon layer in the first channel hole, so as to expose the epitaxial structure in the first channel hole.
The method for manufacturing the three-dimensional memory can further comprise the following steps: and forming a channel structure connected with the epitaxial structure in the first channel hole and the second channel hole.
The method for manufacturing the three-dimensional memory can further comprise the following steps: forming a subsequent sub-stack structure, sub-channel holes and a carbon layer on the first sub-stack structure until an Nth sub-stack structure, an Nth sub-channel hole and an N-1 th carbon layer are formed, so that the Nth sub-channel hole at the top exposes the carbon layer in the sub-channel of the lower layer, wherein N is more than 2; and removing each carbon layer based on the nth sub-channel hole.
According to the manufacturing method of the three-dimensional memory, the defects that in the prior art, the carbon layer is shrunk in the subsequent high-temperature process, so that a carbon gap is formed and a layer structure in the carbon gap is damaged in the subsequent process are overcome by the means of forming the carbon layer for the first time, annealing the carbon layer formed for the first time and forming the carbon layer for the second time. Therefore, the manufacturing method of the three-dimensional memory effectively improves the yield of the manufacture of the semiconductor, and particularly improves the yield of the manufacture of the three-dimensional memory.
In the prior art, as an alternative material for the carbon layer of the present application, polysilicon is used as an etch stop layer to protect the corresponding layer structure from the etchant in the subsequent etching process. However, when etching polysilicon, the process time is relatively long, resulting in a decrease in productivity. According to the manufacturing method of the three-dimensional memory, the carbon layer is used for replacing the polycrystalline silicon layer, so that the time of an etching process can be shortened, and the productivity is improved.
In addition, the cost of carbon materials is lower than that of polysilicon materials. And the cost of the etchant for the carbon material is lower than the cost of the etchant for the polysilicon material. According to the method for manufacturing the three-dimensional memory according to the embodiment of the application, compared with the prior art for depositing polysilicon, the manufacturing cost is improved.
Drawings
Embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
Fig. 1 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the disclosure.
Fig. 2A-2I are schematic cross-sectional views of different stages of a method for manufacturing a three-dimensional memory according to an embodiment of the present application.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed description are merely illustrative of exemplary embodiments of the application and are not intended to limit the scope of the application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.
In the drawings, the size, dimensions and shape of elements have been slightly adjusted for convenience of description. The figures are merely examples and are not drawn to scale. As used herein, the terms "about," "approximately," and the like are used as terms of a table approximation, not as terms of a table degree, and are intended to account for inherent deviations in measured or calculated values that will be recognized by one of ordinary skill in the art. In addition, in this application, the order in which the processes of the steps are described does not necessarily indicate the order in which the processes occur in actual practice, unless explicitly defined otherwise or the context may be inferred.
It will be further understood that terms such as "comprises," "comprising," "includes," "including," "having," "containing," "includes" and/or "including" are open-ended, rather than closed-ended, terms that specify the presence of the stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of the following" appears after a list of features listed, it modifies the entire list of features rather than just modifying the individual elements in the list. Furthermore, when describing embodiments of the present application, use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and technical terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, embodiments and features of embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
As shown in fig. 1, a method for manufacturing a three-dimensional memory according to an embodiment of the present application may include:
and 14, forming the second sub-stack structure on the first sub-stack structure.
In the method for manufacturing a three-dimensional memory according to an embodiment of the present application, the method may further include:
step 15 (not shown), etching the second sub-stack structure to form a second channel hole; and
step 16 (not shown) of forming a functional layer in the channel hole.
In the method for manufacturing the three-dimensional memory according to the embodiment of the application, the carbon layer is formed as the sacrificial layer in the first channel hole so as to form the second sub-stack structure on the first sub-stack structure. However, it will be appreciated by those skilled in the art that the carbon layer may also serve as a protective film within the first channel hole for protecting other layer structures within the first channel hole from damage during subsequent processes. The carbon layer may also be formed as a protective layer in other holes or trenches to protect other layer structures in the corresponding holes or trenches.
According to the manufacturing method of the three-dimensional memory, the defects that in the prior art, carbon gaps appear due to shrinkage of the carbon layer in a subsequent high-temperature process, and the layer structure is damaged due to introduction of corrosive gas into the carbon gaps in the subsequent process are overcome by means of forming the carbon layer for the first time, annealing the carbon layer formed for the first time and forming the carbon layer for the second time. Therefore, the manufacturing method of the three-dimensional memory of the embodiment of the application effectively improves the yield of the manufacturing method of the semiconductor device, and particularly improves the yield of the manufacturing method of the three-dimensional memory.
Fig. 2A-2I are schematic cross-sectional views of different stages of a method for manufacturing a three-dimensional memory according to an embodiment of the present application. Next, each step of the method for manufacturing a three-dimensional memory according to an embodiment of the present application will be described in detail with reference to fig. 2A to 2I.
As shown in fig. 2A, a first sub-stack structure is formed on a substrate. Specifically, the first sub-stack structure 110 is formed by alternately depositing the insulating layer 103 and the sacrificial layer 104 on the substrate 100. The number of layers of the sacrifice layer 103 and the insulating layer 104 is not limited to the number of layers shown in fig. 2A, and may be set as required, for example, to 32 layers, 64 layers, 128 layers, or the like.
The material of the substrate 100 may be a group iii-v compound such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon On Insulator (SOI), germanium On Insulator (GOI), or gallium arsenide. Wherein the substrate 100 includes a doped conductive layer (not shown) for electrical connection; the material of the insulating layer 104 may be one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride; the material of the sacrificial layer 103 may be one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, polysilicon. When selecting the materials of the insulating layer 104 and the sacrificial layer 103, it is necessary to select materials that react to different etchants so that the insulating layer 104 can be preserved when etching the sacrificial layer 103. Although the materials of the substrate 100 and the first sub-stack structure 110 are exemplified in the present embodiment, the materials of the substrate 100 and the first sub-stack structure 110 are not limited thereto. As an embodiment, the material of the substrate 100 may be silicon, and the first sub-stack structure 110 may be a structure in which a plurality of oxide layers and nitride layers are alternately stacked.
In the present application, the deposition process may be an atomic layer deposition (Atomic Layer Deposition, abbreviated as ALD), a physical vapor deposition (Physical Vapor Deposition, abbreviated as PVD), or a chemical vapor deposition (Chemical Vapor Deposition, abbreviated as CVD) process.
And step 12, etching the first sub-stack structure to form a first channel hole penetrating through the first sub-stack structure.
As shown in fig. 2B, in the method for manufacturing the three-dimensional memory according to an embodiment of the present application, the first sub-stack structure 110 is etched, and the first channel hole 105 penetrating the first sub-stack structure 110 is formed. In this embodiment, a photoresist is formed on the first sub-stack structure 110, and then the photoresist is exposed and developed through a mask plate having a predetermined pattern such that the photoresist exposes a predetermined region, i.e., a region to be etched. At this time, a predetermined region is etched by an anisotropic etching process. In this embodiment, the anisotropic etching process may be dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser etching, or the like. By controlling the etching time, the etching process is stopped near the surface of the substrate 100. After the etching process is completed, the photoresist is removed by a solvent, or is removed by an ashing process.
Further, an epitaxial structure 101 may be formed at the bottom of the first channel hole 105. The material of the epitaxial structure 101 may be polysilicon or monocrystalline silicon, but the material of the epitaxial structure is not limited thereto.
And step 13, forming a carbon layer in the first channel hole through at least two carbon deposition processes and at least one carbon annealing process, wherein the carbon annealing process is between the two carbon deposition processes.
As shown in fig. 2C, in the method for manufacturing the three-dimensional memory according to an embodiment of the present application, the carbon layer 106 is formed in the first channel hole through at least two carbon deposition processes and one carbon annealing process. The step of forming the carbon layer 106 may include at least: performing a first carbon deposition process; annealing carbon; a second carbon deposition process is performed.
The step of performing the first carbon deposition process may be: a carbon layer is formed by a deposition process to cover the inner wall of the first channel hole 105 and the top of the first sub-stack structure 110 to form a first carbon layer 106a. In this embodiment, the deposition process may be a chemical vapor deposition process.
The steps of performing the carbon annealing process may be: the carbon annealing process is performed on the first carbon layer 106a such that the first carbon layer 106a is shrunk. In this embodiment, the ambient temperature of the annealing process may be controlled between 450-850 ℃ and the process time may be controlled between 10-60 minutes. The carbon layer formed for the first time is sufficiently shrunk by the step of carbon annealing.
The step of performing the second carbon deposition process may be: after the first carbon layer formation and carbon annealing step, a second carbon layer (not shown) is formed through a deposition process to fill up the first channel hole 105.
In this embodiment, the deposition process may be a chemical vapor deposition process.
As shown in fig. 2D, after the above-described first carbon deposition process, carbon annealing process, and second carbon deposition process, a carbon layer is formed in the first sub-stack structure.
In the method of manufacturing the three-dimensional memory according to an embodiment of the present application, although the carbon deposition process is performed twice and the carbon annealing process is disposed between the carbon deposition processes, it will be understood by those skilled in the art that the carbon deposition process and the carbon annealing process may be added one or more times, respectively, on the basis of the present embodiment according to actual needs. The main purpose of providing a carbon annealing process after the carbon deposition process is, on the one hand, to allow the carbon layer to shrink sufficiently during the carbon annealing process so as not to shrink as much as possible during the subsequent high temperature process; on the other hand, since carbon gaps may be formed after the carbon layer is sufficiently shrunk, it is advantageous to fill the carbon gaps formed on the shrunk first carbon layer in a subsequent carbon deposition process.
In the method for manufacturing the three-dimensional memory according to the embodiment of the present application, the density of forming the first carbon layer is different from the density of forming the second carbon layer. According to an exemplary embodiment of the present application, the density of the first carbon layer is higher than the density of the second carbon layer formed. Continuing taking the example of forming the carbon layer by two carbon deposition processes and one carbon annealing process, a carbon layer having a relatively high density is formed in the first carbon layer forming step by controlling the deposition rate, the ambient temperature, and the like, and then the carbon annealing process is performed. In some embodiments, a relatively dense carbon layer is formed in a first carbon deposition process, and relatively few, small carbon gaps are formed after a carbon annealing process. Then, a carbon layer having a relatively lower density than the first carbon layer is formed in the second carbon deposition process to fill the carbon gaps. In the embodiment of forming the high-density carbon layer for the first time and forming the low-density carbon layer for the second time, because relatively fewer and smaller carbon gaps are formed after the carbon annealing process, fewer gaps need to be filled and the cost is lower than in the embodiment of forming the low-density carbon layer for the first time and forming the high-density carbon layer for the second time.
According to an exemplary embodiment of the present application, after the carbon layer is formed in the first channel hole, a Bevel Dry etching (Bevel Dry Etch) process may be performed to remove carbon on the wafer Bevel.
According to an exemplary embodiment of the present application, after forming the carbon layer within the first channel hole, a backside carbon removal (Back Side Carbon Remove) process may be performed to remove carbon on the wafer backside.
According to an exemplary embodiment of the present application, after forming the carbon layer in the first channel hole, an etching and/or Chemical mechanical planarization (Chemical-Mechanical Planarization, abbreviated as CMP) process may be performed for the carbon layer on top of the first sub-stack structure.
As shown in fig. 2E, in the present embodiment, the carbon layer on top of the first sub-stack structure 110 is removed by, for example, an etching process. The etching process may be a dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser etching, or the like. The etching may be stopped near the upper surface of the first sub-stack structure 110 by controlling the etching time.
Further, the upper surface of the first sub-stack structure 110 is polished by a chemical mechanical planarization process. At this time, the insulating layer 104 of the first sub-stack 110 may serve as a stop layer for chemical mechanical planarization, so that the carbon layer in the first channel hole 105 is aligned with the upper surface of the first sub-stack 110.
And 14, forming a second sub-stack structure on the first sub-stack structure.
As shown in fig. 2F, a second sub-stack 120 is formed on the first sub-stack 110 by a deposition process. The second sub-stack 120 includes a plurality of sacrificial layers 203 and insulating layers 204 alternately stacked, and the number of layers of the sacrificial layers 203 and the insulating layers 204 is not limited to the number of layers shown in fig. 2F, and may be set as desired, for example, to 32 layers, 64 layers, 128 layers, or the like.
As shown in fig. 2G, a second channel hole 205 penetrating the second sub-stack structure 120 is formed in the second sub-stack structure 120 through a photolithography process, the second channel hole 205 being aligned up and down with the previously formed first channel hole 105. In this embodiment, a photoresist is formed on the second sub-stack 120, and then the photoresist is exposed and developed through a mask plate having a predetermined pattern such that the photoresist exposes a predetermined region, i.e., a region to be etched. At this time, a predetermined region is etched by an anisotropic etching process. After the etching process is completed, the photoresist is removed by a solvent, or is removed by an ashing process.
As shown in fig. 2H, after the photoresist is removed, the carbon layer in the first channel hole 105 is removed, and the second channel hole 205 and the first channel hole 105 are penetrated.
As shown in fig. 2I, a functional layer 130 is formed on the through channel hole sidewalls. In an embodiment, the functional layer 130 includes several layer structures to achieve the corresponding functions, including a blocking layer 131, a charge storage layer 132, and a tunneling layer 133. The barrier layer 131 may be formed on the surfaces of the first and second channel holes 105 and 205. The blocking layer 131 can serve to block outflow of charges stored in the charge storage layer 132. In some embodiments, the material of the barrier layer 131 may be silicon oxide. In some embodiments, the barrier layer 131 may comprise a high dielectric constant dielectric (e.g., aluminum oxide). In one example, the barrier layer 131 may be a single layer or a multi-layer structure.
The charge storage layer 132 may be formed on the surface of the blocking layer 131. The charge storage layer 132 can be used to store charge. Writing and erasing of memory data can be achieved by storage or removal of charge in the charge storage layer 132. In some embodiments, charge storage layer 132 may be a nitride layer formed by using a deposition process.
The tunneling layer 133 can be formed on the charge storage layer 132. The charges stored in the charge storage layer 132 or the charges in the channel layer may pass through the tunneling layer 133 by a tunneling effect under a voltage to enable writing and erasing of memory data. In some embodiments, the tunneling layer 133 may be an oxide layer formed by using a deposition process.
Subsequently, as shown in fig. 2I, a channel layer 134 is formed on the surface of the tunneling layer 133. The channel layer 134 can be connected with the epitaxial structure 101 at the bottom of the first channel hole 105 to form a channel for the flow of power. Polysilicon may be deposited directly in the channel holes using a deposition process to form channel layer 134; an amorphous silicon layer may also be formed in the channel hole first, and then crystallized in a subsequent process step to form the polysilicon channel layer 134. The functional layer 130 and the polysilicon channel layer 134 together form a channel structure.
In the above, the three-dimensional memory of the present application is described by taking an example including two sub-stacked structures. However, those skilled in the art will appreciate that the three-dimensional memory of the present application may include N sub-stacks (N > 2). The method for forming the three-dimensional memory comprising N sub-stacked structures comprises the following steps:
forming a first sub-stack structure on a semiconductor substrate;
forming a first channel hole penetrating the first sub-stack structure in the first sub-stack structure;
filling a first carbon sacrificial layer in the first channel hole;
forming a second sub-stack structure on the first sub-stack structure formed with the first carbon sacrificial layer, and forming a second sub-channel hole penetrating the second sub-stack structure in the second sub-stack structure;
forming a second carbon sacrificial layer in the second sub-channel hole; and
and continuing to form a subsequent sub-stack structure, sub-channel holes and a carbon sacrificial layer on the semiconductor substrate until an N-th sub-stack structure, an N-th sub-channel hole and an N-1-th carbon sacrificial layer are formed, so that the sub-channel holes at the top expose the carbon sacrificial layer in the sub-channel holes at the lower layer.
Thereafter, each carbon sacrificial layer is removed based on the sub-channel holes at the top, resulting in a channel hole and a stacked structure. The methods of forming the sub-stack structure, the sub-channel holes, and the carbon layer described above in connection with the drawings may be applied to the manufacturing method of forming the three-dimensional memory including the N sub-stack structures, and will not be repeated here.
The purpose, technical scheme and beneficial effects of the invention are further described in detail in the detailed description. It is to be understood that the above description is only of specific embodiments of the present invention and is not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. A method of manufacturing a three-dimensional memory, comprising:
providing a substrate with a first sub-stack structure;
etching the first sub-stack structure to form at least one first channel hole penetrating through the first sub-stack structure;
forming a carbon layer within the first channel hole by at least two carbon deposition processes and at least one carbon annealing process, wherein the carbon annealing process is interposed between the two carbon deposition processes;
a second sub-stack is formed over the first sub-stack.
2. The method of manufacturing a three-dimensional memory according to claim 1, wherein the step of forming a carbon layer in the first channel hole comprises:
performing a first carbon deposition process to form a first carbon layer within the first trench hole covering an inner wall of the first trench hole;
performing the carbon annealing process such that the first carbon layer is contracted;
and performing a second carbon deposition process to form a second carbon layer on the contracted first carbon layer so as to fill carbon gaps formed after the first carbon layer is contracted.
3. The method of manufacturing a three-dimensional memory according to claim 2, wherein,
the density of the first carbon layer is different from the density of the second carbon layer.
4. The method for manufacturing a three-dimensional memory according to claim 3, wherein,
the density of the first carbon layer is higher than the density of the second carbon layer.
5. The method of manufacturing a three-dimensional memory according to claim 1, wherein,
the carbon annealing process is performed at a temperature of 450-850 ℃.
6. The method of manufacturing a three-dimensional memory according to claim 1, wherein,
the carbon annealing process is performed for 10-60 minutes.
7. The method of manufacturing a three-dimensional memory according to claim 1, wherein the step of forming the carbon layer in the first channel hole comprises:
the carbon layer is formed to close an upper opening of the first channel hole.
8. The method for manufacturing a three-dimensional memory according to any one of claims 2 to 7, further comprising:
and etching the second sub-stack structure to form a second channel hole penetrating through the second sub-stack structure, wherein the second channel hole is aligned with the first channel hole.
9. The method of manufacturing a three-dimensional memory according to claim 8, further comprising:
the carbon layer within the first channel hole is removed via the second channel hole.
10. The method of manufacturing a three-dimensional memory according to claim 9, further comprising, prior to performing the at least two carbon deposition processes and the at least one carbon annealing process:
and forming an epitaxial structure at the bottom of the first channel hole.
11. The method of manufacturing a three-dimensional memory according to claim 10, wherein the step of removing the carbon layer in the first channel hole via the second channel hole comprises:
and removing the carbon layer in the first channel hole, so as to expose the epitaxial structure in the first channel hole.
12. The method of manufacturing a three-dimensional memory according to claim 11, further comprising:
and forming a channel structure connected with the epitaxial structure in the first channel hole and the second channel hole.
13. The method for manufacturing a three-dimensional memory according to any one of claims 2 to 7, further comprising:
forming a subsequent sub-stack structure, sub-channel holes and a carbon layer on the first sub-stack structure until an Nth sub-stack structure, an Nth sub-channel hole and an N-1 th carbon layer are formed, so that the Nth sub-channel hole at the top exposes the carbon layer in the sub-channel of the lower layer, wherein N is more than 2; and
and removing each carbon layer based on the Nth sub-channel hole.
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