CN111162086A - Three-dimensional memory and preparation method thereof - Google Patents
Three-dimensional memory and preparation method thereof Download PDFInfo
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- CN111162086A CN111162086A CN202010006488.4A CN202010006488A CN111162086A CN 111162086 A CN111162086 A CN 111162086A CN 202010006488 A CN202010006488 A CN 202010006488A CN 111162086 A CN111162086 A CN 111162086A
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Abstract
The application provides a three-dimensional memory and a preparation method thereof. The preparation method comprises the following steps: providing a substrate, and forming a first stacked structure on the stacked surface of the substrate; etching the first stacked structure to form a first sub-channel hole penetrating through the first stacked structure; etching the first stacked structure at one side of the first sub-channel hole to form a first sub-gate gap penetrating through the first stacked structure; forming a second stacked structure on the surface of the first stacked structure, which is far away from the substrate; etching the second stacking structure at the position of the second stacking structure, which is aligned with the first sub-channel hole, so as to form a second sub-channel hole which penetrates through the second stacking structure; and etching the second stacked structure at the position of the second stacked structure, which is aligned with the first sub-gate gap, so as to form a second sub-gate gap penetrating through the second stacked structure. The preparation method solves the problems that in the prior art, the stacking height of the gate gaps in the etching process is high, the inclination risk is serious, and leakage current is easy to generate, so that the electrical performance and the yield of the three-dimensional memory are influenced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a preparation method thereof.
Background
Currently, in the process of manufacturing a three-dimensional memory, a substrate is provided and a stacked structure is formed on the substrate, then a Channel Hole (CH) is formed in the stacked structure, and a Gate Line Slot (GLS) is formed after the Channel hole is formed, so as to form a word line opening by removing a sacrificial layer in the stacked structure through the Gate slot, in preparation for a subsequent process of filling a Gate metal in the word line opening and the like. However, in the process of forming the gate slit by the etching process, the etching is difficult to proceed in a predetermined direction perpendicular to the semiconductor substrate, and is inclined, and the inclination degree of the gate slit is gradually increased as the stack height is increased. The gate gap stacking height in the existing etching process is high, the inclination risk is serious, the subsequent process of filling gate metal in the word line opening is easy to generate leakage current, the electrical performance of the three-dimensional memory is influenced, and the yield of the three-dimensional memory is reduced.
Disclosure of Invention
In view of this, the application provides a three-dimensional memory and a manufacturing method thereof, so as to solve the problems in the prior art that a gate gap stacking height in an etching process is high, an inclination risk is serious, a subsequent process of filling gate metal in a word line opening is prone to generating leakage current, electrical performance of the three-dimensional memory is affected, and yield of the three-dimensional memory is reduced.
In a first aspect, the present application provides a method for manufacturing a three-dimensional memory, the method comprising:
providing a substrate, wherein the substrate has a stacking face;
forming a first stacked structure on the stacked surface of the substrate;
etching the first stacked structure to form a first sub-channel hole penetrating through the first stacked structure;
etching the first stacked structure at one side of the first sub-channel hole to form a first sub-gate gap penetrating through the first stacked structure;
forming a second stacked structure on the side of the first stacked structure, which faces away from the substrate;
etching the second stacked structure at a position of the second stacked structure aligned with the first sub-channel hole to form a second sub-channel hole penetrating through the second stacked structure, wherein the bottom of the second sub-channel hole is communicated with the top of the first sub-channel hole;
and etching the second stacked structure at the position of the second stacked structure, which is aligned with the first sub-gate gap, so as to form a second sub-gate gap penetrating through the second stacked structure, wherein the bottom of the second sub-gate gap is communicated with the top of the first sub-gate gap.
In one embodiment, after the etching the first stacked structure to form the first sub-channel hole penetrating the first stacked structure, and before the etching the first stacked structure on the side of the first sub-channel hole to form the first sub-gate slit penetrating the first stacked structure, the method for manufacturing the three-dimensional memory includes:
and forming an epitaxial layer at the bottom of the first sub-channel hole.
In one embodiment, after the "etching the first stacked structure at a side of the first sub-channel hole to form the first sub-gate slit penetrating through the first stacked structure", and before the "forming the second stacked structure at a side of the first stacked structure facing away from the substrate", the method for manufacturing the three-dimensional memory includes:
and forming an oxide layer on the surface of the epitaxial layer departing from the substrate and at the bottom of the first sub-gate gap.
In one embodiment, after the "forming an oxide layer on the surface of the epitaxial layer facing away from the substrate and at the bottom of the first sub-gate slit" and before the "forming a second stacked structure on the side of the first stacked structure facing away from the substrate", the method for manufacturing the three-dimensional memory includes:
and simultaneously carrying out a first sacrificial layer deposition process on the first sub-channel hole and the first sub-gate gap so as to form a first sacrificial layer in the first sub-channel hole and the first sub-gate gap.
In one embodiment, after the "performing a first sacrificial layer deposition process on the first sub-channel hole and the first sub-gate slit simultaneously to form a first sacrificial layer in the first sub-channel hole and the first sub-gate slit" and before the "forming a second stacked structure on a side of the first stacked structure facing away from the substrate", the method for manufacturing a three-dimensional memory includes:
etching the first sacrificial layer to the bottom of the top layer of the first stacked structure;
removing the top layer of the first stacked structure to expose the second top layer of the first stacked structure;
simultaneously performing a second sacrificial layer deposition process on the first sub-channel hole and the first sub-gate gap to form a second sacrificial layer on the first sacrificial layer, wherein the second sacrificial layer covers the first sacrificial layer and the second-to-top layer;
and carrying out planarization treatment on the second sacrificial layer to expose the surface of the secondary top layer.
In one embodiment, after the removing the top layer of the first stacked structure to expose the second top layer of the first stacked structure and before the performing the second sacrificial layer deposition process on the first sub-channel hole and the first sub-gate slit simultaneously to form the second sacrificial layer on the first sacrificial layer, the method for manufacturing the three-dimensional memory includes:
and etching the top side wall of the first sub-channel hole and the top side wall of the first sub-gate gap so as to respectively enlarge the top aperture of the first sub-channel hole and the top aperture of the first sub-gate gap.
In an embodiment, the forming the second stacked structure on a side of the first stacked structure facing away from the substrate includes:
and forming a second stacked structure on the surface of the second-level layer of the first stacked structure and the surface of the second sacrificial layer, wherein a plane formed by the surface of the second-level layer and the surface of the second sacrificial layer is a surface of the first stacked structure, which is far away from the substrate.
In an embodiment, after "etching the second stacked structure at a position of the second stacked structure aligned with the first sub-channel hole to form a second sub-channel hole penetrating through the second stacked structure", and before "etching the second stacked structure at a position of the second stacked structure aligned with the first sub-gate gap to form a second sub-gate gap penetrating through the second stacked structure", the method for manufacturing a three-dimensional memory includes:
and removing the first sacrificial layer and the second sacrificial layer in the first sub-channel hole to enable the first sub-channel hole and the second sub-channel hole to penetrate through to form a channel hole.
In an embodiment, after the "etching the second stacked structure at a position of the second stacked structure aligned with the first sub-gate gap to form a second sub-gate gap penetrating through the second stacked structure", the method for manufacturing a three-dimensional memory includes:
and removing the first sacrificial layer and the second sacrificial layer in the first sub-gate gap to enable the first sub-gate gap and the second sub-gate gap to penetrate through to form a gate gap.
In a second aspect, the present application also provides a three-dimensional memory, which is prepared by the preparation method of the three-dimensional memory.
According to the preparation method of the three-dimensional memory, the two stacking structures of the first stacking structure and the second stacking structure are formed by stacking on the substrate twice, the first etching is carried out on the first stacking structure to form the first sub-gate gap, the second etching is carried out on the second stacking structure to form the second sub-gate gap communicated with the first sub-gate gap, and therefore the through gate gap is formed by etching twice. Compared with a gate gap formed by traditional single etching with high stacking height, the stacking height of the first stacking structure and the second stacking structure is low, so that the etching height required for etching the first sub-gate gap and the second sub-gate gap can be respectively reduced, on one hand, the profile distortion of the first sub-gate gap and the second sub-gate gap can be improved due to the fact that the depth-to-width ratio of each etching is low, the profile distortion of the gate gap formed after the first sub-gate gap and the second sub-gate gap are communicated is improved, on the other hand, the inclination risk of the gate gap can be greatly reduced, the problem of leakage current caused by a subsequent process of filling gate metal in a word line opening is solved, and the electrical performance of the three-dimensional memory and the yield of the three-dimensional memory are improved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a substrate of a three-dimensional memory according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a first stacked structure of a three-dimensional memory according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a first gate slit of a three-dimensional memory according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a first sacrificial layer of a three-dimensional memory according to an embodiment of the present disclosure;
fig. 6 is a schematic cross-sectional view of a portion of a first stacked structure of a three-dimensional memory according to an embodiment of the present disclosure;
FIG. 7 is a schematic process flow diagram of the first stacked structure shown in FIG. 6;
FIG. 8 is a schematic view of another process flow of the first stacked structure shown in FIG. 6;
FIG. 9 is a schematic view of another process flow of the first stacked structure shown in FIG. 6;
FIG. 10 is a schematic view of another process flow of the first stacked structure shown in FIG. 6;
fig. 11 is a schematic structural diagram of a first stacked structure of a three-dimensional memory according to an embodiment of the present disclosure;
fig. 12 is a schematic structural diagram of a second stacked structure of a three-dimensional memory according to an embodiment of the present application;
FIG. 13 is a schematic diagram of a channel hole of a three-dimensional memory according to an embodiment of the present disclosure;
fig. 14 is a schematic structural diagram of a channel hole of a three-dimensional memory according to an embodiment of the present disclosure, in which a blocking layer, a memory layer, a tunneling layer, and a channel layer are sequentially formed on an inner wall of the channel hole;
fig. 15 is a schematic structural diagram of a gate slit of a three-dimensional memory according to an embodiment of the present application.
Detailed Description
Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it is to be understood that the invention may be practiced otherwise than as specifically described and that the invention is therefore not limited to the following embodiments.
Three-dimensional (3D) memories are mainly used as nonvolatile flash memories. Two major non-volatile flash memory technologies employ NAND and NOR architectures, respectively. Compared with the NOR memory, the NAND memory has a fast writing speed, a simple erasing operation, and a smaller memory cell can be realized, thereby achieving a higher storage density. Therefore, the 3D memory adopting the NAND structure is widely used.
As the number of layers and the stack height in the three-dimensional NAND memory increase, an Aspect Ratio (AR) etching process is required in order to increase the memory density. Currently, in the fabrication process of a three-dimensional NAND memory, a substrate is provided and a stacked structure is formed on the substrate, then a Channel Hole (CH) is formed in the stacked structure, and a Gate Line Slot (GLS) is formed after the Channel hole is formed, so as to form a Word-line (WL) opening by removing a sacrificial layer in the stacked structure through the Gate slot, in preparation for the subsequent filling of a Gate metal in the Word-line opening and other processes. However, in the process of forming the gate slit by the etching process, the high aspect ratio etching process may cause difficulty in etching in a predetermined direction vertical to the semiconductor substrate, but may be inclined, particularly, at a connection region between the Core region (Core) and the mesa structure (SS).
In a three-dimensional memory to which a NAND structure is applied, a gate slit of a stacked structure is generally formed by a single etching. However, to increase storage density and capacity, the number of layers (tier) of three-dimensional memories continues to increase, for example from 64 layers to 96, 128 or more layers.
In a 64-layer stacked structure with a stack height of 4.6um, no inclination of the gate gap can be observed; in a 96-layer stacked structure with a stack height of 6.1um, slight gate gap inclination and irregular gaps, namely mouse-bite, can be observed; in a 128-layer stack structure with a stack height of 8.5um, a severe tilt of the gate gap can be observed, which is liable to cause a deterioration in the electrical performance of the three-dimensional memory. That is, the inclination degree of the gate slit is gradually increased as the stack height is increased.
Under the trend, the single etching method has higher processing cost and lower processing efficiency, and the inclination of the gate gap is more serious. The subsequent process of filling the gate metal in the word line opening is prone to generate leakage current, the electrical performance of the three-dimensional memory is affected, and the yield of the three-dimensional memory is reduced.
In view of the above, the present application provides a method for manufacturing a three-dimensional memory, please refer to fig. 1, and fig. 1 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present application. As shown in fig. 1, the method for manufacturing the three-dimensional memory at least includes S100, S200, S300, S400, S500, S600 and S700, which are described in detail below.
S100: providing a substrate, wherein the substrate has a stacking surface;
s200: forming a first stacked structure on a stacked surface of a substrate;
s300: etching the first stacked structure to form a first sub-channel hole penetrating through the first stacked structure;
s400: etching the first stacked structure at one side of the first sub-channel hole to form a first sub-gate gap penetrating through the first stacked structure;
s500: forming a second stacked structure on the surface of the first stacked structure, which is far away from the substrate;
s600: etching the second stacking structure at a position of the second stacking structure, which is aligned with the first sub-channel hole, so as to form a second sub-channel hole penetrating through the second stacking structure, wherein the bottom of the second sub-channel hole is communicated with the top of the first sub-channel hole;
s700: and etching the second stacked structure at the position of the second stacked structure, which is aligned with the first sub-gate gap, so as to form a second sub-gate gap penetrating through the second stacked structure, wherein the bottom of the second sub-gate gap is communicated with the top of the first sub-gate gap.
Each step will be further described below.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a substrate of a three-dimensional memory according to an embodiment of the present disclosure.
S100: a substrate 10 is provided, wherein the substrate 10 has a stacking face 101.
In the embodiment of the present application, the substrate 10 is a semiconductor substrate. For example, the substrate 10 may be a single crystal Silicon (Si) substrate, a single crystal Germanium (Ge) substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, or the like. The substrate 10 may also be a P-type doped substrate or an N-type doped substrate. Suitable materials can be selected as the substrate 10 according to actual requirements, and the present application is not limited to this. Of course, in other embodiments, the material of the substrate 10 may also be a semiconductor or a compound including other elements. For example, the substrate 10 may be a gallium arsenide (GaAs) substrate, an Indium phosphide (InP) substrate, a silicon carbide (SiC) substrate, or the like. Further, the substrate 10 has a stacking face 101, and the stacking face 101 is used to form a stacked structure.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a first stacked structure of a three-dimensional memory according to an embodiment of the present disclosure.
S200: a first stacked structure 20 is formed on the stacking surface 101 of the substrate 10.
In the embodiment of the present application, the first stack structure 20 is formed on the stack surface 101. The first stacked structure 20 includes first material layers 21 and second material layers 22 alternately stacked, and the first stacked structure 20 having a multi-layer structure is formed by successive alternate deposition of the first material layers 21 and the second material layers 22. The first material layer 21 and the second material layer 22 may be deposited by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma-enhanced CVD (PECVD), Sputtering (Sputtering), Metal-organic Chemical vapor deposition (MOCVD), and Atomic Layer Deposition (ALD), and the first stacked structure 20 may be formed by selecting a deposition method according to actual requirements.
Note that the thicknesses of the first material layers 21 and the second material layers 22 alternately stacked in the first stacked structure 20 are substantially uniform, and if the thickness is defined as D, as shown in fig. 3, the thicknesses of the first material layers 21 existing in the first stacked structure 20 are greater than D. For example, the thickness of the first material layer 21 on the second material layer 22 of the sub-bottom layer in the first stacked structure 20 is greater than D; the thickness of the first material layer 21 on the second-highest layer in the first stacked structure 20 is greater than D, and the thickness of these layers is related to the formation process of the three-dimensional memory, in other words, fig. 3 is only an illustration and is not used to limit the specific thickness of each layer in the first stacked structure 20 and the thickness distribution thereof. In other embodiments, the layers in the first stacked structure 20 may have other thicknesses and distributions. In addition, in the manufacturing process of the first stacked structure 20, different stacking layers correspond to different stacking heights, for example, the number of stacked layers of the first stacked structure 20 may be 8, 32, 64, and the like, and the greater the number of layers of the first stacked structure 20, the higher the integration level. The number of the first material layers 21 and the second material layers 22 in the first stacked structure 20 is determined by the number of the memory cells required to be formed in the vertical direction, and the number of the stacked layers and the stacked height of the first stacked structure 20 can be designed according to the actual memory requirement.
In the embodiment of the present application, the first material layer 21 is used as an insulating layer, the second material layer 22 is used as a gate sacrificial layer, and since the second material layer 22 and the first material layer 21 have different etching selectivity, the second material layer 22 used as the gate sacrificial layer will be removed in a subsequent process to form a word line opening, and a highly conductive material will be filled in a space of the word line opening, i.e., the second material layer 22, to form a word line, i.e., a gate. Specifically, the material of the first material layer 21 as the insulating layer may be an insulating dielectric material such as silicon oxide, aluminum oxide, hafnium oxide, or tantalum oxide, the material of the second material layer 22 as the gate sacrificial layer may be silicon nitride, the material of the gate may be metal tungsten, cobalt, copper, nickel, or the like, and may also be polysilicon, doped silicon, or any combination thereof. The selection can be performed according to the actual situation, and the application does not specifically limit the selection.
S300: the first stacked structure 20 is etched to form a first sub-channel hole 23 penetrating the first stacked structure 20.
In the embodiment of the present application, before etching the first stacked structure 20 to form the first sub-channel hole 23 penetrating the first stacked structure 20, a patterned first mask layer (not shown) is formed on a surface of the first stacked structure 20 facing away from the substrate 10. To form an opening in the patterned first mask layer corresponding to the first sub-channel hole 23, the opening exposes a position of the first sub-channel hole 23 to be etched by a subsequent etching process, i.e. a perpendicular projection of the opening on a surface of the first stacked structure 20 facing away from the substrate 10 may at least substantially overlap with the position of the first sub-channel hole 23. By arranging the first mask layer, the etching position of the first sub-channel hole 23 can be quickly and accurately determined, and the first stacked structure 20 can be conveniently etched.
As shown in fig. 3, after exposing the position of the first sub-channel hole 23, an appropriate etching process, such as a dry etching or a wet etching, is performed to remove the portion of the first stacked structure 20 exposed by the opening to form the first sub-channel hole 23 until the first sub-channel hole 23 formed by etching exposes the substrate 10. In other words, the first sub-channel hole 23 is a through hole penetrating the first stacked structure 20, and is a part of a channel hole finally used to form the memory cell string. The first sub-channel hole 23 extends from the surface of the first stacked structure 20 facing away from the substrate 10 to the stacked surface 101 of the substrate 10 to expose the substrate 10, and a portion of the first sub-channel hole 23 is located in the substrate 10 but does not penetrate through the substrate 10. After the first sub-channel hole 23 is formed, the first mask layer may be removed.
It should be noted that, in the step S200, the plurality of first sub-channel holes 23 may be formed simultaneously, that is, the first mask layer may form a plurality of openings respectively corresponding to the plurality of first sub-channel holes 23, and the positions of the plurality of openings correspond to the positions of the plurality of first sub-channel holes 23 to be formed subsequently. The number, size and arrangement of the first sub-channel holes 23 are not particularly limited in the embodiments of the present application. That is, the first sub-channel holes 23 shown in fig. 3 are only examples and are not intended to limit the positions and the number of the first sub-channel holes 23.
In a specific implementation scenario, the first sub-channel hole 23 is formed by plasma dry etching. In the etching process, as the depth of the pore channel increases, the plasma entering the bottom of the pore channel decreases, the deeper the pore channel is, the less the plasma is, the slower the corresponding etching rate is, and the finally formed first sub-channel hole 23 has a side wall structure of an inverted trapezoid pore channel with a larger top aperture compared with a bottom aperture and a smaller bottom aperture.
Of course, in other embodiments, the inclination of the sidewall of the first sub-channel hole 23 may be adjusted by adjusting the etching process parameters or by using a high aspect ratio etching process. This is not specifically limited by the present application.
In the embodiment of the present application, after the first stacked structure 20 is etched to form the first sub-channel hole 23 penetrating the first stacked structure 20, the epitaxial layer 40 is formed at the bottom of the first sub-channel hole 23.
Specifically, the epitaxial layer 40 may be a silicon layer deposited at the bottom of each first sub-channel hole 23 by Selective Epitaxial Growth (SEG), and then, a suitable doping process may be performed on the silicon layer to form the epitaxial layer 40, for example, the silicon layer may be doped by an ion implantation technique (implantation) to improve the conductivity of the first sub-channel hole 23.
It is understood that the epitaxial layer 40 is formed at the bottom of the first sub-channel hole 23 and covers the substrate 10, and the upper surface of the epitaxial layer 40 exceeds the upper surface of the second material layer 22 in the first stacked structure 20 near the sub-bottom layer of the substrate 10, so that after the gate is formed by the second material layer 22 in the subsequent first stacked structure 20, the epitaxial layer 40 and the gate adjacent thereto can form a source gate of the three-dimensional memory. Wherein the epitaxial layer 40 serves as a channel of the source gate tube.
Referring to fig. 4 and 5, fig. 4 is a schematic structural diagram of a first gate slit of a three-dimensional memory according to an embodiment of the present disclosure; fig. 5 is a schematic structural diagram of a first sacrificial layer of a three-dimensional memory according to an embodiment of the present disclosure.
S400: the first stacked structure 20 is etched at a side located at the first sub-channel hole 23 to form a first sub-gate slit 24 penetrating the first stacked structure 20.
In the embodiment of the present application, before etching the first stacked structure 20 at a side of the first sub-channel hole 23 to form the first sub-gate slit 24 penetrating through the first stacked structure 20, a patterned second mask layer (not shown) is formed on a surface of the first stacked structure 20 facing away from the substrate 10, so as to form an opening corresponding to the first sub-gate slit 24 in the patterned second mask layer, where the opening exposes a position of the first sub-gate slit 24 to be etched by a subsequent etching process, that is, a vertical projection of the opening on the surface of the first stacked structure 20 facing away from the substrate 10 may at least substantially overlap with the position of the first sub-gate slit 24. By arranging the second mask layer, the etching position of the first sub-gate gap 24 can be quickly and accurately determined, and the first stacked structure 20 is conveniently etched.
Specifically, after the position of the first sub-gate slit 24 is exposed, an appropriate etching process, for example, a dry etching process or a wet etching process, is performed to remove the portion of the first stacked structure 20 exposed by the opening to form the first sub-gate slit 24 until the first sub-gate slit 24 formed by etching exposes the substrate 10. In other words, the first sub-gate slit 24 is a via hole penetrating the first stacked structure 20, and is a part of a gate slit finally used to divide a core region of the three-dimensional memory into a plurality of block memory regions and/or finger memory regions. The first sub-gate slit 24 extends from a surface of the first stacked structure 20 facing away from the substrate 10 to the stacking surface 101 of the substrate 10, and a portion of the first sub-gate slit 24 is located in the substrate 10, but does not penetrate through the substrate 10. After the first sub-gate slits 24 are formed, the second mask layer may be removed.
It should be noted that, in the step S200, a plurality of first sub-gate slits 24 may be formed at the same time, that is, the first mask layer may form a plurality of openings respectively corresponding to the plurality of first sub-gate slits 24, and the positions of the plurality of openings correspond to the positions of the plurality of first sub-gate slits 24 formed subsequently. The number, size and arrangement of the first sub-gate slits 24 are not particularly limited in the embodiments of the present application. That is, the first sub-gate slits 24 shown in fig. 4 are only examples and are not intended to limit the positions and the number of the first sub-gate slits 24.
In a specific implementation scenario, the first sub-gate slit 24 is formed by using a plasma dry etching method. In the etching process, as the depth of the pore channel increases, the plasma entering the bottom of the pore channel decreases, the deeper the pore channel is, the less the plasma is, the slower the corresponding etching rate is, and the finally formed first sub-gate gap 24 has a side wall structure of an inverted trapezoid pore channel with a larger top aperture compared with a bottom aperture and a smaller bottom aperture.
Of course, in other embodiments, the inclination of the sidewall of the first sub-gate gap 24 may be adjusted by adjusting the etching process parameters or by using a high aspect ratio etching process. This is not specifically limited by the present application.
In the embodiment of the present application, after the first stacked structure 20 is etched on the side of the first sub-channel hole 23 to form the first sub-gate slit 24 penetrating through the first stacked structure 20, the oxide layer 50 is formed on the surface of the epitaxial layer 40 facing away from the substrate 10 and at the bottom of the first sub-gate slit 24. For example, the oxide layer 50 may serve as an insulating layer, which is made of oxide (oxide).
As shown in fig. 4, a layer closest to the substrate 10 in the first stacked structure 20 is a first material layer 21 as an insulating layer, which covers the stacked surface 101 of the substrate 10 so that the substrate 10 does not have an exposed area. However, after the first sub-channel hole 23 and the first sub-gate slit 24 are formed, the bottom of the first sub-channel hole 23 covers the surface of the exposed epitaxial layer 40, and the bottom of the first sub-gate slit 24 exposes the substrate 10, so that there is a risk of leaking charged particles.
Therefore, the oxide layer 50 is formed to insulate the epitaxial layer 40 and the substrate 10, so that the stack surface 101 of the epitaxial layer 40 and the substrate 10 does not have an exposed area, charged particles are effectively prevented from entering the first sub-channel hole 23 and the first sub-gate gap 24 through the epitaxial layer 40 and the substrate 10, the etched particles are prevented from being deflected due to the influence of electronic force on the etched particles in the subsequent process after being charged, the etching can be performed according to an expected direction, and the yield and the working stability of the three-dimensional memory are improved.
It can be understood that after the first sub-channel hole 23 and the first sub-gate slit 24 are formed by etching the first stacked structure 20, there is a space for forming the first sub-channel hole 23 and the first sub-gate slit 24 that are not filled in the first stacked structure 20, and if a stacked structure is to be formed on the first stacked structure 20, the existence of the first sub-channel hole 23 and the first sub-gate slit 24 that are not filled may cause a deposition material to enter the first sub-channel hole 23 and the first sub-gate slit 24, thereby affecting the electrical performance of the three-dimensional memory.
Thus, as shown in fig. 5, after the oxide layer 50 is formed on the surface of the epitaxial layer 40 away from the substrate 10 and at the bottom of the first sub-gate slit 24, a first sacrificial layer deposition process is simultaneously performed on the first sub-channel hole 23 and the first sub-gate slit 24 to form the first sacrificial layer 25 in the first sub-channel hole 23 and the first sub-gate slit 24. The first sacrificial layer 25 can fill the first sub-channel hole 23 and the first sub-gate slit 24, so as to support the subsequent formation of other stacked structures. And the first sacrificial layer 25 is deposited simultaneously on the first sub-channel holes 23 and the first sub-gate slits 24, so that the time spent on sequentially depositing the first sacrificial layer 25 in the first sub-channel holes 23 and the first sub-gate slits 24 can be greatly reduced, the production process is saved, and the production efficiency is effectively improved.
In the embodiment of the present application, the material of the first sacrificial layer 25 is Polysilicon (Polysilicon), and it should be noted that when filling a deep hole, that is, the first sub-channel hole 23, with a material, a void is likely to occur, and especially when filling the Polysilicon in the first sub-channel hole 23, a larger void is generated, which is a normal process phenomenon. Of course, in other embodiments, the material of the first sacrificial layer 25 may also be other materials such as silicon oxide, photoresist, etc., and the application is not limited thereto.
In the embodiment of the present application, after the first sacrificial layer 25 is formed, the top surface of the first sacrificial layer 25 is flush with the top surface of the top layer of the first stacked structure 20. The second material layer 22 is the top layer of the first stacked structure 20, and the first material layer 21 is the next-to-top layer, and the second material layer 22 as a sacrificial layer will be removed in the subsequent process, leaving only the first material layer 21 as the next-to-top layer, which will be described in detail below.
Referring to fig. 6 to 11, fig. 6 is a schematic partial cross-sectional view illustrating a first stacked structure of a three-dimensional memory according to an embodiment of the present disclosure; FIG. 7 is a schematic process flow diagram of the first stacked structure shown in FIG. 6; FIG. 8 is a schematic view of another process flow of the first stacked structure shown in FIG. 6; FIG. 9 is a schematic view of another process flow of the first stacked structure shown in FIG. 6; FIG. 10 is a schematic view of another process flow of the first stacked structure shown in FIG. 6; fig. 11 is a schematic structural diagram of a first stacked structure of a three-dimensional memory according to an embodiment of the present disclosure.
First, as shown in fig. 6 and 7, the first sacrificial layer 25 is etched to the bottom of the top layer of the first stacked structure 20, wherein the top layer of the first stacked structure 20 is the second material layer 22. At this time, the top surface of the first sacrificial layer 25 is located below the top surface of the second uppermost layer. For example, the etching method may be a position-etch-position (DED).
Next, as shown in fig. 8, the top layer of the first stacked structure 20 is removed to expose the sub-top layer of the first stacked structure 20, wherein the sub-top layer of the first stacked structure 20 is the first material layer 21. In other words, the top layer of the first stacked structure 20 is a base layer formed in the first stacked structure 20, and is removed as a sacrificial layer in a subsequent process.
Next, the top sidewall of the first sub-channel hole 23 and the top sidewall of the first sub-gate slit 24 are etched to enlarge the top aperture of the first sub-channel hole 23 and the top aperture of the first sub-gate slit 24, respectively. It is understood that after the top layer is removed, the top sub-channel hole 23 and the top aperture of the first sub-gate slit 24 are enlarged by etching the top sub-layer, thereby forming an alignment process window (OVL window) to facilitate alignment (OVL) of the first stacked structure 20 when a stacked structure is additionally formed on the first stacked structure 20.
Then, as shown in fig. 9, a second sacrificial layer deposition process is simultaneously performed on the first sub-channel holes 23 and the first sub-gate slits 24 to form a second sacrificial layer 26 on the first sacrificial layer 25, wherein the second sacrificial layer 26 covers the first sacrificial layer 25 and the second top layer. It is understood that, since the first sacrificial layer 25 is etched in the foregoing step, so that a portion of the first sacrificial layer 25 is removed, and thus the top surface of the first sacrificial layer 25 is lower than the top surface of the second top layer, in order to ensure that the first sub-channel holes 23 and the first sub-gate slits 24 are filled with the sacrificial material, a second sacrificial layer deposition process is performed to form the second sacrificial layer 26 filling the first sub-channel holes 23 and the first sub-gate slits 24. As shown in fig. 8, the first sacrificial layer 25 is below the dotted line, and the second sacrificial layer 26 is above the dotted line.
Finally, as shown in fig. 10, the second sacrificial layer 26 is planarized to expose the surface of the secondary top layer such that the top surface of the secondary top layer is flush with the top surface of the second sacrificial layer 26. It is understood that the surface of the second sacrificial layer 26 covering the first sacrificial layer 25 and the sub-top layer is not flat, and therefore, the second sacrificial layer 26 needs to be planarized, after which the portion of the second sacrificial layer 26 on the sub-top layer is removed to expose the sub-top layer, and the surface of the sub-top layer of the second sacrificial layer 26 filling the first sub-channel holes 23 and the first sub-gate slits 24 is flush, thereby forming the filled first stacked structure 20 as shown in fig. 11. The planarization process may be a Chemical Mechanical Polishing (CMP) process or a recess etching process, and a person skilled in the art can select an appropriate method to perform the planarization process according to actual situations, and only needs to ensure that the top surface of the sub-top layer is flush with the top surface of the second sacrificial layer 26, which is not limited in this application.
Further, a cap layer (not shown) may be formed on top of the first stacked structure 20, the cap layer is made of the same material as the sub-top layer, and the cap layer covers the sub-top layer of the first stacked structure 20 to supplement a portion of the material of the sub-top layer consumed during the planarization process in the previous step and protect the first stacked structure 20.
Referring to fig. 12, fig. 12 is a schematic structural diagram of a second stack structure of a three-dimensional memory according to an embodiment of the present disclosure.
S500: a second stacked structure 30 is formed on a side of the first stacked structure 20 facing away from the substrate 10.
It is understood that the surface of the second-order layer and the surface of the second sacrificial layer 26 together form a plane which is a side of the first stacked structure 20 facing away from the substrate 10. In other words, the second stacked structure 30 is formed on a plane formed by the surface of the second-level layer of the first stacked structure 20 and the surface of the second sacrificial layer 26.
In the embodiment of the present application, the second stacked structure 30 includes the third material layer 31 and the fourth material layer 32 alternately stacked, and the second stacked structure 30 having a multi-layer structure is formed by successive alternate deposition of the third material layer 31 and the fourth material layer 32. The deposition methods of the third material layer 31 and the fourth material layer 32 may be CVD, PVD, PECVD, sputtering, MOCVD, and atomic layer deposition, and the deposition method may be selected according to actual requirements to form the second stacked structure 30.
It should be noted that the thicknesses of the third material layers 31 and the fourth material layers 32 alternately stacked in the second stacked structure 30 are substantially the same, and if the thickness is defined as D, as shown in fig. 10, the thicknesses of the several third material layers 31 existing in the second stacked structure 30 are greater than D. For example, the thickness of the third material layer 31 closest to the first stacked structure 20 in the second stacked structure 30 is greater than D; the thickness of the third material layer 31 of the second stacked structure 30, except for the top layer, closest to the top layer is greater than D, and the arrangement of these layer thicknesses is related to the formation process of the three-dimensional memory, in other words, fig. 10 is only schematic and is not intended to limit the specific thickness of each layer in the first stacked structure 20 and the thickness distribution thereof. In other embodiments, the layers in the second stacked structure 30 may have other thicknesses and distributions.
In addition, in the manufacturing process of the second stack structure 30, different stacking layers correspond to different stacking heights, for example, the number of stacked layers of the second stack structure 30 may be 8, 32, 64, and the like, and the greater the number of layers of the second stack structure 30, the higher the integration level. The number of layers of the third material layer 31 and the fourth material layer 32 in the second stacked structure 30 is determined by the number of memory cells required to be formed in the vertical direction, the number of stacked layers and the stacked height of the second stacked structure 30 may be designed according to actual memory requirements, and the number of stacked layers and the stacked height of the second stacked structure 30 may be the same as or different from that of the first stacked structure 20.
In the embodiment of the present application, the third material layer 31 is used as an insulating layer, the fourth material layer 32 is used as a gate sacrificial layer, and since the fourth material layer 32 and the third material layer 31 have different etching selectivity, the fourth material layer 32 used as the gate sacrificial layer will be removed in a subsequent process to form a word line opening, and a highly conductive material will be filled in the space of the word line opening, i.e., the fourth material layer 32, to form a word line, i.e., a gate. Specifically, the material of the third material layer 31 as the insulating layer may be an insulating dielectric material such as silicon oxide, aluminum oxide, hafnium oxide, or tantalum oxide, the material of the fourth material layer 32 as the gate sacrificial layer may be silicon nitride, the material of the gate may be metal tungsten, cobalt, copper, nickel, or the like, and may also be polysilicon, doped silicon, or any combination thereof. The selection can be performed according to the actual situation, and the application does not specifically limit the selection.
Referring to fig. 12-14, fig. 12 is a schematic structural diagram of a second stacked structure 30 of a three-dimensional memory according to an embodiment of the present disclosure; FIG. 13 is a schematic diagram of a channel hole of a three-dimensional memory according to an embodiment of the present disclosure; fig. 14 is a schematic structural diagram of a channel hole of a three-dimensional memory according to an embodiment of the present disclosure, in which a blocking layer, a memory layer, a tunneling layer, and a channel layer are sequentially formed on an inner wall of the channel hole.
S600: the second stack structure 30 is etched at a position of the second stack structure 30 aligned with the first sub-channel hole 23 to form a second sub-channel hole 33 penetrating the second stack structure 30, wherein a bottom of the second sub-channel hole 33 is communicated with a top of the first sub-channel hole 23.
In the embodiment of the present application, before the second stacked structure 30 is etched to form the second sub-channel hole 33, a patterned third mask layer (not shown) is formed on a surface of the second stacked structure 30 facing away from the first stacked structure 20, so as to form an opening corresponding to the second sub-channel hole 33 in the patterned third mask layer, where the opening exposes a position of the second sub-channel hole 33 to be etched by a subsequent etching process, that is, a vertical projection of the opening on the surface of the second stacked structure 30 facing away from the first stacked structure 20 may at least substantially overlap with the position of the second sub-channel hole 33. By arranging the third mask layer, the etching position of the second sub-channel hole 33 can be determined quickly and accurately, and the second stacked structure 30 can be etched conveniently.
As shown in fig. 12, after exposing the position of the second sub-channel hole 33, an appropriate etching process, for example, dry etching or wet etching, is performed to remove the portion of the second stack structure 30 exposed by the opening to form the second sub-channel hole 33 until the first sub-channel hole 23 is exposed by the second sub-channel hole 33. In other words, the second sub-channel hole 33 is a through hole penetrating the second stack structure 30, and is another portion of a channel hole finally used to form the memory cell string. The second sub-channel hole 33 extends into the first sub-channel hole 23 from a surface of the second stacked structure 30 facing away from the first stacked structure 20, a bottom of the second sub-channel hole 33 exposes a top of the first sub-channel hole 23, and the bottom of the second sub-channel hole 33 is located in the top of the first sub-channel hole 23 and is communicated with the top of the first sub-channel hole 23. After the second sub-channel hole 33 is formed, the third mask layer may be removed.
It is understood that the third mask layer for forming the second sub-channel hole 33 may be the same as the first mask layer for forming the first sub-channel hole 23 in step S300 to etch the second sub-channel hole 33 coinciding with the center line of the first sub-channel hole 23.
It should be noted that, in the step S500, the plurality of second sub-channel holes 33 may be formed simultaneously, that is, the third mask layer may form a plurality of openings respectively corresponding to the plurality of second sub-channel holes 33, and the positions of the plurality of openings correspond to the positions of the plurality of second sub-channel holes 33 to be formed subsequently. The number, size and arrangement of the second sub-channel holes 33 are not particularly limited in the embodiments of the present application. It is understood that each second sub-channel hole 33 in the second stacked structure 30 is communicated with a corresponding one of the first sub-channel holes 23 in the first stacked structure 20, that is, the second sub-channel holes 33 are in one-to-one correspondence with the first sub-channel holes 23, and each second sub-channel hole 33 is communicated with one of the first sub-channel holes 23 to form a channel hole for forming a memory cell string.
In a specific implementation scenario, the second sub-channel hole 33 is formed by plasma dry etching. In the etching process, as the depth of the pore channel increases, the plasma entering the bottom of the pore channel decreases, the deeper the pore channel is, the less the plasma is, the slower the corresponding etching rate is, and the finally formed second sub-channel hole 33 has a side wall structure of an inverted trapezoid pore channel with a larger top aperture and a smaller bottom aperture compared with the bottom aperture.
Of course, in other embodiments, the inclination of the sidewall of the second sub-channel hole 33 may be adjusted by adjusting the etching process parameters or by using a high aspect ratio etching process. This is not specifically limited by the present application.
As shown in fig. 12 and 13, in the embodiment of the present application, in the process of forming the second sub-channel hole 33 by etching, the sacrificial materials (the first sacrificial layer 25 and the second sacrificial layer 26) at the top of the first sub-channel hole 23 are removed together. After the second stack structure 30 is etched at a position of the second stack structure 30 aligned with the first sub-channel hole 23 to form a second sub-channel hole 33 penetrating the second stack structure 30, the first sacrificial layer 25 and the second sacrificial layer 26 in the first sub-channel hole 23 are removed to form a channel hole 70 through the first sub-channel hole 23 and the second sub-channel hole 33. In other words, the channel hole 70 is formed by two times of etching. Compared with the channel hole formed by the conventional single etching with a high stacking height, the stacking height of the first stacking structure 20 and the second stacking structure 30 is low, so that the etching height required for etching the first sub-channel hole 23 and the second sub-channel hole 33 can be respectively reduced, on one hand, the profile distortion of the first sub-channel hole 23 and the second sub-channel hole 33 can be improved due to the low depth-to-width ratio of each etching, so that the profile distortion of the channel hole 70 formed after the first sub-channel hole 23 and the second sub-channel hole 33 are communicated is improved, on the other hand, the inclination risk of the channel hole 70 can be greatly reduced, the inclination of the channel hole 70 is improved, and the electrical performance of the three-dimensional memory and the yield of the three-dimensional memory are improved.
In addition, in the embodiment of the present application, after the first sacrificial layer 25 and the second sacrificial layer 26 in the first sub-channel hole 23 are removed and the channel hole 70 is formed by penetrating the first sub-channel hole 23 and the second sub-channel hole 33, the barrier layer 61, the memory layer 62, the tunneling layer 63, and the channel layer 64 may be sequentially formed on the sidewall of the channel hole 70 by ALD, CVD, PVD, or any other suitable process to form an Oxide-Nitride-Oxide-polysilicon (ONOP) structure.
As shown in fig. 14, a blocking layer 61 is formed between the memory layer 62 and the sidewall of the channel hole for blocking the outflow of the electron charges. The memory layer 62 is formed between the tunneling layer 63 and the blocking layer 61, and may allow electrons or holes from the channel layer 64 to tunnel through the tunneling layer 63 to the memory layer 62 to store electron charges (electrons or holes) for a memory operation. The storage or removal of charge in the storage layer 62 can affect the on/off state and/or conductance of the semiconductor channel. A tunneling layer 63 is formed between the channel layer 64 and the storage layer 62 for tunneling electron charges (electrons or holes). The channel layer 64 is formed on the sidewall of the tunneling layer 63, and the channel layer 64 is a polysilicon layer.
Further, after the barrier layer 61, the memory layer 62, the tunneling layer 63 and the channel layer 64 are sequentially formed on the sidewall of the channel hole 70, the insulating layer 65 is formed to fill the channel hole 70. It is understood that the insulating layer 65 may serve as a core of the channel hole 70, and the channel layer 64, the tunneling layer 63, the memory layer 62, and the barrier layer 61 sequentially form a stacked structure surrounding the core. The insulating layer may include one or more air gaps.
Referring to fig. 15, fig. 15 is a schematic structural diagram of a gate slit of a three-dimensional memory according to an embodiment of the present disclosure.
S700: and etching the second stack structure 30 at a position of the second stack structure 30 aligned with the first sub-gate slit 24 to form a second sub-gate slit 34 penetrating through the second stack structure 30, wherein the bottom of the second sub-gate slit 34 is communicated with the top of the first sub-gate slit 24.
In the embodiment of the present application, before the second stacked structure 30 is etched to form the second sub-gate slits 34, a patterned fourth mask layer (not shown) is formed on a surface of the second stacked structure 30 away from the first stacked structure 20, so as to form openings corresponding to the second sub-gate slits 34 in the patterned fourth mask layer, where the openings expose positions of the second sub-gate slits 34 to be etched by a subsequent etching process, that is, a vertical projection of the openings on the surface of the second stacked structure 30 away from the first stacked structure 20 may at least substantially overlap the positions of the second sub-gate slits 34. By arranging the fourth mask layer, the etching position of the second sub-gate gap 34 can be determined quickly and accurately, and the second stack structure 30 can be etched conveniently.
Specifically, after the position of the second sub-gate slit 34 is exposed, an appropriate etching process, for example, a dry etching process or a wet etching process, is performed to remove the portion of the second stack structure 30 exposed by the opening to form the second sub-gate slit 34 until the second sub-gate slit 34 exposes the first sub-gate slit 24. In other words, the second sub-gate slit 34 is a via hole penetrating the second stack structure 30 in order to finally form another portion of the gate slit for dividing the core region of the three-dimensional memory into a plurality of block memory regions and/or finger memory regions. The second sub-gate slits 34 extend into the first sub-gate slits 24 from the surface of the second stacked structure 30 facing away from the first stacked structure 20, the bottom of the second sub-gate slits 34 expose the top of the first sub-gate slits 24, and the bottom of the second sub-gate slits 34 is located in the top of the first sub-gate slits 24 and is communicated with the top of the first sub-gate slits 24. And the fourth mask layer may be removed after the second sub-gate slits 34 are formed.
It is understood that the fourth mask layer for forming the second sub-gate slits 34 may be the same as the second mask layer for forming the first sub-gate slits 24 in step S400 to etch the second sub-gate slits 34 coinciding with the center lines of the first sub-gate slits 24.
It should be noted that, in the step S600, a plurality of second sub-gate slits 34 may be formed at the same time, that is, the fourth mask layer may form a plurality of openings respectively corresponding to the plurality of second sub-gate slits 34, and the positions of the plurality of openings correspond to the positions of the plurality of second sub-gate slits 34 formed subsequently. The number, size and arrangement of the second sub-gate slits 34 are not particularly limited in the embodiments of the present application. It is understood that each second sub-gate slit 34 in the second stacked structure 30 is communicated with a corresponding first sub-gate slit 24 in the first stacked structure 20, that is, the second sub-gate slits 34 are in one-to-one correspondence with the first sub-gate slits 24, and each second sub-gate slit 34 is communicated with one first sub-gate slit 24 to form a gate slit for dividing the core area of the three-dimensional memory into a plurality of block memory areas and/or finger memory areas.
In a specific implementation scenario, the second sub-gate slit 34 is formed by using a plasma dry etching method. In the etching process, as the depth of the channel increases, the plasma entering the bottom of the channel decreases, the deeper the channel is, the less the plasma is, the slower the corresponding etching rate is, and the finally formed second sub-gate gap 34 has a side wall structure of an inverted trapezoid channel with a larger top aperture compared with a bottom aperture and a smaller bottom aperture.
Of course, in other embodiments, the inclination of the sidewall of the second sub-gate gap 34 may also be adjusted by adjusting the etching process parameters or by using a high aspect ratio etching process. This is not specifically limited by the present application.
In the embodiment of the present application, after the second stacked structure 30 is etched at the position of the second stacked structure 30 aligned with the first sub-gate slit 24 to form the second sub-gate slit 34 penetrating through the second stacked structure 30, the first sacrificial layer 25 and the second sacrificial layer 26 in the first sub-gate slit 24 are removed, so that the first sub-gate slit 24 and the second sub-gate slit 34 penetrate through to form the gate slit 80. The gate slit 80 may serve as an etchant passage for forming a word line opening by removing the fourth material layer 32, which serves as a sacrificial layer, in the first and second stacked structures 20 and 30 using isotropic etching.
It is understood that in the case where the third material layer 31 and the fourth material layer 32 in the first stack structure 20 and the second stack structure 30 are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and one or more of C4F8, C4F6, CH2F2, and O2 may be used in vapor etching. During the etching step, the gate gap 80 is filled with an etchant. The end portions of the fourth material layer 32 in the first and second stacked structures 20 and 30 are exposed in the opening of the gate slit 80, and thus, the fourth material layer 32 is contacted to the etchant. The etchant gradually etches the fourth material layer 32 from the opening of the gate slit 80 toward the interior of the first stacked structure 20 and the second stacked structure 30. Due to the selectivity of the etchant, the etching removes the third material layer 31 with respect to the third material layer 31 to form the word line opening. Next, the gate gap 80 and the word line openings may be filled with a gate metal using a suitable deposition method, such as Atomic Layer Deposition (ALD), using the gate gap 80 as a deposition path to form word lines, i.e., gates.
According to the preparation method of the three-dimensional memory, two stacked structures, namely a first stacked structure 20 and a second stacked structure 30, are formed by stacking on a substrate 10 twice, first etching is carried out on the first stacked structure 20 to form a first sub-gate gap 24, second etching is carried out on the second stacked structure 30 to form a second sub-gate gap 34 communicated with the first sub-gate gap 24, and therefore a through gate gap 80 is formed by etching twice. Compared with the gate gap formed by the conventional single etching with high stacking height, the stacking height of the first stacking structure 20 and the second stacking structure 30 is low, so that the etching height required for etching the first sub-gate gap 24 and the second sub-gate gap 34 can be respectively reduced, on one hand, the profile distortion of the first sub-gate gap 24 and the second sub-gate gap 34 can be improved due to the low depth-to-width ratio of each etching, so that the profile distortion of the gate gap 80 formed after the first sub-gate gap 24 and the second sub-gate gap 34 are penetrated is improved, on the other hand, the inclination risk of the gate gap 80 can be greatly reduced, the inclination of the gate gap 80 is improved, the problem of leakage current caused by the subsequent process of filling gate metal in the word line opening is avoided, and the electrical performance of the three-dimensional memory and the yield of the three-dimensional memory are improved.
The method for manufacturing a three-dimensional memory according to the embodiment of the present invention is described above, and the embodiment of the present invention also provides a three-dimensional memory that can be manufactured using, but not limited to, the above manufacturing method. The effects and structures of the three-dimensional memory device are described above and will not be described here.
The foregoing is illustrative of the present invention and it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and are intended to be within the scope of the invention.
Claims (10)
1. A preparation method of a three-dimensional memory is characterized by comprising the following steps:
providing a substrate, wherein the substrate has a stacking face;
forming a first stacked structure on the stacked surface of the substrate;
etching the first stacked structure to form a first sub-channel hole penetrating through the first stacked structure;
etching the first stacked structure at one side of the first sub-channel hole to form a first sub-gate gap penetrating through the first stacked structure;
forming a second stacked structure on the side of the first stacked structure, which faces away from the substrate;
etching the second stacked structure at a position of the second stacked structure aligned with the first sub-channel hole to form a second sub-channel hole penetrating through the second stacked structure, wherein the bottom of the second sub-channel hole is communicated with the top of the first sub-channel hole;
and etching the second stacked structure at the position of the second stacked structure, which is aligned with the first sub-gate gap, so as to form a second sub-gate gap penetrating through the second stacked structure, wherein the bottom of the second sub-gate gap is communicated with the top of the first sub-gate gap.
2. The method of claim 1, wherein after the etching the first stacked structure to form a first sub-channel hole extending through the first stacked structure and before the etching the first stacked structure on a side of the first sub-channel hole to form a first sub-gate slit extending through the first stacked structure, the method comprises:
and forming an epitaxial layer at the bottom of the first sub-channel hole.
3. The method of claim 2, wherein after the etching the first stacked structure on the side of the first sub-channel hole to form the first sub-gate slit penetrating the first stacked structure and before the forming the second stacked structure on the side of the first stacked structure away from the substrate, the method comprises:
and forming an oxide layer on the surface of the epitaxial layer departing from the substrate and at the bottom of the first sub-gate gap.
4. The method according to claim 3, wherein after the step of forming the oxide layer on the surface of the epitaxial layer facing away from the substrate and at the bottom of the first sub-gate slit and before the step of forming the second stacked structure on the side of the first stacked structure facing away from the substrate, the method comprises:
and simultaneously carrying out a first sacrificial layer deposition process on the first sub-channel hole and the first sub-gate gap so as to form a first sacrificial layer in the first sub-channel hole and the first sub-gate gap.
5. The method according to claim 4, wherein after the step of performing a first sacrificial layer deposition process on the first sub-channel hole and the first sub-gate slit simultaneously to form a first sacrificial layer in the first sub-channel hole and the first sub-gate slit and before the step of forming a second stacked structure on a side of the first stacked structure facing away from the substrate, the method comprises:
etching the first sacrificial layer to the bottom of the top layer of the first stacked structure;
removing the top layer of the first stacked structure to expose the second top layer of the first stacked structure;
simultaneously performing a second sacrificial layer deposition process on the first sub-channel hole and the first sub-gate gap to form a second sacrificial layer on the first sacrificial layer, wherein the second sacrificial layer covers the first sacrificial layer and the second-to-top layer;
and carrying out planarization treatment on the second sacrificial layer to expose the surface of the secondary top layer.
6. The method of claim 5, wherein after the removing the top layer of the first stacked structure to expose the second-level top layer of the first stacked structure and before the performing a second sacrificial layer deposition process on the first sub-channel hole and the first sub-gate gap simultaneously to form a second sacrificial layer on the first sacrificial layer, the method comprises:
and etching the top side wall of the first sub-channel hole and the top side wall of the first sub-gate gap so as to respectively enlarge the top aperture of the first sub-channel hole and the top aperture of the first sub-gate gap.
7. The method for manufacturing a three-dimensional memory according to claim 6, wherein the step of forming a second stacked structure on a side of the first stacked structure facing away from the substrate comprises:
and forming a second stacked structure on the surface of the second-level layer of the first stacked structure and the surface of the second sacrificial layer, wherein a plane formed by the surface of the second-level layer and the surface of the second sacrificial layer is a surface of the first stacked structure, which is far away from the substrate.
8. The method for fabricating the three-dimensional memory according to claim 7, wherein after etching the second stack structure at a position of the second stack structure aligned with the first sub-channel hole to form a second sub-channel hole penetrating through the second stack structure, and before etching the second stack structure at a position of the second stack structure aligned with the first sub-gate gap to form a second sub-gate gap penetrating through the second stack structure, the method for fabricating the three-dimensional memory comprises:
and removing the first sacrificial layer and the second sacrificial layer in the first sub-channel hole to enable the first sub-channel hole and the second sub-channel hole to penetrate through to form a channel hole.
9. The method for fabricating the three-dimensional memory according to claim 8, wherein after the etching the second stacked structure at a position of the second stacked structure aligned with the first sub-gate gap to form a second sub-gate gap penetrating through the second stacked structure, the method for fabricating the three-dimensional memory comprises:
and removing the first sacrificial layer and the second sacrificial layer in the first sub-gate gap to enable the first sub-gate gap and the second sub-gate gap to penetrate through to form a gate gap.
10. A three-dimensional memory, wherein the three-dimensional memory is formed by the method of any one of claims 1 to 9.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112542464A (en) * | 2020-12-09 | 2021-03-23 | 长江存储科技有限责任公司 | Manufacturing method of three-dimensional memory |
| CN112563286A (en) * | 2020-12-09 | 2021-03-26 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
| CN113178453A (en) * | 2020-05-29 | 2021-07-27 | 长江存储科技有限责任公司 | Three-dimensional memory, preparation method thereof and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107810552A (en) * | 2015-08-25 | 2018-03-16 | 桑迪士克科技有限责任公司 | Use the method containing the chamber manufacture multi-level store stacked body structure for sacrificing packing material |
| CN109196645A (en) * | 2018-06-08 | 2019-01-11 | 长江存储科技有限责任公司 | The method for being used to form the dual stack channel pore structure of three-dimensional storage part |
| CN109417074A (en) * | 2018-09-27 | 2019-03-01 | 长江存储科技有限责任公司 | The semiconductor plug and forming method thereof protected in three-dimensional storage part by protectiveness dielectric layer |
| US20190221574A1 (en) * | 2018-01-18 | 2019-07-18 | Sandisk Technologies Llc | Three-dimensional memory device containing offset column stairs and method of making the same |
-
2020
- 2020-01-03 CN CN202010006488.4A patent/CN111162086A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107810552A (en) * | 2015-08-25 | 2018-03-16 | 桑迪士克科技有限责任公司 | Use the method containing the chamber manufacture multi-level store stacked body structure for sacrificing packing material |
| US20190221574A1 (en) * | 2018-01-18 | 2019-07-18 | Sandisk Technologies Llc | Three-dimensional memory device containing offset column stairs and method of making the same |
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| CN112563286A (en) * | 2020-12-09 | 2021-03-26 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
| CN112563286B (en) * | 2020-12-09 | 2023-11-28 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
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