CN112533046A - Audio data synchronization device and method thereof - Google Patents
Audio data synchronization device and method thereof Download PDFInfo
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- CN112533046A CN112533046A CN201911098617.0A CN201911098617A CN112533046A CN 112533046 A CN112533046 A CN 112533046A CN 201911098617 A CN201911098617 A CN 201911098617A CN 112533046 A CN112533046 A CN 112533046A
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- 230000005540 biological transmission Effects 0.000 claims abstract description 19
- 230000007423 decrease Effects 0.000 claims abstract description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000013500 data storage Methods 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4307—Synchronising the rendering of multiple content streams or additional data on devices, e.g. synchronisation of audio on a mobile phone with the video output on the TV screen
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/44004—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video buffer management, e.g. video decoder buffer or video display buffer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
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- Engineering & Computer Science (AREA)
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- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention discloses an audio data synchronization device and a method thereof, wherein the device comprises a universal sequence bus host, a processor and an audio codec, wherein the processor comprises a universal sequence bus module for receiving an audio packet from the universal sequence bus host; the first-in first-out buffer stores the audio packets; the clock generator generates a clock signal; the control unit stores a maximum data amount threshold value and a minimum data amount threshold value, and judges whether the data amount stored in the first-in first-out buffer is larger than the maximum data amount threshold value or smaller than the minimum data amount threshold value, so as to increase or decrease the frequency of the clock signal; and the audio codec receives the audio packet and the clock signal through the data transmission interface and processes the audio packet according to the clock signal so as to output audio.
Description
Technical Field
The present invention relates to audio data processing technology, and more particularly, to an audio data synchronization apparatus and method thereof.
Background
In many audio applications, audio playback using a Universal Serial Bus (USB) has become the mainstream. Generally, the audio processing requires the clock synchronization within the error range of 2500ppm, so a time error may occur every 2500ppm, and the accumulated time error may cause the sound to break.
Since the usb protocol is an asynchronous (asynchronous) design, and clock sources of the usb host for generating the audio packets and the audio codec for playing the codec audio packets are not consistent, the buffer for storing the audio packets is prone to have a problem of buffer overflow or underrun, which causes a sound break.
Disclosure of Invention
An objective of the present invention is to provide an audio data synchronization apparatus and method thereof, wherein a clock generator of a processor generates a clock signal and provides the clock signal to a counter and a data transmission interface, and the counter monitors a change in data storage capacity of a first-in-first-out (FIFO) buffer storing an audio packet to adjust a frequency of the clock signal, so as to prevent a break caused by an overflow or an underload of the FIFO buffer.
To achieve the above objective, the present invention provides an audio data synchronization device, which comprises a usb host, a processor and an audio codec. The USB host is used for transmitting an audio packet. The processor comprises a Universal Serial Bus (USB) module, a first-in first-out (FIFO) buffer, a clock generator, a control unit and a data transmission interface. The USB module is used for receiving the audio packets. The FIFO buffer is used to store the audio packets. The clock generator generates a clock signal. The control unit is used for storing a maximum data amount threshold value and a minimum data amount threshold value and judging whether the data amount stored in the first-in first-out buffer is larger than the maximum data amount threshold value or smaller than the minimum data amount threshold value. When the control unit judges that the data quantity stored in the first-in first-out buffer is larger than the maximum data quantity critical value, the control unit controls the clock generator to increase the frequency of the clock signal, and when the control unit judges that the data quantity stored in the first-in first-out buffer is smaller than the minimum data quantity critical value, the control unit controls the clock generator to decrease the frequency of the clock signal. The data transmission interface outputs the audio packets from the FIFO buffer and outputs the clock signal. The audio codec receives the audio packet and the clock signal through the data transmission interface, and processes the audio packet according to the clock signal to output audio.
According to an embodiment of the present invention, the data transmission interface is an Inter-IC Sound (I) interface between integrated circuits2S) interface, which is used to transmit audio package to audio coder-decoder.
According to an embodiment of the present invention, the processor includes a counter, and when the count of the counter reaches a predetermined value, the counter generates a trigger signal to the control unit to trigger the control unit to determine a state of the amount of data stored in the fifo buffer, so that the control unit repeatedly determines the state of the amount of data stored in the fifo buffer.
According to an embodiment of the present invention, the counter counts based on a clock signal.
According to an embodiment of the present invention, the clock signal is independent of the clock signal.
To achieve the above object, the present invention provides an audio data synchronization method, which comprises the following steps: receiving an audio packet from a USB host; storing the audio packets in a first-in first-out buffer; setting a maximum data amount critical value and a minimum data amount critical value of the first-in first-out buffer; generating a clock signal; outputting the audio packets and the clock signal from the FIFO buffer to an audio codec through a data transmission interface; processing the audio packet by using an audio codec according to the clock signal to output audio; judging whether the data amount stored in the first-in first-out buffer is larger than a maximum data amount threshold value or smaller than a minimum data amount threshold value; when the data amount stored in the first-in first-out buffer is judged to be larger than the maximum data amount critical value, the frequency of the clock signal is increased; and reducing the frequency of the clock signal when the data amount stored in the first-in first-out buffer is judged to be smaller than the minimum data amount threshold value.
According to an embodiment of the present invention, the data transmission interface is an I2And the S interface is used for transmitting the audio packet to an audio codec.
According to an embodiment of the present invention, the audio data synchronization method comprises using a counter, wherein when the count of the counter reaches a predetermined value, the counter generates a trigger signal to trigger the determination of the status of the amount of data stored in the fifo buffer, thereby repeatedly determining the status of the amount of data stored in the fifo buffer.
According to an embodiment of the present invention, the counter counts based on a clock signal.
According to an embodiment of the present invention, the clock signal is independent of the clock signal.
As mentioned above, the present invention provides an audio data synchronization apparatus and method, wherein a processor continuously counts the amount of data in a fifo buffer, and then feeds back the frequency of a control clock signal according to the amount of data, so that the speed of transmitting data by a usb host and the speed of an audio codec can be effectively synchronized, thereby avoiding the occurrence of a noise-breaking phenomenon due to the overflow or underload of data in the buffer caused by the lack of synchronization between the two.
Drawings
FIG. 1 is a block diagram of an audio data synchronization apparatus according to the present invention;
FIG. 2 is a second block diagram of the audio data synchronization apparatus according to the present invention;
FIG. 3 is a diagram illustrating the operation of the present invention to avoid FIFO data overflow;
FIG. 4 is a schematic diagram illustrating the operation of the present invention to avoid FIFO underrun;
FIG. 5 is a flow chart of an audio data synchronization method of the present invention;
fig. 6 is a flowchart of an embodiment of an audio data synchronization method of the present invention.
[ description of symbols ]
100: processor with a memory having a plurality of memory cells
101: universal serial bus host
1011: audio packet
111: universal sequence bus bar module
112: first-in first-out buffer
1121 amount of data
113: data transmission interface
114: control unit
115: counter with a memory
116: clock generator
1171: clock signal
120: trigger signal
130: audio codec
200: framework picture
201: universal serial bus host oscillator
301: maximum data amount threshold
302：I2S interface
401: minimum data threshold
501. 502, 503, 504, 505, 506, 601, 602, 603, 604, 605, 606, 607: step (ii) of
Detailed Description
Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily understand the embodiments. The invention described can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The description of the well-known part (well-known part) is omitted and like reference numerals refer to like elements in the present invention.
Referring to fig. 1 to 4, a block diagram and an operation diagram of an audio data synchronization apparatus according to the present invention are shown. As shown in fig. 1, the Audio data synchronization apparatus includes a Universal Serial Bus (USB) host 101, a processor 100, and an Audio codec (Audio codec) 130. The processor 100 is connected between the usb host 101 and the audio codec 130, and serves as a bridge between the usb host and the audio codec, and the processor 100 can receive the audio packets of the usb host 101 and then transmit the audio packets to the audio codec 130 as a sound source.
The processor 100 includes a Universal Serial Bus (USB) module 111, a first-in-first-out (FIFO) buffer 112, a clock generator 116, a control unit 114, a counter 115, and a data transmission interface 113. In one embodiment, the usb host may be disposed in a computer, and the audio codec 130 may be a microphone or a speaker connected to a usb port of the computer; the data transmission interface 113 may be an Inter-IC Sound (I) interface between ICs2S) interface.
The USB host 101 is configured to transmit an audio packet 1011 for storage in the FIFO 112 of the processor 100. The USB module 111 receives the audio packet 1011, the FIFO 112 stores the audio packet 1011, and the clock generator 116 generates a clock signal 1171. The data transmission interface 113 is used for outputting the audio packets 1011 from the FIFO buffer 112 and outputting the clock signal 1171 to the audio codec 130. The audio codec 130 may receive the audio packet 1011 and the clock signal 1171 through the data transmission interface 113 of the processor 100, and process the audio packet 1011 according to the clock signal 1171 to output audio.
Since the usb protocol is asynchronous (asynchronous) design, the usb host and the audio codec use independent clock signals, as shown in fig. 2, the usb host 101 uses the usb host oscillator 201 as a clock source, and the audio codec 130 uses the clock signal 1171 provided by the processor 100 as its clock source, so that the decoding processing speed (e.g. playing audio or recording) of the audio codec 130 is not synchronous with the audio packet generating speed (computer processing speed), and the packet processing time is long, which easily causes buffer data overflow or underload, and further generates noise break.
To solve this problem, the control unit 114 stores and sets a maximum data amount threshold 301 (as an upper limit) and a minimum data amount threshold 401 (as a lower limit), and determines whether the amount of data 1121 stored in the fifo buffer 112 is larger than the maximum data amount threshold 301 or smaller than the minimum data amount threshold 401.
As shown in fig. 3, when the control unit 114 determines that the amount of data 1121 stored in the fifo 112 is greater than the maximum data amount threshold 301, it indicates that the current speed of processing the audio packets by the audio codec 130 is slower than the speed of generating the audio packets, so that more and more data are stored in the fifo 112 and have reached the maximum data amount threshold 301, and once the data stored in the fifo 112 continuously increases and exceeds the storage capacity of the fifo 112, the buffer data overflows and is corrupted.
To avoid a sound break, the control unit 114 controls the clock generator 116 to increase the frequency of the clock signal 1171, since the audio codec 130 passes through I2The S-interface 302 obtains the clock signal as the clock source, so increasing the frequency of the clock signal 1171 increases the processing speed of the audio codec 130 to process more audio packets. Therefore, the data amount 1121 of the fifo 112 gradually decreases below the maximum data amount threshold 301.
When the control unit 114 determines that the amount of data 1121 stored in the fifo 112 is smaller than the minimum data amount threshold 401, it indicates that the audio codec 130 is currently processing audio packets faster than the audio packet generation speed, so that the fifo 112 stores less data and reaches the minimum data amount threshold 401; as soon as the amount of data stored in the FIFO 112 is continuously reduced and finally no audio packets are available for the audio codec 130 to process, a buffer underrun may occur, resulting in a glitch.
To avoid the noise-breaking, the control unit 114 controls the clock generator 116 to decrease the frequency of the clock signal 1171, thereby decreasing the processing speed of the audio codec 130 to process fewer audio packets. Therefore, the data amount of the fifo 112 gradually increases to be higher than the minimum data amount threshold 401.
If the amount of data 1121 stored in the FIFO 112 is between the maximum data amount threshold 301 and the minimum data amount threshold 401, no change is made to the clock speed. By the above control method, the processor 100 can continuously adjust the processing speed of the audio codec 130 to avoid the broadcast problem.
As further shown in fig. 1, the processor 100 may use the counter 115 to continuously trigger the control unit 114 to make the above determination. If the control unit 114 confirms the data amount of the fifo buffer 112 every millisecond, the change of the data amount of the fifo buffer 112 is not significant enough; therefore, the counter 115 can be set to count for a longer time (e.g., one second) so that the change of the data amount of the FIFO 112 is significant enough to determine whether to adjust the frequency of the clock 1171, thereby increasing the accuracy.
In one embodiment, the counter 115 outputs a trigger signal (or interrupt signal) 120, such as a trigger signal (tick)120, when it counts to a predetermined value. When the control unit 114 receives the trigger signal 120, the data amount 1121 of the fifo 112 is read, and the above determination is performed. The counter 115 resets (reset) its count value upon output of the trigger signal 120, and restarts the count. Counter 115 may count according to clock signal 1171.
In one embodiment, the clock generator 116 may include an oscillator that generates an oscillation signal and a clock signal generation unit that generates a clock signal suitable for the subsequent circuit according to the oscillation signal. The oscillator may be implemented as an RC oscillator or a crystal oscillator. To adjust or fine tune the frequency of the clock signal, the control unit 114 may change the voltage or current applied to the oscillator, thereby changing the frequency of the oscillating signal and thus the frequency of the clock signal. However, the above description is only exemplary and not limiting, and any technique of adjusting the frequency of the clock signal can be applied to the present invention.
Please refer to fig. 5, which is a flowchart illustrating an audio data synchronization method according to the present invention. As shown in fig. 5, the audio data synchronization method of the present invention includes the following steps 501 to 506. In step 501, an audio packet is received from a USB host. At step 502, audio packets are stored in a FIFO buffer. In step 503, a maximum data threshold 301 and a minimum data threshold 401 of the FIFO are set. In step 504, a clock signal is generated and the audio packets are output from the fifo buffer and the clock signal is output to an audio codec via a data transfer interface.
In step 505, it is determined whether the amount of data stored in the fifo buffer is greater than the maximum data amount threshold 301 or less than the minimum data amount threshold 401, and when the amount of data stored in the fifo buffer is greater than the maximum data amount threshold 301, the clock generator 116 is controlled to increase the frequency of the clock signal, and when the amount of data stored in the fifo buffer is less than the minimum data amount threshold 401, the clock generator 116 is controlled to decrease the frequency of the clock signal.
In step 506, the audio codec 130 is used to process the audio packet 1011 according to the clock signal 1171 to output audio. Therefore, the audio data synchronization method of the present invention can provide a clock signal 1171 to the audio codec 130 through the data transmission interface 113, and continuously monitor the change of the data storage amount of the fifo buffer 112 storing the audio packet 1011, when the data storage amount exceeds the upper limit, the frequency of the clock signal 1171 is reduced, when the data storage amount is lower than the lower limit, the frequency of the clock signal 1171 is increased, so as to adjust the frequency of the clock signal 1171, thereby effectively synchronizing the speed of processing the audio packet 1011 by the audio codec 130 with the speed of providing the audio packet 1011 by the usb host 101, so as to prevent the sound break caused by the overflow or underload of the fifo buffer 112.
Please refer to fig. 6, which is a flowchart illustrating an audio data synchronization method according to an embodiment of the present invention. As shown in fig. 6, this embodiment includes the following steps 601 to 607, and can be applied to the audio data synchronization apparatus shown in fig. 1.
In step 601, the control unit 114 waits for an interrupt signal generated by the counter 115. In step 602, the size of the data stored in the FIFO 112 is read. In step 603, it is determined whether the amount of data stored in the fifo 112 is less than the minimum data threshold 401, if so, the process proceeds to step 604 to decrease the frequency of the clock signal 1171, and if not, the process proceeds to the next step. In step 605, it is determined whether the amount of data stored in the fifo 112 is greater than the maximum data amount threshold 301, if so, the process proceeds to step 606, the frequency of the clock signal 1171 is increased, and if not, the process proceeds to the next step; in step 607, the frequency of the clock signal 1171 is not changed.
In summary, the present invention provides a dynamic clock adjustment technique for synchronizing the audio packet generation speed and the audio packet encoding/decoding speed, detecting whether the data amount in the fifo buffer is smaller than the minimum data amount threshold or larger than the maximum data amount threshold every second, and adjusting the audio packet generation speed through I2The S interface transmits the frequency of the clock signal of the audio codec, thereby dynamically adjusting the codec speed of the audio codec in time.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (10)
1. An audio data synchronization apparatus, comprising:
a USB host for transmitting an audio packet;
a processor, comprising:
a USB module for receiving the audio packet;
a first-in first-out buffer for storing the audio packet;
a clock generator for generating a clock signal;
a control unit for storing a maximum data amount threshold and a minimum data amount threshold, and determining whether the data amount stored in the fifo buffer is greater than the maximum data amount threshold or less than the minimum data amount threshold, when the control unit determines that the data amount stored in the fifo buffer is greater than the maximum data amount threshold, the control unit controlling the clock generator to increase the frequency of the clock signal, and when the control unit determines that the data amount stored in the fifo buffer is less than the minimum data amount threshold, the control unit controlling the clock generator to decrease the frequency of the clock signal; and
a data transmission interface for outputting the audio packet from the FIFO buffer and outputting the clock signal; and
and the audio codec is used for receiving the audio packet and the clock signal through the data transmission interface and processing the audio packet according to the clock signal so as to output audio.
2. The apparatus of claim 1, wherein the data transmission interface is an audio interface between ICs for transmitting the audio packet to the audio codec.
3. The apparatus of claim 1, wherein the processor comprises a counter, and when the counter reaches a predetermined value, the counter generates a trigger signal to the control unit to trigger the control unit to determine the status of the amount of data stored in the FIFO buffer, so that the control unit repeatedly determines the status of the amount of data stored in the FIFO buffer.
4. The audio data synchronization apparatus of claim 3, wherein the counter counts based on the clock signal.
5. The audio data synchronization apparatus of claim 1, wherein the clock signal is independent of the USB host.
6. A method for synchronizing audio data, comprising:
receiving an audio packet from a USB host;
storing the audio packet in a first-in first-out buffer;
setting a maximum data amount threshold value and a minimum data amount threshold value of the first-in first-out buffer;
generating a clock signal;
outputting the audio packet and the clock signal from the FIFO buffer to an audio codec through a data transmission interface;
processing the audio packet by using the audio codec according to the clock signal to output audio;
when the data amount stored in the first-in first-out buffer is judged to be larger than the maximum data amount critical value, the frequency of the clock signal is increased; and
when the data amount stored in the FIFO buffer is judged to be smaller than the minimum data amount threshold value, the frequency of the clock signal is reduced.
7. The audio data synchronization method of claim 6, wherein the data transmission interface is I2And the S interface is used for transmitting the audio packet to the audio codec.
8. The method of claim 6, further comprising counting with a counter, wherein the counter generates a trigger signal to trigger the determining of the status of the amount of data stored in the FIFO buffer when the counter reaches a predetermined value, thereby repeatedly determining the status of the amount of data stored in the FIFO buffer.
9. The audio data synchronization method of claim 8, wherein the counter counts based on the clock signal.
10. The method of claim 6, wherein the USB host operates independently of the clock signal.
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| TW108133694 | 2019-09-18 | ||
| TW108133694A TWI722574B (en) | 2019-09-18 | 2019-09-18 | Audio and data synchronization device and method thereof |
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| CN104125164A (en) * | 2013-04-26 | 2014-10-29 | 联发科技股份有限公司 | Active output buffer controller and related method |
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| CN106407157A (en) * | 2015-07-31 | 2017-02-15 | 盛微先进科技股份有限公司 | Universal serial bus audio frequency locking device and method |
| TW201807591A (en) * | 2016-08-29 | 2018-03-01 | 松翰科技股份有限公司 | Device and method for adjusting USB clock frequency |
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