CN116204476A - Data processing system, buffer circuit and operation method of buffer circuit - Google Patents

Data processing system, buffer circuit and operation method of buffer circuit Download PDF

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Publication number
CN116204476A
CN116204476A CN202111441346.1A CN202111441346A CN116204476A CN 116204476 A CN116204476 A CN 116204476A CN 202111441346 A CN202111441346 A CN 202111441346A CN 116204476 A CN116204476 A CN 116204476A
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data
control signal
circuit
clock signal
control
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杨尚原
吴柏贤
陈焕文
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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Priority to CN202111441346.1A priority Critical patent/CN116204476A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

A buffer circuit includes a memory circuit and a control circuit. The memory circuit is used for storing input data from the data transmission device and transmitting output data to the data receiving device. The control circuit is used for calculating the residual data quantity of the memory circuit and generating a control signal according to the residual data quantity. The remaining data amount represents the amount of data to be transferred in the memory circuit. If the control signal is used for controlling the data transmission device to generate a writing clock signal, the control circuit reduces the frequency of the writing clock signal through the control signal when the residual data quantity rises. If the control signal is used for controlling the data receiving device to generate the reading clock signal, the control circuit reduces the frequency of the reading clock signal through the control signal when the residual data quantity is reduced.

Description

Data processing system, buffer circuit and operation method of buffer circuit
Technical Field
The present disclosure relates to a data processing system, a buffer circuit, and a method for operating the buffer circuit, and more particularly, to a data processing system, a buffer circuit, and a method for operating the buffer circuit that prevent power surges.
Background
As consumer electronics become more complex in functionality, it is a common design approach for multiple circuit blocks in digital circuitry to use multiple frequency signals, i.e., the multiple circuit blocks may belong to different clock domains (clock domains). Data signals are susceptible to metastable states (meta-stable states) when transmitted between different clock domains, which may cause the data signal to change to an erroneous level during transmission. To overcome this problem, a buffer circuit may be provided on the data transfer path across the clock domain for temporarily storing the data signal to ensure that the data receiving end can sample a stable data signal. Generally, the buffer circuit selectively interrupts the data transmission operation according to the remaining memory space. However, abrupt interruption of circuit operation can cause a drastic change in power and can easily cause a power surge (power ripple).
Disclosure of Invention
The present disclosure provides a buffer circuit including a memory circuit and a control circuit. The memory circuit is used for storing input data from the data transmission device and transmitting output data to the data receiving device. The control circuit is used for calculating the residual data quantity of the memory circuit and generating a control signal according to the residual data quantity. The remaining data amount represents the amount of data to be transferred in the memory circuit. If the control signal is used for controlling the data transmission device to generate a writing clock signal, the control circuit reduces the frequency of the writing clock signal through the control signal when the residual data quantity rises. If the control signal is used for controlling the data receiving device to generate the reading clock signal, the control circuit reduces the frequency of the writing clock signal through the control signal when the residual data quantity is reduced.
The present disclosure provides a method of operating a buffer circuit, comprising the following steps: storing input data from the data transfer device to the memory circuit to transfer output data from the memory circuit to the data receiving device; calculating a remaining data amount of the memory circuit, wherein the remaining data amount represents an amount of data to be transferred in the memory circuit; and adjusting the working period of the control signal according to the residual data quantity. Generating the control signal according to the remaining data amount includes the following steps: if the control signal is used for controlling the data transmission device to generate a writing clock signal, when the residual data quantity rises, the frequency of the writing clock signal is reduced by the control signal; and if the control signal is used for controlling the data receiving device to generate the reading clock signal, reducing the frequency of the reading clock signal through the control signal when the residual data quantity is reduced.
The present disclosure provides a data processing system including a data transfer device, a data receiving device, a memory circuit, and a control circuit. The data transfer device is used for generating a write clock signal. The data receiving device is used for generating a reading clock signal. The memory circuit is used for storing input data from the data transmission device and transmitting output data to the data receiving device. The control circuit is used for calculating the residual data quantity of the memory circuit and generating a control signal according to the residual data quantity. The remaining data amount represents the amount of data to be transferred in the memory circuit. If the control signal is used for controlling the data transmission device to generate a writing clock signal, the control circuit reduces the frequency of the writing clock signal through the control signal when the residual data quantity rises. If the control signal is used for controlling the data receiving device to generate the reading clock signal, the control circuit reduces the frequency of the reading clock signal through the control signal when the residual data quantity is reduced.
One of the advantages of the buffer circuit, the operation method of the buffer circuit and the data processing system is that the power surge can be prevented.
Drawings
FIG. 1 is a simplified functional block diagram of a data processing system according to one embodiment of the present disclosure.
FIG. 2 is a diagram illustrating the remaining data amount of the buffer circuit and the frequency of the write clock signal according to an embodiment of the present disclosure.
FIG. 3 is a timing diagram of a data processing system according to one embodiment of the present disclosure.
FIG. 4 is a timing diagram of a data processing system according to another embodiment of the present disclosure.
FIG. 5 is a simplified functional block diagram of a data processing system according to one embodiment of the present disclosure.
FIG. 6 is a diagram illustrating the remaining data amount of the buffer circuit and the frequency of the read clock signal according to an embodiment of the disclosure.
FIG. 7 is a timing diagram of a data processing system according to one embodiment of the present disclosure.
FIG. 8 is a timing diagram of a data processing system according to another embodiment of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described below with reference to the accompanying drawings. In the drawings, like reference numerals designate identical or similar components or process flows.
FIG. 1 is a simplified functional block diagram of a data processing system 100 according to one embodiment of the present disclosure. Referring to fig. 1, a data processing system 100 includes a data transmitting device 110, a data receiving device 120, and a buffer circuit 130. The data transfer means 110 and the data receiving means 120 are located in different clock domains and thus the data transfer between the two is not synchronized. The buffer circuit 130 is coupled between the data transmitting device 110 and the data receiving device 120, and is used for buffering the data transmitted from the data transmitting device 110 to the data receiving device 120, so as to realize the data transmission across clock domains. In some embodiments, the data transfer device 110 and the data receiving device 120 may be located in the same clock domain and both perform asynchronous data transfer.
The data transfer device 110 includes an arithmetic circuit 112 and a clock generation circuit 114. For brevity, the remaining components and connections in the data transfer device 110 are not shown in FIG. 1. The operation circuit 112 is configured to transmit the input data Din and the write enable signal w_en to the buffer circuit 130, wherein the write enable signal w_en is configured to control the buffer circuit 130 to perform a write operation to store the input data Din. The clock generation circuit 114 is used for generating a write clock signal w_clk, wherein the write clock signal w_clk is used for controlling operations of other circuit blocks in the data transfer device 110. In some embodiments, when the write clock signal w_clk stops oscillating, other circuit blocks in the data transfer device 110 other than the clock generation circuit 114 are controlled to stop operating. For example, the data traffic of the operation circuit 112 transmitting the input data Din may be positively correlated with the frequency of the write clock signal w_clk, and when the write clock signal w_clk stops oscillating, the operation circuit 112 may stop transmitting the input data Din. The data traffic of the operation circuit 112 represents the average magnitude of the input data Din transmitted by the operation circuit 112 per unit time, and for convenience of description, the data traffic of the operation circuit 112 is also referred to as the data traffic of the data transmission device 110 in some paragraphs of the present disclosure. In some embodiments, the operation circuit 112 may be implemented by a Direct Memory Access (DMA) controller, or a combination of a DMA controller and a video processing chip to provide video data as input data Din to the buffer circuit 130, but the disclosure is not limited thereto.
The data receiving apparatus 120 includes an arithmetic circuit 122 and a clock generating circuit 124. For brevity, the remaining components and connections in the data receiving apparatus 120 are not shown in fig. 1. The operation circuit 122 is configured to receive the output data Dout from the buffer circuit 130 and provide a read enable signal r_en to the buffer circuit 130, wherein the read enable signal r_en is configured to control the buffer circuit 130 to perform a read operation to provide the output data Dout to the operation circuit 122. The clock generation circuit 124 is configured to generate a read clock signal r_clk, where the read clock signal r_clk is used to control operations of other circuit blocks in the data receiving device 120. In some embodiments, when the read clock signal r_clk stops oscillating, other circuit blocks in the data receiving device 120 except the clock generating circuit 124 are controlled to stop operating. For example, the data traffic of the output data Dout received by the operation circuit 122 may be a frequency positively correlated to the read clock signal r_clk, and the operation circuit 122 may stop receiving the output data Dout when the read clock signal r_clk stops oscillating. The data traffic of the operation circuit 122 represents the average magnitude of the output data Dout received by the operation circuit 122 in a unit time, and for convenience of description, the data traffic of the operation circuit 122 is also referred to as the data traffic of the data receiving device 120 in some paragraphs of the present disclosure. In some embodiments, the operation circuit 122 may be implemented by a Timing Controller (TCON) for controlling a display panel (not shown) to display a corresponding frame according to the output data Dout, but the disclosure is not limited thereto.
The buffer circuit 130 includes a memory circuit 132 and a control circuit 134. The memory circuit 132 is used for performing a write operation according to the write enable signal w_en and the write clock signal w_clk, and for performing a read operation according to the read enable signal r_en and the read clock signal r_clk. In some embodiments, memory circuit 132 may be implemented as a first-in-first-out (FIFO) memory circuit. The control circuit 134 is configured to generate the control signal w_gen according to a remaining data amount of the memory circuit 132, wherein the remaining data amount of the memory circuit 132 refers to an amount of data temporarily stored in the memory circuit 132 and to be transmitted to the data receiving device 120. In some embodiments, the control circuit 134 may receive the write pointer w_ptr and the read pointer r_ptr of the memory circuit 132 and subtract the read pointer r_ptr from the write pointer w_ptr to obtain the amount of data remaining. The control signal w_gen is used to control the clock generation circuit 114 to generate the write clock signal w_clk having a specified frequency. As described above, the data traffic of the operation circuit 122 is positively related to the frequency of the write clock signal w_clk, and the control circuit 134 can control the data traffic of the operation circuit 122 by controlling the frequency of the write clock signal w_clk. In some embodiments, the control signal w_gen is used to disable (disable) the write clock signal w_clk, i.e., the control signal w_gen is used to stop the data transfer device 110 from generating the write clock signal w_clk.
Fig. 2 is a diagram illustrating the remaining data amount of the buffer circuit 130 and the frequency of the write clock signal w_clk according to an embodiment of the disclosure. Please refer to fig. 1 and fig. 2 simultaneously. The control circuit 134 is configured to compare a plurality of thresholds THa to THc having different magnitudes from those of fig. 2 with respect to the remaining data amount. In some embodiments, the threshold values THa-THc are 50%, 70% and 90% of the effective capacity of the memory circuit 132, respectively, but the disclosure is not limited thereto. The control circuit 134 adjusts the waveform of the control signal w_gen (e.g. adjusts the pulse width and/or the duty cycle) according to the comparison result, so that the frequency of the write clock signal w_clk varies with the remaining data amount. For example, when the remaining data amount of the memory circuit 132 rises from below the threshold THa to reach the threshold THa, the control circuit 134 switches the write clock signal w_clk from the frequency Fa to the frequency Fb; when the remaining data amount of the memory circuit 132 falls below the threshold value THa from between the threshold values THa and THb, the control circuit 134 switches the write clock signal w_clk from the frequency Fb to the frequency Fa, and so on. The correspondence between the waveform of the control signal w_gen and the frequency of the write clock signal w_clk will be described in detail with reference to fig. 3 and 4.
As can be seen from FIG. 2, the control circuit 134 can make the frequency of the write clock signal w_clk substantially inversely related to the remaining data amount of the memory circuit 132. In some embodiments, the frequency Fa may be the original frequency at which the write clock signal w_clk is not reduced by any means; frequency Fb may be 25% of frequency Fa; the frequency Fc may be 12.5% of the frequency Fa; the frequency Fd may be 0% of the frequency Fa, which represents that the write clock signal w_clk stops oscillating and completely stops the transmission of the input data Din, but the disclosure is not limited thereto. By adaptively adjusting the frequency of the write clock signal w_clk, even if the data transmission of the data transmitting apparatus 110 and the data receiving apparatus 120 is not synchronized (e.g., the data transmitting apparatus 110 is first transmitting the input data Din but the data receiving apparatus 120 has not yet started to receive the output data Dout, or the data traffic of the data transmitting apparatus 110 is not limited by any means is larger than that of the data receiving apparatus 120), the storage space of the memory circuit 132 is not completely exhausted, so as to ensure that the data transmission between the data transmitting apparatus 110 and the data receiving apparatus 120 is not lost. How the frequency of the write clock signal w_clk is adaptively adjusted by the data processing system 100 will be illustrated with reference to fig. 3 and 4.
FIG. 3 is a timing diagram of data processing system 100 according to one embodiment of the present disclosure. FIG. 4 is a timing diagram of data processing system 100 according to another embodiment of the present disclosure. In fig. 3 and 4, the lower half is an enlarged timing chart of the upper half outlined with a dotted line. The timing of fig. 4 follows the timing of fig. 3. Referring to fig. 1 to 3, the write enable signal w_en of fig. 3 has a logic high level and the read enable signal r_en has a logic low level, which indicates that the data transmitting device 110 is transmitting the input data Din, and the data receiving device 120 has not yet started to receive the output data Dout. Accordingly, the amount of data remaining in the memory circuit 132 will gradually rise in the embodiment of FIG. 3.
When the remaining data amount is below the threshold THa, the memory circuit 132 has a lot of room, and the control circuit 134 can set the write clock signal w_clk to the frequency Fa, i.e. the original frequency of the write clock signal w_clk. To achieve this configuration, the control circuit 134 keeps the control signal w_gen at a logic low level, i.e., the control signal w_gen has a duty cycle (duty cycle) of 0%. The control signal w_gen with a logic low level allows the clock generation circuit 114 to generate the write clock signal w_clk, and the control signal w_gen with a logic high level stops the clock generation circuit 114 from generating the write clock signal w_clk (i.e. stops the write clock signal w_clk from oscillating). The arithmetic circuit 122 is controlled by the write clock signal w_clk at the frequency Fa, and transmits the input data Din at a data traffic (hereinafter referred to as an original data traffic) which is not degraded by any means.
Then, if the remaining data amount rises to reach the threshold THa, the control circuit 134 may set the write clock signal w_clk to the frequency Fb to reduce the data throughput of the operation circuit 122. To achieve this, the control circuit 134 sets the control signal w_gen to have a periodic pulse, i.e., periodically disables the clock generation circuit 114 from generating the write clock signal w_clk to reduce the frequency of the write clock signal w_clk. Specifically, the frequency of the control signal w_gen may be 25% of the frequency Fa, and the logic high level and the logic low level of the control signal w_gen respectively occupy 75% and 25% of one period, i.e. the control signal w_gen has 75% of the duty cycle. As a result, the data traffic of the operation circuit 112 is reduced to 25% of the original data traffic.
If the remaining data amount continues to rise to the threshold THb, the control circuit 134 may further increase the pulse width of the control signal w_gen to set the write clock signal w_clk to the frequency Fc, thereby further reducing the data throughput of the operation circuit 112. At this time, the frequency of the control signal w_gen may be 12.5% of the frequency Fa, and the logic high level and the logic low level of the control signal w_gen respectively occupy 87.5% and 12.5% of a period, i.e. the control signal w_gen has a duty cycle of 87.5%. As a result, the data traffic of the operation circuit 112 is reduced to 12.5% of the original data traffic. If the remaining data amount of the memory circuit 132 further rises to reach the maximum threshold THc, the control circuit 134 can maintain the control signal w_gen at the logic high level, i.e. the control signal w_gen has a duty cycle of 100%. At this time, the write clock w_clk has the frequency Fd (i.e. stops oscillating), and the operation circuit 112 stops transmitting the write data Din completely.
As can be seen from the above, when the remaining data amount of the memory circuit 132 increases, the control circuit 134 increases the pulse width and the duty cycle of the control signal w_gen multiple times to decrease the frequency of the write clock signal w_clk multiple times, thereby decreasing the data traffic of the operation circuit 112 multiple times.
Please refer to fig. 1, 2 and 4. In the embodiment of fig. 4, the read enable signal r_en is switched from a logic low level to a logic high level, which represents that the data receiving apparatus 120 starts to receive the output data Dout from the memory circuit 132, so that the remaining data amount of the memory circuit 132 gradually decreases. The control circuit 134 can sequentially decrease the pulse width and the duty cycle of the control signal w_gen when the remaining data amount of the memory circuit 132 decreases, so as to sequentially increase the frequency of the write clock signal w_clk, thereby gradually increasing the data throughput of the operation circuit 112. Those skilled in the art can understand how to adjust the waveform of the control signal w_gen to increase the frequency of the write clock signal w_clk according to the description of fig. 3, and the description is not repeated here for brevity.
FIG. 5 is a simplified functional block diagram of a data processing system 500 according to one embodiment of the present disclosure. The data processing system 500 comprises a data transmitting device 510, a data receiving device 520 and a buffer circuit 530. Structurally, the data transfer device 510 includes an arithmetic circuit 512 and a clock generation circuit 514; the data receiving apparatus 520 includes an arithmetic circuit 522 and a clock generating circuit 524; buffer circuit 530 includes memory circuit 532 and control circuit 534. In some embodiments, the data transfer device 510 may be implemented by various suitable real-time computing (real-time computing) semiconductor silicon intellectual property (silicon intellectual property), and the data receiving device 520 may be implemented by a DMA controller. As shown in FIG. 5, the connection between functional blocks of data processing system 500 is similar to data processing system 100 of FIG. 1 and is not repeated here for brevity. In addition, data processing system 500 also is similar in operation to data processing system 100 of FIG. 1, and therefore only differences are described in detail below.
In the present embodiment, the data transmitting device 510 and the data receiving device 520 are located in different clock domains, so that data transmission between the two devices is not synchronized. The aforementioned data transmission dyssynchrony may be that the data traffic of the data receiving device 520, which is not limited by any means, is greater than the data traffic of the data transmitting device 510. In some embodiments, the data transfer device 510 and the data receiving device 520 are located in the same clock domain and the data transfer between the two is not synchronized. The control circuit 534 of the buffer circuit 530 is configured to generate a control signal r_gen, where the control signal r_gen is configured to control the clock generation circuit 524 to generate the read clock signal r_clk having a specified frequency. By controlling the frequency of the read clock signal r_clk, the control circuit 534 can control the data traffic of the arithmetic circuit 522 of the data receiving device 520. In some embodiments, the control signal r_gen is used to disable the read clock signal r_clk, i.e., the control signal r_gen is used to stop the data receiving device 520 from generating the read clock signal r_clk.
Fig. 6 is a diagram illustrating the remaining data amount of the buffer circuit 530 and the frequency of the read clock signal r_clk according to an embodiment of the disclosure. Please refer to fig. 5 and fig. 6 simultaneously. The control circuit 134 compares the remaining data amount with a plurality of thresholds THd to THf having different magnitudes from those in fig. 5. In some embodiments, the threshold values THd-THf are 50%, 30% and 10% of the effective capacity of the memory circuit 132, respectively, but the disclosure is not limited thereto. The control circuit 534 adjusts the waveform of the control signal r_gen (e.g. adjusts the pulse width and/or the duty cycle) according to the comparison result, so that the frequency of the read clock signal r_clk varies with the amount of the remaining data.
As shown in fig. 6, the control circuit 534 can make the frequency of the read clock signal r_clk substantially positively correlated with the remaining data amount, i.e. as the remaining data amount gradually decreases, the control circuit 534 can set the frequency of the read clock signal r_clk to the frequencies Fe to Fh sequentially from high to low. In some embodiments, the frequency Fe may be the original frequency at which the read clock signal r_clk is not reduced by any means; the frequency Ff may be 25% of the frequency Fe; the frequency Fg may be 12.5% of the frequency Fe; the frequency Fh may be 0% of the frequency Fe, which represents stopping the oscillation of the read clock signal r_clk to completely stop the transmission of the output data Dout, but the disclosure is not limited thereto. By adaptively adjusting the frequency of the read clock signal r_clk, the remaining data amount of the memory circuit 132 will not return to zero even if the data transfer of the data transfer device 110 and the data receiving device 120 are not synchronized, to ensure that the data receiving device 120 does not receive erroneous output data Dout. How the data processing system 500 adjusts the frequency of the read clock signal r_clk adaptively will be illustrated below in conjunction with fig. 7 and 8.
FIG. 7 is a timing diagram of a data processing system 500 according to one embodiment of the present disclosure. FIG. 8 is a timing diagram of a data processing system 500 according to another embodiment of the present disclosure. In fig. 7 and 8, the lower half is an enlarged timing chart of the upper half outlined with a dotted line. The timing of FIG. 8 is subsequent to the timing of FIG. 7. Referring to fig. 5 to 7, the write enable signal w_en and the read enable signal r_en of fig. 7 have logic high levels, which indicates that the data transmitting device 110 is transmitting the input data Din and the data receiving device 120 is receiving the output data Dout. However, the original data traffic of the data receiving device 120 is not reduced by any means greater than the data traffic of the data transmitting device 110, so the remaining data amount of the memory circuit 132 will gradually decrease in the embodiment of fig. 7.
When the remaining data amount is above the threshold THd, the control circuit 134 may set the write clock signal w_clk to the frequency Fa, i.e., the original frequency at which the read clock signal r_clk is unrestricted. To achieve this configuration, the control circuit 534 keeps the control signal r_gen at a logic low level, i.e., the control signal r_gen has a duty cycle of 0%. The control signal r_gen with a logic low level allows the clock generating circuit 524 to generate the read clock signal r_clk, and the control signal r_gen with a logic high level stops the clock generating circuit 524 from generating the read clock signal r_clk (i.e. stops the read clock signal r_clk from oscillating). The operation circuit 522 receives the output data Dout with an unrestricted data traffic (hereinafter referred to as an original data traffic) under the control of the read clock signal r_clk with the frequency Fa.
Then, if the remaining data amount decreases to reach the threshold THd, the control circuit 534 may set the read clock signal r_clk to the frequency Ff to decrease the data traffic of the operation circuit 522. To achieve this, the control circuit 534 sets the control signal r_gen to have periodic pulses, i.e., periodically disables the clock generation circuit 524 from generating the read clock signal r_clk to decrease the frequency of the read clock signal r_clk. Specifically, the frequency of the control signal r_gen may be 25% of the frequency Fe, and the logic high level and the logic low level of the control signal r_gen respectively occupy 75% and 25% of a period, i.e. the control signal w_gen has a duty cycle of 75%. As a result, the data traffic of the arithmetic circuit 522 is reduced to 25% of the original data traffic.
If the remaining data amount continues to decrease to reach the threshold THe, the control circuit 534 can further increase the pulse width of the control signal r_gen to set the read clock signal r_clk to the frequency Fg, thereby further reducing the data throughput of the operation circuit 522. At this time, the frequency of the control signal r_gen may be 12.5% of the frequency Fe, and the logic high level and the logic low level of the control signal r_gen respectively occupy 87.5% and 12.5% of a period, i.e. the control signal r_gen has a duty cycle of 87.5%. As a result, the data traffic of the arithmetic circuit 522 is reduced to 12.5% of the original data traffic. If the remaining data amount of the memory circuit 532 further decreases to reach the minimum threshold THf, the control circuit 134 can maintain the control signal r_gen at the logic high level, i.e., the control signal r_gen has a duty cycle of 100%. At this time, the read clock signal r_clk has the frequency Fh (i.e. stops oscillating), and the operation circuit 522 stops transmitting the output data Dout completely.
As can be seen from the above, when the remaining data amount of the memory circuit 532 decreases, the control circuit 534 increases the pulse width and the duty cycle of the control signal r_gen multiple times to decrease the frequency of the read clock signal r_clk multiple times, and further decreases the data throughput of the operation circuit 522 multiple times.
Please refer to fig. 5, 6 and 8. The transfer of the output data Dout is stopped at the beginning of the timing of fig. 8, so that the remaining data amount of the memory circuit 532 gradually increases. The control circuit 534 can sequentially decrease the pulse width and the duty cycle of the control signal r_gen when the remaining data amount of the memory circuit 532 increases, so as to sequentially increase the frequency of the read clock signal r_clk, and gradually increase the data throughput of the operation circuit 522. Those skilled in the art can understand how to adjust the waveform of the control signal r_gen to increase the frequency of the read clock signal r_clk according to the description of fig. 7, and the description is not repeated here for brevity.
In the above embodiments, by progressively changing the frequencies of the write clock signal w_clk and the read clock signal r_clk, the power consumption of the data transmission device 110 of fig. 1 and the data reception device 520 of fig. 5 is progressively changed, so that the power burst in the data transmission device 110 of fig. 1 and the data reception device 520 of fig. 5 can be prevented. In other words, the above embodiments can improve the reliability of the circuit. It should be noted that the number and value of the threshold values THa to THc and the threshold values THd to THf, and the number and value of the frequencies Fa to Fd and the frequencies Fe to Fh are only exemplary embodiments, and may be adjusted according to actual design requirements. For example, increasing the threshold number helps to further reduce power fluctuations of the circuit, while decreasing the threshold number may avoid the power of the circuit being frequently switched to improve stability. For another example, the data throughput of the operation circuit 112 and the effective capacity of the memory circuit 132 may be considered when designing the frequency of the write clock signal w_clk at each stage, so that the write clock signal w_clk after the frequency is reduced effectively slows down the rising speed of the remaining data amount of the memory circuit 132. For another example, the data throughput of the arithmetic circuit 522 and the effective capacity of the memory circuit 532 may be considered when designing the frequency of the read clock signal r_clk at each stage, so that the read clock signal r_clk after the frequency is reduced effectively slows down the falling speed of the remaining data amount of the memory circuit 532.
Certain terms are used throughout the description and claims to refer to particular components. However, those of ordinary skill in the art will appreciate that the same components may be referred to by different terms. The description and claims are not intended to identify differences in names, but rather are intended to identify differences in functionality of the components. The terms "comprising" and "comprises" as used in the specification and claims are to be construed as open-ended terms, including, but not limited to. In addition, "coupled" herein includes any direct or indirect connection. Accordingly, if a first element couples to a second element, that connection may be through an electrical or wireless transmission, an optical transmission, etc., directly to the second element, or through other elements or connections indirectly to the second element.
As used herein, the term "and/or" includes any combination of one or more of the listed items. In addition, any singular term shall include the plural meaning unless the specification expressly states otherwise.
The foregoing is only illustrative of the preferred embodiments of the present disclosure, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Reference numerals illustrate:
100. 500: data processing system
110. 510: data transmission device
112. 512: arithmetic circuit
114. 514: clock generating circuit
120. 520: data receiving device
122. 522: arithmetic circuit
124. 524: clock generating circuit
130. 530: buffer circuit
132. 532: memory circuit
134. 534: control circuit
Din: input data
Dout: output data
w_en: write enable signal
r_en: read enable signal
w_clk: writing clock signals
r_clk: reading clock signals
w_ptr: write pointer
r_ptr: reading pointer
w_gen, r_gen: control signal
THa to THc, THd to THf: threshold value
Fa to Fd, fe to Fh: frequency of

Claims (10)

1. A buffer circuit, comprising:
a memory circuit for storing input data from the data transfer device and for transferring output data to the data receiving device; and
a control circuit for calculating a remaining data amount of the memory circuit, wherein the remaining data amount represents an amount of data to be transferred in the memory circuit,
wherein if the control signal is used for controlling the data transmission device to generate a write clock signal, the control circuit reduces the frequency of the write clock signal through the control signal when the residual data quantity rises,
if the control signal is used for controlling the data receiving device to generate a read clock signal, the control circuit reduces the frequency of the read clock signal through the control signal when the residual data quantity is reduced.
2. The buffer circuit of claim 1, wherein if the control signal is used to stop the data transfer device from generating the write clock signal, the control circuit increases the duty cycle of the control signal when the remaining data amount increases,
if the control signal is used for stopping the data receiving device from generating the read clock signal, the control circuit increases the working period of the control signal when the residual data quantity is reduced.
3. The buffer circuit of claim 1, wherein the memory circuit performs a write operation to store the input data according to the write clock signal of the data transfer device, and the memory circuit performs a read operation to transfer the output data to the data receiving device according to the read clock signal of the data receiving device.
4. The buffer circuit of claim 1, wherein if the control signal is used to stop the data transfer device from generating the write clock signal, the control circuit is used to compare the remaining data amount with a plurality of first thresholds of different sizes, the control circuit increases the pulse width of the control signal when the remaining data amount rises to one of the plurality of first thresholds, the control circuit sets the duty cycle of the control signal to 100% when the remaining data amount rises to the maximum one of the plurality of first thresholds,
if the control signal is used for stopping the data receiving device from generating the read clock signal, the control circuit is used for comparing the residual data quantity with a plurality of second thresholds with different sizes, the control circuit increases the pulse width of the control signal when the residual data quantity is reduced to one of the second thresholds, and sets the working period of the control signal to 100% when the residual data quantity is reduced to the smallest of the second thresholds.
5. The buffer circuit of claim 1, wherein the data transmitting means and the data receiving means are located in different clock domains.
6. The buffer circuit of claim 1, wherein the data transmitting means and the data receiving means are located in the same clock domain, and the data transmitting means and the data receiving means perform asynchronous data transmission.
7. The buffer circuit of claim 1, wherein the memory circuit has a write pointer and a read pointer, the control circuit subtracting the read pointer from the write pointer to obtain the remaining data amount.
8. A method of operation of a snubber circuit, comprising:
storing input data from the data transfer device to the memory circuit to transfer output data from the memory circuit to the data receiving device;
calculating a remaining data amount of the memory circuit, wherein the remaining data amount represents an amount of data to be transferred in the memory circuit; and
generating a control signal according to the remaining data amount, comprising:
if the control signal is used for controlling the data transmission device to generate a writing clock signal, when the residual data quantity rises, the frequency of the writing clock signal is reduced by the control signal; and
if the control signal is used for controlling the data receiving device to generate a read clock signal, the frequency of the read clock signal is reduced by the control signal when the residual data quantity is reduced.
9. The method of claim 8, wherein generating the control signal based on the remaining data amount further comprises:
adjusting the working period of the control signal according to the residual data quantity;
if the control signal is used for stopping the data transmission device from generating the writing clock signal, increasing the working period of the control signal when the residual data quantity rises; and
if the control signal is used for stopping the data receiving device from generating the read clock signal, the working period of the control signal is increased when the residual data quantity is reduced.
10. A data processing system, comprising:
data transfer means for generating a write clock signal;
data receiving means for generating a read clock signal;
a memory circuit for storing input data from the data transfer device and for transferring output data to the data receiving device; and
a control circuit for calculating a remaining data amount of the memory circuit, wherein the remaining data amount represents an amount of data to be transferred in the memory circuit,
wherein if the control signal is used to control the data transfer device to generate the write clock signal, the control circuit reduces the frequency of the write clock signal by the control signal when the remaining data amount rises,
if the control signal is used for controlling the data receiving device to generate the reading clock signal, the control circuit reduces the frequency of the reading clock signal through the control signal when the residual data quantity is reduced.
CN202111441346.1A 2021-11-30 2021-11-30 Data processing system, buffer circuit and operation method of buffer circuit Pending CN116204476A (en)

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Application Number Priority Date Filing Date Title
CN202111441346.1A CN116204476A (en) 2021-11-30 2021-11-30 Data processing system, buffer circuit and operation method of buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111441346.1A CN116204476A (en) 2021-11-30 2021-11-30 Data processing system, buffer circuit and operation method of buffer circuit

Publications (1)

Publication Number Publication Date
CN116204476A true CN116204476A (en) 2023-06-02

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