TWI722574B - Audio and data synchronization device and method thereof - Google Patents

Abstract

The present invention discloses an audio data synchronization device, which includes a universal serial bus (USB) host, a processor, and an audio codec. The processor includes a universal serial bus module to receive audio packets from the USB host; the first-in first-out (FIFO) buffer stores the audio packets; the clock generator generates the clock signal; the control unit stores the maximum data volume threshold and the minimum Data volume threshold, and determine whether the data volume stored in the FIFO buffer is greater than the maximum data volume threshold or less than the minimum data volume threshold, so as to increase or decrease the frequency of the clock signal; and a data transmission interface. The audio codec receives audio packets and clock signals through the data transmission interface, and processes the audio packets according to the clock signals to output audio.

Description

Audio data synchronization device and method

The present invention relates to an audio data processing technology, in particular to an audio data synchronization device and method.

In many audio applications, the use of universal serial bus (USB) for audio playback has gradually become the mainstream. Generally speaking, audio processing requires clock synchronization within the error range of 2500ppm, so every 2500ppm may produce a time error, and the accumulated time error will cause the sound to break the sound.

Since the universal serial bus protocol is an asynchronous design, the clock sources of the universal serial bus host used to generate audio packets and the audio codec used to encode and decode audio packets are inconsistent, so the buffer for storing audio packets The device is prone to buffer overflow or underrun problems, resulting in sound breaking.

One purpose of the present invention is to provide an audio data synchronization device and method, which uses the clock generator of the processor to generate a clock signal and provides it to the counter and the data transmission interface at the same time, and uses the counter to monitor the first-in-first-out buffer for storing audio packets To adjust the frequency of the clock signal by changing the amount of data stored to prevent the sound breakage caused by the overflow or underload of the first-in-first-out buffer.

To achieve the above objective, the present invention provides an audio data synchronization device, which includes a universal serial bus host, a processor, and an audio codec. The universal serial bus host is used to transmit an audio packet. The processor includes a universal serial bus (USB) module, a first-in-first-out (FIFO) buffer, a clock generator, a control unit, and a data transmission interface. The universal serial bus module is used to receive audio packets. The first-in first-out buffer is used to store audio packets. The clock generator generates a clock signal. The control unit stores a maximum data volume threshold and a minimum data volume threshold, and determines whether the data volume stored in the first-in first-out buffer is greater than the maximum data volume threshold or less than the minimum data volume threshold. When the control unit determines that the amount of data stored in the first-in-first-out buffer is greater than the maximum data amount threshold, the control unit controls the clock generator to increase the frequency of the clock signal. When the control unit determines the amount of data stored in the first-in-first-out buffer When it is less than the threshold of the minimum data amount, the control unit controls the clock generator to reduce the frequency of the clock signal. The data transmission interface outputs audio packets from the first-in first-out buffer and outputs the clock signal. The audio codec receives audio packets and clock signals through the data transmission interface, and processes the audio packets according to the clock signals to output audio.

According to an embodiment of the present invention, the aforementioned data transmission interface is an Inter-IC Sound (I ² S) interface for transmitting audio packets to the audio codec.

According to an embodiment of the present invention, the processor includes a counter, and when the counter count reaches a preset value, the counter generates a trigger signal to the control unit to trigger the control unit to determine the amount of data stored in the first-in-first-out buffer The status, thereby allowing the control unit to repeatedly determine the status of the amount of data stored in the first-in-first-out buffer.

According to an embodiment of the present invention, the counter counts based on the clock signal.

According to an embodiment of the present invention, the operating clock of the universal serial bus host is independent of the clock signal.

To achieve the above objective, the present invention provides an audio data synchronization method, which includes the following steps: receiving an audio packet from a universal serial bus host; storing the audio packet in A first-in-first-out buffer; set a maximum data volume threshold and a minimum data volume threshold of the first-in-first-out buffer; generate a clock signal; output audio packets and output from the first-in-first-out buffer through a data transmission interface Clock signal to an audio codec; use the audio codec to process audio packets according to the clock signal to output audio; determine whether the amount of data stored in the first-in first-out buffer is greater than the threshold of the maximum amount of data or less than the minimum amount of data When it is judged that the amount of data stored in the first-in first-out buffer is greater than the threshold of the maximum amount of data, increase the frequency of the clock signal; and when it is judged that the amount of data stored in the first-in-first-out buffer is less than the threshold of the minimum amount of data When, reduce the frequency of the clock signal.

According to an embodiment of the present invention, the data transmission interface is an I ² S interface for transmitting the audio packet to the audio codec.

According to an embodiment of the present invention, the audio data synchronization method of the present invention includes using a counter. When the counter count reaches a preset value, the counter generates a trigger signal to trigger the judgment of the first-in-first-out buffer. The status of the data volume is used to repeatedly determine the status of the data volume stored in the first-in-first-out buffer.

According to an embodiment of the present invention, the counter counts based on the clock signal.

According to an embodiment of the present invention, the operating clock of the universal serial bus host is independent of the clock signal.

As mentioned above, the object of the present invention is to provide an audio data synchronization device and method. The processor continuously counts the amount of data in the first-in-first-out buffer, and then feeds back and controls the frequency of the clock signal according to the amount of data. The data transmission speed of the universal serial bus host can be effectively synchronized with the speed of the audio codec, so as to avoid overflow or underload of the buffer data due to the asynchrony between the two, and the phenomenon of sound breakage.

100: processor

101: Universal serial bus host

1011: Audio packet

111: Universal Serial Bus Module

112: FIFO buffer

1121: data volume

113: Data Transmission Interface

114: control unit

115: counter

116: Clock Generator

1171: Clock signal

120: trigger signal

130: Audio codec

200: Architecture diagram

201: Universal Serial Bus Host Oscillator

301: Maximum data volume threshold

302: I ² S interface

401: Minimum data volume threshold

501, 502, 503, 504, 505, 506, 601, 602, 603, 604, 605, 606, 607: steps

Figure 1 is a block diagram of the audio data synchronization device of the present invention.

Figure 2 is a block diagram of the audio data synchronization device of the present invention.

Figure 3 is a schematic diagram illustrating the operation of the present invention to avoid overflow of data in the first-in-first-out buffer.

Figure 4 is a schematic diagram illustrating the operation of the present invention to avoid under-loading of data in the first-in-first-out buffer.

Figure 5 is a flowchart of the audio data synchronization method of the present invention.

Figure 6 is a flowchart of an embodiment of the audio data synchronization method of the present invention.

Hereinafter, with reference to the accompanying drawings, the embodiments according to the present invention will be described in detail to make it easy for those skilled in the art to understand. The above-mentioned creation can be implemented in a variety of variations, but should not be limited to these embodiments. The description of the well-known part is omitted in the present invention, and the same reference numbers represent the same elements in the present invention.

Please refer to FIG. 1 to FIG. 4, which show the block diagram and operation schematic diagram of the audio data synchronization device of the present invention. As shown in FIG. 1, the audio data synchronization device includes a universal serial bus (USB) host 101, a processor 100, and an audio codec 130. The processor 100 is connected between the universal serial bus host 101 and the audio codec 130, as a bridge between the universal serial bus host and the audio codec, the processor 100 can receive the universal serial bus host 101 The audio packet is then sent to the audio codec 130 as a sound source.

The processor 100 includes a universal serial bus (USB) module 111, a first-in-first-out (FIFO) buffer 112, a clock generator 116, a control unit 114, a counter 115, and a data transmission interface 113. In one embodiment, the universal serial bus host can be set in a computer, and the audio codec 130 can be a microphone or speaker connected to the universal serial bus port of the computer; the data transmission interface 113 can be an integrated Inter-IC Sound (I ² S) interface.

The universal serial bus host 101 is used to transmit an audio packet 1011 and stored in the first-in first-out buffer 112 of the processor 100. The universal serial bus module 111 is used to receive the audio packet 1011, the first-in first-out buffer 112 is used to store the audio packet 1011, and the clock generator 116 is used to generate a clock signal 1171. The data transmission interface 113 is used to output the audio packet 1011 from the first-in first-out buffer 112 and output the clock signal 1171 to the audio codec 130. The audio codec 130 can receive the audio packet 1011 and the clock signal 1171 through the data transmission interface 113 of the processor 100, and process the audio packet 1011 according to the clock signal 1171 to output audio.

Since the universal serial bus protocol is an asynchronous design, the universal serial bus host and audio codec will use their own independent clock signals. As shown in Figure 2, the universal serial bus host 101 uses the universal serial bus The host oscillator 201 is used as the clock source, and the audio codec 130 uses the clock signal 1171 provided by the processor 100 as its clock source, so the audio codec 130 performs decoding processing speed (for example, playing audio or recording) If it is not synchronized with the generation speed of the audio packet (computer processing speed), the packet processing time will easily cause the buffer data overflow or underload, which will cause the problem of audio cracking.

To solve this problem, the control unit 114 stores and sets a maximum data volume threshold 301 (as an upper limit) and a minimum data volume threshold 401 (as a lower limit), and determines the data volume 1121 stored in the first-in first-out buffer 112 Whether it is greater than the maximum data volume threshold 301 or less than the minimum data volume threshold 401.

As shown in Figure 3, when the control unit 114 determines that the data volume 1121 stored in the first-in first-out buffer 112 is greater than the maximum data volume threshold 301, it means that the audio codec 130 is currently processing audio The packet speed is slower than the audio packet generation speed. Therefore, the data stored in the first-in first-out buffer 112 is increasing and has reached the maximum data volume threshold 301. Once the data stored in the first-in first-out buffer 112 continues to increase and exceed The storage capacity of the first-in-first-out buffer 112 will cause the buffer data to overflow, resulting in broken sound.

In order to avoid breaking the sound, the control unit 114 controls the clock generator 116 to increase the frequency of the clock signal 1171. Since the audio codec 130 ^{obtains the clock signal through the I 2} S interface 302 as the clock source, the clock signal is increased. The frequency of 1171 can increase the processing speed of the audio codec 130 to process more audio packets. Therefore, the data volume 1121 of the first-in first-out buffer 112 will gradually decrease and be lower than the maximum data volume threshold 301.

When the control unit 114 determines that the data volume 1121 stored in the first-in-first-out buffer 112 is less than the minimum data volume threshold 401, it means that the current audio codec 130 is processing audio packets faster than the audio packet generation speed, so first-in-first-out The data stored in the buffer 112 is getting less and less, and has reached the minimum data volume threshold 401; once the data stored in the first-in-first-out buffer 112 continues to decrease and there is no audio packet for the audio codec 130 to process, it will cause The buffer data is under-loaded, resulting in broken sound.

In order to avoid sound breaking, the control unit 114 controls the clock generator 116 to reduce the frequency of the clock signal 1171, thereby reducing the processing speed of the audio codec 130 to process fewer audio packets. Therefore, the data volume of the first-in first-out buffer 112 will gradually increase and be higher than the minimum data volume threshold 401.

If the data volume 1121 stored in the first-in first-out buffer 112 is between the maximum data volume threshold 301 and the minimum data volume threshold 401, the clock speed will not be changed. Through the above control method, the processor 100 can continuously adjust the processing speed of the audio codec 130 to avoid broadcasting problems.

As shown in FIG. 1 again, the processor 100 can use the counter 115 to continuously trigger the control unit 114 to make the above determination. If the control unit 114 confirms the data amount of the first-in first-out buffer 112 every millisecond, the change of the data amount of the first-in first-out buffer 112 is not obvious enough; therefore, the counter 115 can be set to take a longer time (for example, a Sec) to count to make the change of the data amount of the first-in-first-out buffer 112 obvious enough to determine whether the frequency of the clock signal 1171 needs to be adjusted, thereby improving the accuracy.

In one embodiment, the counter 115 outputs a trigger signal (or interrupt signal) 120, such as a tick, when the counter 115 counts to a preset value. When the control unit 114 receives the trigger signal 120, it reads the data volume 1121 of the first-in first-out buffer 112, and performs the above-mentioned judgment. The counter 115 resets its count value after outputting the trigger signal 120 and restarts counting. The counter 115 can count according to the clock signal 1171.

In one embodiment, the clock generator 116 may include an oscillator and a clock signal generating unit. The oscillator generates an oscillating signal, and the clock signal generating unit generates a clock signal suitable for subsequent circuits according to the oscillating signal. The oscillator can be implemented with an RC oscillator or a crystal oscillator. In order to adjust or fine-tune the frequency of the clock signal, the control unit 114 can change the voltage or current applied to the oscillator, thereby changing the frequency of the oscillating signal, thereby changing the frequency of the clock signal. However, the foregoing is only an example, and is not intended to limit the present invention. Any technology that can adjust the frequency of the clock signal can be applied to the present invention.

Please refer to Figure 5, which is a flowchart of the audio data synchronization method of the present invention. As shown in FIG. 5, the audio data synchronization method of the present invention includes the following steps 501 to 506. In step 501, an audio packet is received from a universal serial bus host. In step 502, the audio packets are stored in a first-in first-out buffer. In step 503, a maximum data volume threshold 301 and a minimum data volume threshold 401 of the first-in first-out buffer are set. In step 504, a clock signal is generated, and an audio packet is output from the first-in first-out buffer and the clock signal is output to an audio codec through a data transmission interface.

In step 505, it is determined whether the amount of data stored in the first-in first-out buffer is greater than the maximum data amount threshold 301 or less than the minimum data amount threshold 401. When it is determined that the data amount stored in the first-in-first-out buffer is greater than the maximum data amount threshold When the value is 301, the clock generator 116 is controlled to increase the frequency of the clock signal. When it is determined that the amount of data stored in the first-in-first-out buffer is less than the minimum data amount threshold 401, the clock generator 116 is controlled to decrease the frequency of the clock signal. frequency.

In step 506, the audio codec is used to process the audio packet according to the clock signal to output audio. Thereby, the audio data synchronization method of the present invention can provide a clock signal to the audio codec through the data transmission interface, and continuously monitor the change of the data storage capacity of the first-in-first-out buffer storing the audio packets, when the data storage capacity exceeds The upper limit will reduce the frequency of the clock signal. When the data storage is lower than the lower limit, the frequency of the clock signal will be increased, and the frequency of the clock signal will be adjusted accordingly to effectively enable the audio codec to process audio packets. The speed is synchronized with the speed of the audio packets provided by the universal serial bus host to prevent the sound breakage caused by the overflow or underload of the first-in-first-out buffer.

Please refer to FIG. 6, which is a flowchart of an embodiment of the audio data synchronization method of the present invention. As shown in Figure 6, this embodiment includes the following steps 601 to 607, and can be applied to the audio data synchronization device shown in Figure 1. .

In step 601, the control unit 114 waits for an interrupt signal generated by the counter 115. In step 602, the data size stored in the first-in first-out buffer 112 is read. In step 603, it is judged whether the amount of data stored in the data first-in first-out buffer 112 is less than the minimum data amount threshold 401, if yes, go to step 604, reduce the frequency of the clock signal 1171, if not, go to the next step . In step 505, it is determined whether the amount of data stored in the data first-in first-out buffer 112 is greater than the maximum data amount threshold 301, if yes, go to step 606 to increase the frequency of the clock signal 1171, if not, go to the next step ; In step 607, the frequency of the clock signal 1171 is not changed.

In summary, the present invention proposes a dynamic clock adjustment technology to synchronize the speed of audio packet generation and the speed of audio packet encoding and decoding to detect whether the amount of data in the first-in-first-out buffer is less than the minimum amount of data every second If the threshold value is greater than the threshold value of the maximum data volume, ^{the frequency of the clock signal sent to the audio codec via the I 2} S interface is adjusted to dynamically adjust the codec speed of the audio codec in time.

However, the illustrations and descriptions disclosed above are only the preferred embodiments of the present invention, and are not intended to limit the implementation of the present invention. Anyone familiar with the art will make changes based on the spirit of the present invention. Or modification shall be included in the scope of the following patent application in this case.

100: processor

101: Universal serial bus host

1011: Audio packet

111: Universal Serial Bus Module

112: FIFO buffer

1121: data volume

113: Data Transmission Interface

114: control unit

115: counter

116: Clock Generator

1171: Clock signal

120: trigger signal

130: Audio codec

Claims (8)

An audio data synchronization device, comprising: a universal serial bus host for transmitting an audio packet; a processor, comprising: a universal serial bus (USB) module for receiving the audio packet; a first-in first-out (FIFO) buffer to store the audio packet; a clock generator to generate a clock signal; a control unit to store a maximum data volume threshold and a minimum data volume threshold, and determine the first-in-first-out Whether the data volume stored in the buffer is greater than the maximum data volume threshold or less than the minimum data volume threshold, when the control unit determines that the data volume stored in the first-in-first-out buffer is greater than the maximum data volume threshold The control unit controls the clock generator to increase the frequency of the clock signal. When the control unit determines that the amount of data stored in the first-in-first-out buffer is less than the minimum data amount threshold, the control unit controls the time The pulse generator reduces the frequency of the clock signal; a counter, when the counter count reaches a preset value, the counter generates a trigger signal to the control unit to trigger the control unit to determine the storage of the first-in first-out buffer The state of the amount of data, thereby allowing the control unit to repeatedly determine the state of the amount of data stored in the first-in-first-out buffer; and a data transmission interface that outputs the audio packet from the first-in-first-out buffer, And output the clock signal; and an audio codec that receives the audio packet and the clock signal through the data transmission interface, and processes the audio packet according to the clock signal to output audio. The audio data synchronization device according to claim 1, wherein the data transmission interface is an Inter-IC Sound (I ² S) interface for transmitting the audio packet to the audio codec. The audio data synchronization device according to claim 1, wherein the counter counts based on the clock signal. The audio data synchronization device according to claim 1, wherein the operating clock of the universal serial bus host is independent of the clock signal. An audio data synchronization method includes: receiving an audio packet from a universal serial bus host; storing the audio packet in a first-in-first-out buffer; setting a maximum data volume threshold and a minimum value of the first-in-first-out buffer Data volume threshold; generate a clock signal; through a data transmission interface, output the audio packet from the first-in-first-out buffer and output the clock signal to an audio codec; use the audio codec according to the clock Signal processing the audio packet to output audio; using a counter to count, when the counter reaches a preset value, the counter generates a trigger signal to trigger the judgment of the amount of data stored in the first-in-first-out buffer State, thereby repeatedly determining the state of the amount of data stored in the first-in-first-out buffer. When it is determined that the amount of data stored in the first-in-first-out buffer is greater than the maximum data amount threshold, the clock signal is increased Frequency; and when it is determined that the amount of data stored in the first-in-first-out buffer is less than the threshold value of the minimum amount of data, reduce the frequency of the clock signal. The audio data synchronization method according to claim 5, wherein the data transmission interface is an I ² S interface for transmitting the audio packet to the audio codec. The audio data synchronization method according to claim 5, wherein the counter counts based on the clock signal. The audio data synchronization method according to claim 5, wherein the operating clock of the universal serial bus host is independent of the clock signal.

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