JP2002342092A - Data processor and data processing control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively utilize the resources of a data processing circuit inside a data processor. SOLUTION: According to an interruption reduction number set to an interruption signal control circuit 3 by a controller 1, the interruption signal control circuit 3 generates interruption signals INT for which the number of times of interruption is reduced and outputs them to the data processing circuit 4 on the basis of clock signals CLK and the number of times of performing an interruption processing per unit time in the data processing circuit 4 is reduced. Thus, the number of times of performing an interruption start processing and an interruption end processing is reduced and the resources of the data processing circuit 4 are effectively utilized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus and a data processing control method, and more particularly, to inputting data for performing predetermined processing or performing predetermined processing on input data in response to an interrupt signal. This is suitable for use in a data processing device that outputs data in response to an interrupt signal.

[0002]

2. Description of the Related Art Conventionally, some audio equipment such as AV amplifiers and DVDs are provided with an audio data processing device for performing various processes on audio data input from outside or generated inside the audio equipment. there were. The audio data processing device is a DSP
(Digital signal processor) and the like, and the audio data is subjected to predetermined processing and output based on instructions from a controller (CPU).

FIG. 5 is a block diagram showing a configuration of a conventional audio data processing device. In FIG. 5, reference numeral 41 denotes a clock supply circuit, which supplies a clock signal LRCK to DS.
It is supplied to P42 and the data output circuit 43. When the data output circuit 43 outputs the output data DTO to the outside, the clock signal LRCK is applied to Lch (left channel).
This signal is for distinguishing and outputting data of Rch (right channel). Further, the clock signal LRCK is supplied to the DSP 42 as an interrupt signal INT for the DSP 42 to output the processing data DTP.

[0004] The DSP 42 decodes (decodes) compressed input data DTI of a predetermined format supplied from outside the audio data processing apparatus according to a predetermined algorithm. Further, the DSP 42 receives the input data D in response to the clock signal LRCK supplied from the clock supply circuit 41 as an interrupt signal INT.
Process the decoded result (decoded data) of the TI into processing data DTP
The data is sequentially transmitted in parallel to the data output circuit 43 and supplied.

A data output circuit 43 buffers the processed data DTP of the parallel data supplied from the DSP 42 and converts it into output data DTO of serial data. Further, the data output circuit 43 outputs the output data DTO to a DAC (D / A converter) (not shown) in accordance with the clock signal LRCK supplied from the clock supply circuit 41 while distinguishing between Lch data and Rch data. For example, when the clock signal LRCK is at a high level (hereinafter, referred to as “H”), the data output circuit 43 outputs the output data DTO of Lch data, and the clock signal LRCK is at a low level (hereinafter, referred to as “H”). In the case of “L”, the data output circuit 43 outputs the output data DTO of the Rch data.

FIG. 6 is a diagram for explaining the operation of the DSP 42 in the conventional audio data processing device shown in FIG. As shown in FIG. 6, when the clock signal LRCK supplied from the clock supply circuit 41 as the interrupt signal INT changes from “L” to “H”, the DSP 4
No. 2 determines that an interrupt request has been made. When determining that the interrupt request has been made, the DSP 42 suspends the normal processing (main routine processing) and starts the interrupt processing. That is, at times T ₁₁ , T ₁₂ , T ₁₃ , T ₁₄ and T _{15 at} which the clock signal LRCK rises, DS
P42 is a main routine processing MP11 for reading and decoding input data DTI supplied from the outside,
MP12, MP13, MP14 and MP15 (DSP
The processing time t _MP ) is interrupted. And DSP42
Is the result of decoding the input data DTI (decoded data)
To the data output circuit 43.

[0007] The interrupt processing is an interrupt start processing S11.
To S15 (processing time t _S ), interrupt routine processing IP1
1 to IP14 (processing time t _IP ) and interrupt end processing R
Each consists 11～R14 (process time t _R). The interrupt start processes S11 to S15 are performed by the DSP 42
Is performed in the main routine processes MP11 to MP
This is a process for shifting from S15 to interrupt routine processes IP11 to IP14. The above interrupt start processing S11-
In S15, the DSP 42 executes the main routine processing M
At the time of interruption of P11 to MP15, the state of the general-purpose register (not shown) provided in the DSP 42 (the value in the general-purpose register) and the like are saved in a predetermined register (save register).

The above interrupt routine processing IP11 to IP1
4 is a process of outputting the decoding result (decoded data) of the input data DTI processed in the main routine processes MP11 to MP15 from the DSP 42 to the data output circuit 43. The above interrupt routine processing IP11 to IP1
In DSP 4, the DSP 42 executes the main routine processing MP1.
In 1 to MP15, the input data DTI is read and decoded, and the decoding result of the input data DTI stored in a predetermined buffer memory is read. And DS
P42 outputs a decoding result of the input data DTI read from the predetermined buffer memory to the data output circuit 43 as processing data DTP.

In the interrupt routine IP11, the DSP 42 outputs the decoding result of the input data DTI in the main routine MP11 to the data output circuit 4.
3 and the input data DTI in the main routine process MP12 in the interrupt routine process IP12.
Is output to the data output circuit 43. Similarly, the DSP 42 outputs the decoding result of the input data DTI in the main routine processes MP13 and MP14 to the data output circuit 43 in the interrupt routine processes IP13 and IP14, respectively.

In addition, the above-described interrupt end processing R11 to R14
Executes the processing performed by the DSP 42 from the interrupt routine processing IP11 to IP14 to the main routine processing MP1.
This is a process for shifting to 1 to MP15. In the interrupt end processing R11 to R14, the DSP 42
The state of the general-purpose registers provided in 42 (the value in the general-purpose registers) and the like are restored to the state before interrupt processing is performed. That is, the DSP 42 performs the interrupt start processing S11 to S15.
The state of the general-purpose register (value in the general-purpose register) saved in a predetermined register or the like is restored, and the state of the general-purpose register at the time of interruption of the main routine processing MP11 to MP15 is restored. After that, the DSP 42 executes again the main routine process interrupted by the interrupt process.

As described above, the DSP 42 repeats the main routine processing and the interrupt processing. As a result, as long as the input data DTI is supplied from the outside, the DSP 42 outputs the input data DT so that the output data DTO output from the audio data processing device is not interrupted.
The decoding result of I is output to the data output circuit 43.

[0012]

However, in the above-mentioned conventional audio data processing apparatus, the clock signal LRCK supplied to the data output circuit is always supplied to the DSP as an interrupt signal INT each time. Rises, that is, every time an interrupt request is generated by the clock signal LRCK, the DSP executes the interrupt processing. As a result, in DSP,
The ratio of the processing amount and processing time required for interrupt processing to the processing amount and processing time of the entire DSP has increased.

In particular, the DSP uses the clock signal LRC
Every time there is an interrupt request by K, an interrupt start process (a save process of the state of the general-purpose register and the like) for performing an interrupt routine process and an interrupt end process (a restore process of the state of the saved general-purpose register and the like) must be performed. did not become.
Therefore, the processing time and time required for the DSP to perform the normal processing such as the main routine processing can be reduced by the processing amount and processing time required for the interrupt start processing and the interrupt end processing which must be executed for each interrupt request. There was a problem that resources could not be used effectively.

The present invention has been made to solve such a problem, and the ratio of the processing amount and processing time required for interrupt processing to the processing amount and processing time of the entire data processing circuit in the data processing device is determined. It is an object of the present invention to reduce the cost and to make effective use of the resources of the data processing circuit.

[0015]

According to the present invention, there is provided a data processing apparatus comprising: a setting circuit for setting a set value; and the number of interrupts smaller than the number of interrupts of a first interrupt signal to be inputted according to the set value. An interrupt signal control circuit for generating and outputting a second interrupt signal; input processing of data for performing predetermined processing in accordance with the second interrupt signal; and output processing of data subjected to predetermined processing And a data processing circuit for performing at least one of the processes.

According to the present invention configured as described above, a second interrupt signal having a smaller number of interrupts than the number of interrupts of the first interrupt signal is generated according to the set value and supplied to the data processing circuit. Therefore, the number of executions of the interrupt processing in the data processing circuit per unit time is reduced,
It is possible to reduce the ratio of the time required for the interrupt start process and the interrupt end process per unit time, which has been executed for each interrupt, to the unit time, and to increase the ratio of the time during which the data processing circuit performs the normal process. become.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram showing a configuration of a data processing device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a controller, and an interrupt signal (clock signal CLK) input in an interrupt signal control circuit 3
The interrupt reduction number setting signal SET for setting the reduction number (hereinafter, referred to as “interruption reduction number”) of the interrupt number of the output interrupt signal INT is supplied to the interrupt signal control circuit 3. The number of interrupt reductions is
This is a ratio of the number of interrupts of the clock signal CLK to the number of interrupts of the interrupt signal INT, and an arbitrary reduction number can be set. For example, if the interrupt reduction number is “4”, the interrupt signal control circuit 3 outputs the clock signal C
It outputs an interrupt signal INT that generates one interrupt every four interrupts by LK.

The controller 1 controls each functional unit such as the data processing device, and writes predetermined data into a register (not shown) in the data processing circuit 4 by a control signal CTL, or reads data from the register. Read. Further, the controller 1 instructs start, end, stop, and the like of the processing operation of the data processing circuit 4.

Reference numeral 2 denotes an interrupt signal generating circuit which supplies the generated clock signal CLK to the interrupt signal control circuit 3 as an interrupt signal and also supplies the clock signal CLK to the data input / output circuit 5.

The interrupt signal control circuit 3 controls the interrupt signal (clock signal CL) supplied from the interrupt signal generation circuit 2 according to the interrupt reduction number set by the interrupt reduction number setting signal SET supplied from the controller 1.
A new interrupt signal INT in which the number of interrupts in K) is reduced is generated and supplied to the data processing circuit 4. That is, the interrupt signal control circuit 3 reduces the interrupt by the clock signal CLK supplied from the interrupt signal generating circuit 2 in accordance with the set interrupt reduction number.
T is supplied to the data processing circuit 4.

The data processing circuit 4 includes a data input / output circuit 5
And an input / output terminal for transmitting and receiving data DT to / from the data input / output circuit 5 and the data input / output circuit 5 based on an instruction from the controller 1 or the like.
A predetermined process is performed on the data DT supplied from. Then, the data processing circuit 4 reads the data DT from the data input / output circuit 5 according to the interrupt by the interrupt signal INT supplied from the interrupt signal control circuit 3,
The data subjected to the predetermined processing is output to the data input / output circuit 5.

The data processing circuit 4 can refer to the interrupt reduction number set in the interrupt signal control circuit 3 and is supplied from the data input / output circuit 5 according to the interrupt reduction number. A predetermined process is performed on the data DT. When the data processing circuit 4 refers to the interrupt reduction number, first, it outputs an interrupt reduction number notification request signal REQ requesting notification of the interrupt reduction number to the interrupt signal control circuit 3. Then, the data processing circuit 4 refers to the interrupt reduction number set by the interrupt reduction number reference signal REF supplied from the interrupt signal control circuit 3 as a response to the interrupt reduction number notification request signal REQ.

The data input / output circuit 5 includes an input terminal and an output terminal for exchanging data such as audio data with the outside of the data processing device and with the data processing circuit 4.
Alternatively, input / output terminals are provided. The data input / output circuit 5 accumulates data supplied from outside the data processing device according to the clock signal CLK supplied from the interrupt signal generation circuit 2 and supplies the accumulated data to the data processing circuit 4 Or Also,
The data input / output circuit 5 accumulates data which has been subjected to predetermined processing and is supplied from the data processing circuit 4, and outputs the accumulated data to the outside.

In FIG. 1, the interrupt signal INT output from the interrupt signal control circuit 3 is supplied only to the data processing circuit 4, but the interrupt signal INT is supplied to the data input / output circuit 5. You may do it.

Next, the operation will be described. In the following description, the clock signal CLK output as an interrupt signal from the interrupt signal generating circuit 2 rises (“L”).
→ change to "H"), an interrupt by the clock signal CLK from the interrupt signal generating circuit 2 is assumed to occur.

First, the controller 1 sets the interrupt reduction number in the interrupt signal control circuit 3 by the interrupt reduction number setting signal SET. Next, a data processing operation by the data processing device is started. At this time, the interrupt signal generation circuit 2
Then, supply of the clock signal CLK of a predetermined cycle to the interrupt signal control circuit 3 and the data input / output circuit 5 is started. The interrupt signal control circuit 3 supplied with the clock signal CLK detects the rise of the clock signal CLK and counts the number of interrupts by a counter or the like. The number of interrupts is counted by incrementing the count value by one each time a rising edge of the clock signal CLK is detected.

When the detected number of interrupts of the clock signal CLK becomes equal to the set value of the interrupt reduction number, the interrupt signal control circuit 3 outputs the interrupt signal INT.
Is output to the data processing circuit 4. That is, the interrupt signal control circuit 3 sets the clock signal C to a predetermined value, where N is an arbitrary number.
An interrupt by the interrupt signal INT is output to the data processing circuit 4 every N cycles of LK.

When the data processing circuit 4 to which the interrupt signal INT is supplied detects an interrupt due to the interrupt signal INT, it performs interrupt processing (interrupt start processing, interrupt routine processing, and interrupt end processing). For example, upon detecting an interrupt due to the interrupt signal INT, the data processing circuit 4 reads data DT to be processed in at least N periods of the clock signal CLK from the data input / output circuit 5. Further, for example, the data processing circuit 4
Detects an interrupt due to the interrupt signal INT,
Data D that has been subjected to predetermined processing before detecting the interrupt
And outputs T to the data input / output circuit 5. The data DT output to the data input / output circuit 5 is data of a data amount output from the data input / output circuit 5 to the outside during at least N periods of the clock signal CLK.

According to the data processing device configured as shown in FIG. 1, the interrupt signal IN with respect to the number of interrupts of the clock signal CLK supplied from the interrupt signal generation circuit 2
The controller 1 sets an interruption reduction number of the interruption number of T in the interruption signal control circuit 3, and the interruption signal control circuit 3 reduces the interruption number based on the clock signal CLK in accordance with the set interruption reduction number. Generate an interrupt signal INT. Then, the data processing circuit 4
In response to the interruption by the interruption signal INT, an interruption process for reading the data DT to be decoded from the data input / output circuit 5 and outputting the decoding result of the data DT to the data input / output circuit 5 is executed.

Thus, the data processing circuit 4 executes the interrupt processing not for each interruption by the clock signal CLK but for each interruption by the interruption signal INT in which the number of interruptions is reduced. It is possible to reduce the number of executions of the interrupt process per unit, to reduce the number of executions of the interrupt start process and the interrupt end process, and to shorten the time required for the unit time. Therefore, the time required for the data processing circuit 4 to perform the main routine processing per unit time can be increased, and the resources of the data processing circuit 4 can be effectively used.

Since an arbitrary interrupt reduction number can be set in the interrupt signal control circuit 3 by the interrupt reduction number setting signal SET output from the controller 1, the main routine processing performed by the data processing circuit 4 per unit time is performed. The number of interrupt reductions can be set in accordance with the amount of processing. For example, when it is desired to increase the processing amount of the main routine processing performed by the data processing circuit 4 (to increase the resources of the data processing circuit 4), the number of interrupt reductions is increased, and conversely, the main routine processing performed by the data processing circuit 4 If it is desired to reduce the processing amount (reduce the resources of the data processing circuit 4), the number of interrupt reductions is reduced. Therefore, the number of interrupt reductions can be set according to the resources used in the data processing circuit 4, and the resources of the data processing circuit 4 can be used effectively.

In the data processor shown in FIG. 1, when the rising edge of the clock signal CLK is detected by the interrupt signal control circuit 3 and the number of interrupts is counted by a counter or the like, the rising edge of the clock signal CLK is detected. Each time, the count value is incremented by one and counted, but the set value of the interrupt reduction number is set in a counter or the like as an initial value, and the count value is decremented by one each time the rising edge of the clock signal CLK is detected. You may do it. In this case, the count value is “0”.
Is reached, the interrupt signal control circuit 3 outputs the interrupt signal I
An interrupt by NT is output to the data processing circuit 4.

Next, a specific embodiment of the data processing apparatus as shown in FIG. 1 will be described with reference to the drawings. (First Embodiment) FIG. 2 is a block diagram showing a configuration example of an audio data processing device to which a data processing device according to a first embodiment of the present invention is applied.

The audio data processing device shown in FIG.
Interrupt signal I generated based on clock signal LRCK
In accordance with NT, data (processed data DTP) obtained by subjecting input data DTI, which is audio data supplied from the outside, to predetermined processing is output, and in accordance with a clock signal LRCK, the data is processed outside the audio data processing apparatus, for example, not shown. The above processing data DTP is stored in a DAC (D / A converter).
Is converted into output data DTO and output.

In FIG. 2, reference numeral 11 denotes a CPU, which counts the number of interrupts of a clock signal LRCK supplied from the clock supply circuit 14 as an interrupt signal.
The interrupt reduction number setting signal SET for setting an arbitrary interrupt reduction number by the interrupt signal INT output from the
Feed to 2. The CPU 11 controls each functional unit such as the DSP 15 (digital signal processor) by a control signal or the like (not shown).

The register 12 sets and holds the number of interrupt reductions in accordance with the interrupt reduction number setting signal SET supplied from the CPU 11. The counter 13 receives an interrupt by the clock signal LRCK from the clock supply circuit 14 according to the interrupt reduction number set in the register 12, generates an interrupt signal INT in which the number of interrupts is reduced, and supplies the interrupt signal INT to the DSP 15. The above register 1
2 and the counter 13 correspond to the interrupt signal control circuit 3 shown in FIG.

Specifically, the counter 13 increments the count value by one every time an interrupt due to the clock signal LRCK is detected.
The number of interrupts is counted by incrementing by one. Also,
The counter 13 refers to the set value of the interrupt reduction number set in the register 12 and determines whether or not the set value of the interrupt reduction number matches the count value of the interrupt count of the clock signal LRCK. As a result of the determination, when the set value of the number of interrupt reductions matches the count value of the number of interrupts of the clock signal LRCK, the counter 13 outputs an interrupt due to the interrupt signal INT to the DSP 15 and simultaneously outputs the interrupt by the clock signal LRCK. Is reset to "0". On the other hand, when the set value of the interrupt reduction number does not match the count value of the number of interrupts of the clock signal LRCK, the counter 13 continues counting the number of interrupts by the clock signal LRCK.

The clock supply circuit 14 is provided with the DSP 15
When the data subjected to the predetermined processing is output to the outside as output data DTO, a clock signal LRCK for separately outputting Lch (left channel) data and Rch (right channel) data is output to the data output circuit 16. Supply. Note that the clock signal LRCK is a clock signal having the same frequency as the sampling frequency used in audio equipment including the audio data processing device and configured, for example, 44.1 kHz (CD standard) and 48 kHz (DVD standard). Clock signal. Further, the clock supply circuit 14 supplies the clock signal LRCK to the counter 13 as an interrupt signal for outputting the processing data DTP from the DSP 15.

The DSP 15 reads input data DTI supplied at a certain timing from the outside, and decodes the input data DTI according to a predetermined algorithm. Further, the DSP 15 accumulates and stores a decoding result (decoded data) obtained by the decoding in a buffer memory (not shown) provided therein. Here, the input data DTI includes a plurality of compressed bit strings in a predetermined format, and the plurality of bit strings are bit strings of a predetermined size.

In response to the interrupt signal INT reduced in the number of interrupts supplied from the counter 13, the DSP 15 decodes the decoded result (decoded data) of the input data DTI accumulated and stored in the buffer memory into the processing data D.
TP is sequentially transmitted to the data output circuit 16 in parallel,
Supply. The DSP 15 can refer to the set value of the interrupt reduction number set in the register 12 via the interrupt reduction number reference signal NREF, and is supplied from outside according to the set value of the interrupt reduction number. The input data DTI is subjected to a predetermined process.

The data output circuit 16 buffers the processed data DTP of the parallel data supplied from the DSP 15, converts the processed data DTP into serial data output data DTO, and outputs it. At this time, the data output circuit 16 outputs the clock signal L supplied from the clock supply circuit 14.
In accordance with RCK, the output data DTO is distinguished into Lch data and Rch data and output to an external device, for example, a DAC (not shown). For example, the clock signal LRCK
Is high level (hereinafter, referred to as “H”), the data output circuit 16 outputs the output data DTO of Lch data, and the clock signal LRCK is at low level (hereinafter, referred to as “L”). .), The data output circuit 16 outputs the output data DTO of the Rch data.

Next, the operation will be described. In the following description, when the clock signal LRCK supplied as an interrupt signal from the clock supply circuit 14 rises (changes from “L” to “H”), an interrupt by the clock signal LRCK from the clock supply circuit 14 occurs. It shall be. Further, the CPU 11 registers the interrupt reduction number in the register 1 in advance by the interrupt reduction number setting signal SET.
It is assumed that the number is set to 2 and the set value of the number of interrupt reductions is N (N is an arbitrary number).

First, when the data processing operation is started by the audio data processing device, the clock supply circuit 1
From 4, the supply of the clock signal LRCK of a predetermined cycle to the counter 13 and the data output circuit 16 is started. Counter 1 to which the clock signal LRCK is supplied
Reference numeral 3 detects an interrupt (rising edge of the clock signal LRCK) caused by the clock signal LRCK, and increments the count value by one each time an interrupt is detected, and counts the number of interrupts of the clock signal LRCK. Further, the counter 13 refers to the set value of the interrupt reduction number set in the register 12, compares the set value of the interrupt reduction number with the count value of the interrupt count, and compares the set value of the interrupt reduction number with the set value of the interrupt reduction number. When the count value of the number of interrupts is not equal, the detection and counting of the interrupt by the clock signal LRCK are continuously performed.

On the other hand, as a result of the comparison, if the set value of the number of interrupts is equal to the count of the number of interrupts,
The counter 13 outputs an interrupt signal INT to the DSP 15, and resets the count value of the number of interrupts to "0".
That is, the counter 13 outputs the clock signal LRCK.
An interrupt signal INT is output to the DSP 15 every N periods.

When an interrupt due to the interrupt signal INT output from the counter 13 to the DSP 15 is detected by the DSP 15, the DSP 15 interrupts the normal processing (main routine processing) and executes the interrupt processing (interrupt start processing, interrupt routine processing). And interrupt end processing).
In the interrupt processing, the DSP 15 first saves the value of a general-purpose register provided inside the DSP 15 when the main routine processing is interrupted to a predetermined register (save register) (interrupt start processing).

Next, the DSP 15 outputs the processing data DTP to the data output circuit 16 (interrupt routine processing). The data amount of the processing data DTP output from the DSP 15 is the data amount output from the data output circuit 16 to the outside during the period of N cycles of the clock signal LRCK. When the interrupt routine processing is completed, D
The SP 15 restores the value of the general-purpose register saved in a predetermined register (save register) in the interrupt start process, and restores the state at the time of interruption of the main routine process before performing the interrupt process (interrupt end process). The operation of the main routine process is restarted.

The counter 13 detects an interrupt by the clock signal LRCK and counts the number of times, regardless of whether or not the interrupt processing operation is being performed. Then, when the set value of the interrupt reduction number becomes equal to the count value of the interrupt count again, the counter 13 resets the count value of the interrupt count to “0” and outputs the interrupt signal INT to the DSP 15. When the DSP 15 detects the interruption by the interruption signal INT, the DSP 15 interrupts the main routine processing again and starts the interruption processing.

The operation of the DSP 15 in the above operation will be described with reference to FIG. FIG. 3 is a diagram for explaining the operation of the DSP 15 in the audio data processing device shown in FIG. In FIG. 3,
The case where the set value N of the interrupt reduction number set by the interrupt reduction number setting signal SET is 4 is shown.

The interrupt routine processing IP shown in FIG.
1 and the main routine process MP2, in order to facilitate comparison with FIG. 6, each time corresponding to the interrupt routine processes IP11 to IP14 and the main routine process MP11 to MP14 shown in FIG.
P11 'to IP14' and MP15 'to MP18'
(MP11 ′ to MP14 ′), but DS
In the process at P15, the interrupt routine process IP1 and the main routine process MP2 are not divided as described above, but are each a series of processes.

At time T ₁ , the counter 13 reads the register 1
It is determined that the set value of the interrupt reduction number set to 2 matches the count value of the number of interrupts by the clock signal LRCK, and an interrupt by the interrupt signal INT is output from the counter 13 to the DSP 15. When the DSP 15 detects an interrupt due to the interrupt signal INT, it first interrupts the main routine process and starts an interrupt start process S1 (processing time t _S ).

In the interrupt start processing S1, the DSP
15 is the DS at the time of interruption of the main routine processing.
The state of the general-purpose register provided in P15 (the value in the general-purpose register) is saved in a predetermined register (save register). As a result, the DSP 15 switches from the main routine processing to the interrupt routine processing IP1 (processing time t _IP × 4).
Move to

Next, in the interruption routine process IP1, DSP 15, after decoding by the main routine processing MP1 not shown immediately before time T _1, reads the decoding result of the input data DTI accumulated stored in the buffer memory, the processing Data output circuit 16 as data DTP
To supply. In the interrupt routine process IP1, the DSP 15 outputs the data output circuit 16 during the period of four cycles of the clock signal LRCK, that is, (set value of the number of interrupt reductions) × (one cycle of the clock signal LRCK).
And outputs to the data output circuit 16 the processing data DTP of the data amount to be output to the outside of the audio data processing device.

When the above-described interrupt routine process IP1 is completed, the DSP 15 executes an interrupt end process R1 (processing time t _R ). In the above-described interrupt end processing R1,
The DSP 15 restores the value of the general-purpose register saved in a predetermined register (save register) or the like in the interrupt start processing S1. As a result, the DSP 15 restores the state at the time of interruption of the main routine processing, and switches from the interrupt routine processing IP1 to the main routine processing MP2 (processing time t _MP
× 4 + t _RM ).

Thereafter, at time T ₂ when four cycles of the clock signal LRCK have elapsed from time T ₁ , the DSP 15 again outputs an interrupt due to the interrupt signal INT to the counter 13.
Until the data is output to the DSP 15, the main routine processing MP2 such as reading of the input data DTI and decoding of the input data DTI is performed. And in the same way,
Time T ₂ or later, interrupt processing (interrupt start processing, the interrupt routine processing and interrupt termination processing) repeated and the main routine processing.

As shown in FIG. 3,
-The operation of the DSP 15 in the audio data processing device
And during the period of four cycles of the clock signal LRCK (see FIG.
The time ｛(t shown in FIG._S+ T_IP+ T_R+ T_MP) × 4｝)
The DSP 15 executes the interrupt processing (interrupt start processing, interrupt
The time required for the chin process and the interrupt end process) is t _S
+ (T_IP× 4) + t_RIt is.

Therefore, in the audio data processing device shown in FIG. 2, during four periods of the clock signal LRCK, the DSP 15 operates as follows: ｛(t _S + t _IP + t _R + t _MP )
× 4｝-｛t _S + (t _IP × 4) + t _R ｝ = ｛t _MP × 4 +
(T _S + t _R ) × 3｝ can be spent on the main routine processing. That is, as compared with the conventional audio data processing apparatus shown in FIG. 6, the time for performing the main routine processing can be made longer by the time t _RM shown in FIG. 3 corresponding to (t _S + t _R ) × 3.

For example, if the operating frequency of the DSP 15 is 108
MHz, and the frequency of the clock signal LRCK is 48 kHz, the operation frequency (108 MHz) of the DSP 15 is 148 for one interrupt start process and one interrupt end process.
Assume that it consumes cycles. At this time, one cycle of the frequency (48 kHz) of the clock signal LRCK is D
Since it is 2250 cycles of the operating frequency of SP15,
In one cycle of the frequency of the clock signal LRCK,
In one interrupt start process and one interrupt end process,
148/2250 = approximately 7% of the time will be consumed.

On the other hand, when the number of interrupts is reduced to 1/4 as shown in FIG. 3, the number of interrupts is one in four cycles of the frequency of the clock signal LRCK, and one cycle of the frequency of the clock signal LRCK. 1
The time consumed in interrupt start processing and interrupt end processing per time can be set to 148 / (2250 × 4) = about 1.6%. The DSP 15 has 148 cycles of the operating frequency (108 MHz) of the DSP 15 × 3 = 4.
The main routine process can be performed for a longer time of 44 μs.

As described above in detail, according to the first embodiment, the CPU 11 sets the number of interrupts of the interrupt signal INT with respect to the number of interrupts of the clock signal LRCK in the register 12 to reduce the number of interrupts.
The number of interrupts of the clock signal LRCK is counted, and the count of the number of interrupts of the clock signal LRCK is compared with the number of interrupts set in the register 12, and the number of interrupts is reduced based on the comparison result. An interrupt signal INT is generated and output to the DSP 15. The DSP 15 executes an interrupt process in response to the interrupt by the interrupt signal INT, and outputs a decoding result of the input data DTI supplied from the outside to the data input / output circuit 5.

As a result, the DSP 15 executes the interrupt process for each interrupt by the interrupt signal INT whose number of interrupts has been reduced, thereby reducing the number of times the DSP 15 executes the interrupt process, and starting and ending the interrupt per unit time. The number of executions of the process can be reduced, and the time required for the unit time can be shortened. Therefore, the time for the DSP 15 to perform the main routine processing per unit time can be increased, and the resources of the DSP 15 can be effectively used.

Further, since the CPU 11 can set an arbitrary interrupt reduction number in the register 12 by the interrupt reduction number setting signal SET, the interrupt reduction according to the resources (processing amount of the main routine processing) required in the DSP 15 can be performed. The number can be set, and the resources of the DSP 15 can be used effectively.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 11 is a block diagram illustrating a configuration example of an audio data processing device to which the data processing device according to the embodiment is applied. FIG.
The audio data processing device shown in FIG. 1 accumulates input data DTI ′, which is audio data supplied from the outside, and converts the input data DTI ′ into a predetermined size in response to an interrupt signal INT generated based on a clock signal LRCK. The input data is subjected to predetermined processing and output to an outside of the audio data processing apparatus, for example, a DAC (not shown).

In FIG. 4, blocks having the same functions as the blocks shown in FIG. 2 are denoted by the same reference numerals, and redundant description will be omitted. In addition, blocks that are not the same as those illustrated in FIG. 2 but have corresponding functions are denoted by the same reference numerals.

In FIG. 4, reference numeral 31 denotes a data input circuit, which includes a not-shown FIFO (not shown) provided in accordance with a clock signal LRCK supplied from a clock supply circuit 14 '.
Input data DTI 'supplied from an external device at a certain timing to a buffer memory such as O is accumulated and stored as input data DTI. The data input circuit 31 outputs the data stored in the buffer memory to the DSP 15 'as input data DTI in accordance with the clock signal LRCK or the like supplied from the clock supply circuit 14'. here,
The input data DTI and DTI 'are composed of a plurality of compressed bit strings in a predetermined format, and the plurality of bit strings are bit strings of a predetermined size.

The clock supply circuit 14 'supplies the clock signal LRCK to the data input circuit 31. Also,
The clock supply circuit 14 'is connected to the clock signal LRCK.
Is output to the data output circuit 16, and the data output circuit 16
Is the processing data DT according to the clock signal LRCK.
Input data DTI supplied from DSP 15 'as P
And outputs the decoding result (decoded data). Further, the clock supply circuit 14 ′ supplies the clock signal LRCK to the counter 13 as an interrupt signal for inputting the input data DTI stored in the data input circuit 31.

The DSP 15 'responds to the interrupt signal INT supplied from the counter 13 by reducing the number of interrupts.
Input data DTI stored in data input circuit 31
And decodes the input data DTI according to a predetermined algorithm. And DSP15
Supplies the decoding result (decoded data) of the input data DTI to the data output circuit 16 as processing data DTP sequentially. The DSP 15 'refers to the set value of the interrupt reduction number set in the register 12 via the interrupt reduction number reference signal NREF, and according to the set value of the interrupt reduction number, the data input circuit 31 A predetermined process is performed on the input data DTI input from.

Next, the operation will be described. In the following description, it is assumed that when the clock signal LRCK rises (changes from “L” to “H”), an interrupt by the clock signal LRCK from the clock supply circuit 14 ′ occurs. Further, the CPU 11 sets the number of interrupt reductions in the register 12 in advance by the interrupt reduction number setting signal SET, and sets the set value of the interrupt reduction number to N (N is an arbitrary number).

First, when the data processing operation is started by the audio data processing device, the clock supply circuit 1
4 ′, a clock signal LRCK having a predetermined cycle is supplied to the counter 13 and the data input circuit 31. Also,
The data input circuit 31 sequentially stores input data DTI ′ supplied from the outside at a predetermined timing in a buffer memory such as a FIFO provided therein.

The counter 13 to which the clock signal LRCK is supplied detects an interruption by the clock signal LRCK, and every time an interruption is detected, the count value is incremented by 1 to count the number of interruptions of the clock signal LRCK. The counter 13 refers to the set value of the interrupt reduction number set in the register 12 and compares the set value of the interrupt reduction number with the count value of the interrupt count. As a result of the comparison, when the set value of the interrupt reduction number is not equal to the count value of the interrupt count, the counter 13 continues to detect and count the interrupt by the clock signal LRCK.

On the other hand, as a result of the comparison, when the set value of the reduced number of interrupts is equal to the counted value of the number of interrupts,
The counter 13 outputs an interrupt signal INT to the DSP 15 ', and resets the count value of the number of interrupts to "0".
That is, the counter 13 outputs the clock signal LRCK.
, An interrupt signal INT is output to the DSP 15 'every N cycles.

When the DSP 15 'detects an interrupt due to the interrupt signal INT output from the counter 13, the DSP 15' interrupts the normal processing (main routine processing) and executes the interrupt processing (interrupt start processing, interrupt routine processing). Processing and interrupt end processing) are started. In the interrupt process, the DSP 15 'first saves the value of a general-purpose register provided inside the DSP 15' when the main routine process is interrupted to a predetermined register (save register) or the like (interrupt start process).

Next, the DSP 15 'operates the data input circuit 3
The input data DTI sequentially accumulated and stored in step 1 is read (interrupt routine processing). When the interrupt routine processing is completed, the DSP 15 'restores the value of the general-purpose register saved in a predetermined register (save register) or the like in the interrupt start processing, and restores the value of the main routine processing before performing the interrupt processing. The state is restored (interruption end processing), and the operation of the main routine processing is restarted.

Regardless of whether or not the interrupt processing operation is being performed, the counter 13 detects an interrupt by the clock signal LRCK and counts the number of interrupts. When the count value becomes equal again, the counter 13 outputs an interrupt signal INT to the DSP 15 ′ and resets the count value of the number of interrupts to “0”. When the DSP 15 'detects an interrupt due to the interrupt signal INT again, the DSP 15' interrupts the main routine process and performs the interrupt process.

As described above, according to the second embodiment, the CPU 11 sets the number of interrupts of the interrupt signal INT relative to the number of interrupts of the clock signal LRCK in the register 12. In addition, the counter 13
Counts the number of interrupts of the clock signal LRCK, compares the counted number with the reduced number of interrupts set in the register 12, generates an interrupt signal INT in which the number of interrupts is reduced based on the comparison result, and sends the signal to the DSP 15 '. Output. Then, the DSP 15 ′ executes an interrupt process for inputting the input data DTI to be decoded from the data input circuit 31 in response to the interrupt by the interrupt signal INT.

As a result, the DSP 15 'executes the interrupt process for each interrupt by the interrupt signal INT in which the number of interrupts is reduced, thereby reducing the number of executions of the interrupt process in the DSP 15', and the interrupt start process per unit time. In addition, the number of executions of the interrupt end process can be reduced, and the time required for the unit time can be reduced. Therefore, the time for the DSP 15 'to perform the main routine processing per unit time can be increased,
The resources of the DSP 15 'can be effectively used.

Further, since the CPU 11 can set an arbitrary interrupt reduction number in the register 12 by the interrupt reduction number setting signal SET, the interrupts can be set in accordance with the resources (processing amount of the main routine processing) required in the DSP 15 '. The number of reductions can be set, and the resources of the DSP 15 ′ can be used effectively.

In the first and second embodiments, when the counter 13 detects the rising edge of the clock signal LRCK and counts the number of interrupts, the count is incremented by one. However, the set value of the interrupt reduction number may be set in the counter 13 as an initial value, and the count value may be decremented by one each time an interrupt due to the clock signal LRCK is detected. In this case, when the count value becomes “0”, the counter 13 outputs an interrupt by the interrupt signal INT.

The above embodiments are merely examples of implementation of the present invention, and the technical scope of the present invention should not be interpreted in a limited manner. It is. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features. (Supplementary Note 1) A setting circuit for setting a set value and a first interrupt signal are input, and the second interrupt number is smaller than the interrupt number of the first interrupt signal according to the set value set by the setting circuit. An interrupt signal control circuit that generates and outputs an interrupt signal of the type described above; a data input process for performing a predetermined process according to the second interrupt signal output from the interrupt signal control circuit; and a predetermined process And a data processing circuit for performing at least one of an output process of the data subjected to the processing.

(Supplementary Note 2) The interrupt signal control circuit detects an interrupt due to the first interrupt signal, and based on the detected number of interrupts of the first interrupt signal and the set value, generates the second interrupt signal. 2. The data processing device according to claim 1, wherein the data processing device generates an interrupt signal. (Supplementary Note 3) The set value is a ratio of the number of interrupts of the first interrupt signal to the number of interrupts of the second interrupt signal, and the interrupt signal control circuit determines the detected first interrupt signal.
3. The data processing apparatus according to claim 2, wherein the second interrupt signal for interrupting the data processing circuit is generated when the number of interrupts of the interrupt signal and the set value match.

(Supplementary Note 4) The interrupt signal control circuit supplies information on the set value in response to a request from the data processing circuit, and the data processing circuit supplies the information supplied from the interrupt signal control circuit. 4. The data processing device according to claim 3, wherein a predetermined process is performed on the data based on information on a set value.

(Supplementary Note 5) The interrupt signal control circuit includes a storage circuit that stores a set value set by the setting circuit, an interrupt caused by the first interrupt signal, and the detected first interrupt signal. And a counting circuit for generating the second interrupt signal based on the counted value of the number of interrupts and the set value stored in the storage circuit. 2. The data processing device according to 1.

(Supplementary Note 6) The counting circuit includes a counter circuit that increments a count value each time an interrupt due to the first interrupt signal is detected, and the count value of the counter circuit is stored in the storage circuit. 5. The data processing apparatus according to claim 4, wherein when the set value is matched, a second interrupt signal for interrupting the data processing circuit is generated, and the count value is reset. (Supplementary Note 7) The counting circuit includes a counter circuit that decrements a count value each time an interrupt due to the first interrupt signal is detected, and interrupts the data processing circuit when the count value of the counter circuit is 0. The data processing device according to claim 4, wherein the second interrupt signal is generated, and the count value is set to a set value stored in the storage circuit.

(Supplementary Note 8) The data processing apparatus according to supplementary note 1, wherein the data is audio data. (Supplementary note 9) The supplementary note 8, wherein the first interrupt signal is a clock signal for outputting data subjected to predetermined processing by the data processing circuit to the outside of the data processing device. Data processing device.

(Supplementary note 10) The data processing device according to supplementary note 9, wherein the data processing circuit is a digital signal processor. (Supplementary note 11) The supplementary note 10, wherein the clock signal is a clock signal for outputting data subjected to predetermined processing by the data processing circuit into left channel data and right channel data. A data processing device according to claim 1.

(Supplementary Note 12) A set value is set, a first interrupt signal is input, and a first interrupt signal is input according to the set value.
The number of interrupts is smaller than the number of interrupts
And performs at least one of a data input process for performing a predetermined process and a data output process for performing the predetermined process in accordance with the generated second interrupt signal. A data processing control method comprising:

(Supplementary Note 13) An interrupt due to the first interrupt signal is detected, and when the detected interrupt count of the first interrupt signal matches the set value, the data processing circuit is interrupted. 13. The data processing control method according to supplementary note 12, wherein an interrupt signal of No. 2 is generated. (Supplementary Note 14) The set value set above is stored and the first set value is stored.
13. The method according to claim 12, wherein an interrupt by the interrupt signal is detected, the number of interrupts is counted, and the second interrupt signal is generated based on the counted value of the number of interrupts and the stored set value. Data processing control method.

(Supplementary note 15) The data processing control method according to supplementary note 12, wherein the data is audio data. (Supplementary note 16) The data processing control method according to supplementary note 15, wherein the first interrupt signal is a clock signal for outputting the data subjected to the predetermined processing to the outside. (Supplementary note 17) The data according to Supplementary note 16, wherein the clock signal is a clock signal for outputting the data that has been subjected to the predetermined processing as left-channel data and right-channel data. Processing control method.

[0088]

As described above, according to the present invention,
A setting circuit for setting a set value, an interrupt signal control circuit for generating and outputting a second interrupt signal having a smaller number of interrupts than the number of interrupts of the input first interrupt signal according to the set value, Data for performing at least one of data input processing for performing predetermined processing and data output processing for performing predetermined processing in accordance with the second interrupt signal output from the interrupt signal control circuit A processing circuit. As a result, the number of times that the data processing circuit executes the interrupt processing per unit time can be reduced, the ratio of the time required for the interrupt processing per unit time can be reduced, and the time required for the data processing circuit to perform the normal processing can be reduced. The percentage can be higher. Therefore,
Resources of the data processing circuit in the data processing device can be effectively utilized.

Also, since a setting circuit for setting a set value is provided, the number of interrupts of the second interrupt signal can be set according to resources used in the data processing circuit per unit time, and The resources of the processing circuit can be effectively used.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing a configuration example of a data processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of an audio data processing device to which the data processing device according to the first embodiment is applied.

FIG. 3 is a diagram illustrating an operation example of a DSP in an audio data processing device to which the data processing device according to the first embodiment is applied.

FIG. 4 is a block diagram illustrating a configuration example of an audio data processing device to which a data processing device according to a second embodiment is applied.

FIG. 5 is a block diagram showing a configuration of a conventional audio data processing device.

FIG. 6 shows a DS in a conventional audio data processing device.
It is a figure showing operation of P.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Controller 2 Interrupt signal generation circuit 3 Interrupt signal control circuit 4 Data processing circuit 5 Data input / output circuit 11 CPU 12 Register 13 Counter 14, 14 'Clock supply circuit 15, 15' DSP 16 Output circuit 31 Input circuit INT Interrupt signal

Continuation of the front page F term (reference) 5B098 AA05 BA01 BA19 BB02 BB03 FF02 FF03

Claims (5)

[Claims] 1. A setting circuit for setting a set value, a first interrupt signal being input, and a first interrupt signal having a smaller number of interrupts than the number of interrupts of the first interrupt signal according to the set value set by the setting circuit. An interrupt signal control circuit that generates and outputs an interrupt signal of the second type; a data input process for performing a predetermined process in accordance with the second interrupt signal output from the interrupt signal control circuit; A data processing circuit for performing at least one of output processing of the processed data. 2. The interrupt signal control circuit detects an interrupt due to the first interrupt signal, and detects the second interrupt signal based on the detected interrupt count of the first interrupt signal and the set value. The data processing device according to claim 1, wherein 3. The setting value is a ratio of the number of interrupts of the first interrupt signal to the number of interrupts of the second interrupt signal. 3. The data processing apparatus according to claim 2, wherein the second interrupt signal for interrupting the data processing circuit is generated when the number of interrupts matches the set value. 4. An interrupt signal control circuit comprising: a storage circuit for storing a set value set by the setting circuit; an interrupt caused by the first interrupt signal; and an interrupt of the detected first interrupt signal. 2. The apparatus according to claim 1, further comprising: a counting circuit that counts the number of times and generates the second interrupt signal based on the count value of the number of times of interrupt and the set value stored in the storage circuit. The data processing device according to claim 1. 5. Setting a set value, inputting a first interrupt signal, and generating a second interrupt signal having a smaller number of interrupts than the number of interrupts of the first interrupt signal according to the set set value; Data processing for performing at least one of data input processing for performing predetermined processing and data output processing for performing predetermined processing in accordance with the generated second interrupt signal. Control method.