JP2008072164A - Transmission device, electric circuit and power consumption stabilizing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent variation in power consumption in a transmission device for outputting data to be outputted during a data valid period when the data exist and outputting dummy data during a data invalid period when the data do not exist. <P>SOLUTION: A selector 16 in the transmission device 30 selects data D1 during the data valid period, and selects dummy data 5 generated by a dummy data generating circuit 17 during the data invalid period. The dummy data generating circuit 17 generates the dummy data having a small difference in a data change rate between the dummy data and data to be outputted during the data valid data. For example, the circuit generates the dummy data 5 having a data change rate of 50% or the dummy data 5 having a data change rate corresponding to the data change rate of the data D1 immediately before the data invalid period. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a transmission device that outputs the data in a data valid period in which data to be output exists, and outputs arbitrary data in a data invalid period that does not exist, and more particularly to output data in the transmission device The present invention relates to a current consumption stabilization technique that can prevent the current consumed by the current from fluctuating much between a data valid period and a data invalid period.

  SPI-3 (System 3) specified by OIF (Optical Internetworking Forum) as an interface that can output the above data during the data valid period and any data such as “0” data during the data invalid period Packet Interface Level 3) has been conventionally known and has been adopted as a packet interface for many devices such as ASSP (Application Specific Standard Product).

  FIG. 10 is a block diagram showing a configuration example of a conventional general transmission device 10 and reception device 20 using SPI-3.

[Configuration of transmitting device 10]
First, the configuration of the transmission device 10 will be described. Referring to FIG. 10, a transmitting device 10 that transfers data using SPI-3 includes a T / RSX (T: Transmit, RSX: Receive Start of Transfer signal) generation circuit 11 and a T / RENB (RENB: Receive Read). An enable signal) generation circuit 12, a switching control circuit 15, a selector 16, a “0” output circuit 101, a parity operation circuit 103, and a parity output circuit 104 are provided. Further, the transmitting device 10 receives a packet identification for identifying a 32-bit data D1 (an address is added immediately before the data D1) and a valid portion of the data D1 from a packet generation circuit (not shown). Signal 102 is input. Next, each circuit in the transmission device 10 will be described.

T / RSX generation circuit 11: When the T / RSX generation circuit 11 detects the address existing immediately before the data D1 based on the packet identification signal 102, the T / RSX signal S2 is set to the high level (“Hi”). When the head portion of the data D1 is detected, the T / RSX signal S2 is set to the low level (“Lo”).

T / RENB generation circuit 12: When the T / RENB generation circuit 12 detects the beginning of the valid part of the data D1 based on the packet identification signal 102, the T / RENB signal S3 is set to “Lo”, and the beginning of the invalid part Is detected, the T / RENB signal S3 is set to “Hi”.

“0” output circuit 101: The “0” output circuit 101 outputs 32-bit all “0” parallel data as data to be output from the transmitting device 10 during the invalid period of the data D1. Not specified by OIF, but for many devices. When the data D1 is invalid, “0” data is output as meaningless data.

Switching control circuit 15: The switching control circuit 15 outputs data D1 to the selector 16 based on the T / RSX signal S2 and the T / RENB signal S3, or is output from the “0” output circuit 101. The transfer / interruption signal S8 is output to instruct whether to output the “0” data. More specifically, the output of the data D1 is instructed by setting the transfer / interrupt signal S8 to “Hi” at the rising edge of the T / RSX signal S2, and the transfer / interrupt signal S8 is set at the rising edge of the T / RENB signal S3. Instructing the output of “0” data by setting “Lo”.

Selector 16: The selector 16 selects the data D1 when the transfer / interrupt signal S8 from the switching control circuit 15 is “Hi” and outputs it to the data bus DB, and when it is “Lo”, the “0” output circuit. The “0” data output from 101 is selected and output to the data bus DB.

Parity operation circuit 103: The parity operation circuit 103 receives the data D1 and the packet identification signal 102, and “1” included in the 32-bit data D1 while the packet identification signal 102 is “Hi”. Is determined to be odd or even, and the determination result is output as a parity operation result 108.

Parity output circuit 104: The parity output circuit 104 receives the parity operation result 108 and the transfer / interrupt signal S8 as input, and performs parity during the period when the transfer / interrupt signal S8 is “Hi” (period in which transfer is instructed). When the operation result 108 indicates an odd number, “0” is output as the parity bit 107, and when the parity operation result 108 indicates an even number, “1” is output as the parity bit 107.

[Reception device 20]
Next, the configuration of the receiving device 20 will be described. The receiving device 20 is a device that receives data using SPI-3, and includes a T / RSX receiving circuit 13, a T / RENB receiving circuit 14, a data processing circuit 18, and a detecting circuit 105.

T / RSX reception circuit 13: The T / RSX reception circuit 13 receives the T / RSX signal S2 transmitted from the transmission device 10 and outputs the T / RSX signal S7.

T / RENB reception circuit 14: The T / RENB reception circuit 14 receives the T / RENB signal S3 and outputs the T / RENB signal S6.

Data processing circuit 18: The data processing circuit 18 outputs data D2 and a packet identification signal 110 according to the states of the T / RENB signal S6 and the T / RSX signal S7. More specifically, after the T / RSX signal S7 rises, the output of the data D2 starts at the timing when the T / RENB signal S6 falls, and then the data D2 starts at the timing when the T / RENB signal S6 rises. Stop output. Further, while the data D2 is being output, the packet identification signal 110 is set in a state indicating that data exists.

-Detection circuit 105: The detection circuit 105 uses the parity bit 107 while the T / RENB signal S6 is "Lo" to determine whether or not there is an error in the data D1 sent via the data bus DB. Validate.

[Description of operation]
Next, operations of the transmitting device 10 and the receiving device 20 shown in FIG. 10 will be described with reference to the time chart of FIG.

  Data D1 and a packet identification signal 102 are input from the outside to the transmission device 10, and the data D1 is input to the selector 16 and the parity calculation circuit 103. The packet identification signal 102 includes the T / RSX generation circuit 11, T The signal is input to the / RENB generation circuit 12 and the parity operation circuit 103.

  When the T / RSX generation circuit 11 detects the address existing immediately before the data D1 based on the packet identification signal 102 at time t1, the T / RSX signal S2 is set to “Hi”, and then the data D1 at time t2. When the head portion is detected, the T / RSX signal S2 is set to “Lo”. Further, when the T / RENB generation circuit 12 detects the leading portion of the data D1 based on the packet identification signal 102 at time t2, the T / RENB signal S3 is set to “Lo”, and the invalid portion of the data is detected at time t3. Then, the T / RENB signal S3 is set to “Hi”.

  The switching control circuit 15 sets the transfer / suspend signal S8 to “Hi” when the T / RSX signal S2 becomes “Hi” at time t1, and transfers / suspends when the T / RENB signal S3 becomes “Hi” at time t3. Set signal S8 to “Lo”.

  The selector 16 outputs the address and data D1 to the data bus DB when the transfer / interrupt signal S8 becomes “Hi” at time t1, and outputs “0” when the transfer / interrupt signal S8 becomes “Lo” at time t3. The “0” data output from 101 is output to the data bus DB.

  While the packet identification signal 102 indicates that data exists, the parity calculation circuit 103 determines whether the number of “1” s in the data D1 is odd or even, and outputs the determination result as the parity calculation result 108 To do. The parity output circuit 104 receives the parity operation result 108 and the transfer / interruption signal S8 as input, and when the transfer operation / interruption signal S8 is “Hi”, the parity operation result 108 indicates an odd number as the parity bit 107. When “0” is output and the parity calculation result 108 indicates an even number, “1” is output as the parity bit 107.

  The T / RSX receiving circuit 13 in the receiving device 20 receives the T / RSX signal S2 and outputs the T / RSX signal S7, and the T / RENB receiving circuit 14 receives the T / RENB signal S3 and performs T / RENB signal S6 is output.

  When the T / RENB signal S6 becomes “Lo”, the data processing circuit 18 extracts the data D1 sent via the data bus DB and outputs it as data D2, and sets the packet identification signal 110 to “Hi”. To do.

  The detection circuit 105 verifies whether or not there is an error in the data D1 based on the data D1 and the parity bit 107 sent via the data bus DB.

  The above is the operation of the conventional general transmission device 10 and reception device 20 using SPI-3.

  On the other hand, a technology that does not use SPI-3, but that outputs input data when there is input data and outputs dummy data with parity when there is no input data has been known. (For example, refer to Patent Document 1). The conventional technique described in Patent Document 1 includes a plurality of input circuits I1 to IN, a common processing circuit, and a plurality of output circuits O1 to ON. Each input circuit I1 to IN receives data with parity to which a parity bit is added, and each input circuit I1 to IN outputs data to the common processing circuit when data with parity is input. When no data with parity is input, dummy data with parity is output to the common processing circuit. The common processing circuit processes data output from the input circuits I1 to IN and outputs the processed data to the output circuits O1 to ON. Each output circuit O1 to ON performs a parity check on the data (data with parity or dummy data with parity) output from the common processing circuit, and issues a warning when a data error is detected.

JP-A-1-241949

  By the way, when data transfer is performed using SPI-3, current is consumed to change the data D1 to “Lo” and “Hi” during the data valid period. However, since the state is fixed to “0” during the data invalid period, the current consumption is reduced. Thus, when data transfer is performed using SPI-3, the current consumed at the time of switching between the data valid period and the data invalid period greatly fluctuates (fluctuates by about 1 A). The power supply circuit that supplies the operating voltage to the transmitting device adjusts the current to keep the output voltage constant, but cannot follow the sudden fluctuations in the current consumption that occur when the data valid period and data invalid period change. The output voltage may fluctuate. As shown in FIG. 12, when a device having a digital circuit, an analog circuit, or SPI-3 is connected to one power supply circuit, an analog circuit or the like tends to be easily affected by voltage fluctuations. May cause.

  Patent Document 1 describes that dummy data is output during a data invalid period, but the conventional technique described in Patent Document 1 is not intended to reduce fluctuations in current consumption. Therefore, it is not described at all what kind of dummy data can be output to reduce fluctuations in current consumption.

(Object of invention)
Accordingly, an object of the present invention is to prevent the current consumed by the transmitting device from fluctuating greatly when the data valid period and the data invalid period are switched.

The first transmitting device according to the present invention is:
A transmission device that outputs the data in a data valid period in which data to be output exists and outputs dummy data in a data invalid period that does not exist,
As the dummy data, a dummy data generation circuit that generates dummy data having a small difference in data change rate from data output in a data valid period is provided.

A second transmitting device according to the present invention is the first transmitting device,
The data change rate of the dummy data generated by the dummy data generation circuit is a fixed value.

A third transmitting device according to the present invention is the second transmitting device,
A data change rate of dummy data generated by the dummy data generation circuit is approximately 50%.

A fourth transmission device according to the present invention is the first transmission device,
The data change rate of the dummy data generated by the dummy data generation circuit is dynamically changed.

A fifth transmitting device according to the present invention is the fourth transmitting device,
The dummy data generation circuit generates dummy data having a data change rate corresponding to a data change rate of data output immediately before a data invalid period.

A sixth transmitting device according to the present invention is the fifth transmitting device,
A change rate detection circuit for detecting a data change rate of data output immediately before the data invalid period, and
The dummy data generation circuit generates dummy data according to the data change rate detected by the change rate detection circuit.

A seventh transmitting device according to the present invention is the sixth transmitting device,
The rate of change detection circuit is
A counter that is incremented at the rise and fall of the data and is reset every predetermined time;
And a control circuit for inputting a count value of the counter at the start of a data invalid period and obtaining a data change rate based on the input count value.

An eighth transmitting device according to the present invention is the sixth transmitting device,
The rate of change detection circuit is
A counter that is incremented when the data rises and falls;
A shift register having a predetermined number of stages for capturing and shifting the count value of the counter according to a clock signal;
And a control circuit that calculates a data change rate based on count values held in an input stage and an output stage of the shift register at the start of a data invalid period.

A ninth transmission device according to the present invention is any one of the first to eighth transmission devices,
A parity output circuit is provided that outputs a parity bit for the data during a data valid period and outputs a parity bit for the dummy data during a data invalid period.

The electrical circuit according to the present invention is
A power circuit;
The transmission device according to any one of claims 1 to 9 connected to the power supply circuit;
And an analog circuit connected to the power supply circuit.

The first current consumption stabilization method according to the present invention includes:
A method for stabilizing current consumption in a transmitting device that outputs the data in a data valid period in which data to be output exists and outputs dummy data in a non-existent data invalid period,
As the dummy data, dummy data having a small difference in data change rate from data output in a data valid period is generated.

A second consumption current stabilization method according to the present invention is the first consumption current stabilization method,
A method for stabilizing current consumption, characterized in that the data change rate of dummy data is a fixed value.

A third current consumption stabilization method according to the present invention is the first current consumption stabilization method,
The data change rate of the dummy data is dynamically changed.

A fourth consumption current stabilization method according to the present invention is the third consumption current stabilization method,
Dummy data having a data change rate corresponding to the data change rate of data output immediately before the data invalid period is generated.

[Action]
The transmitting device outputs the data in a data valid period in which data exists, and outputs dummy data in a data invalid period in which no data exists. This dummy data is generated by a dummy data generation circuit, and the dummy data generation circuit generates dummy data having a small difference in data change rate from the data output in the data valid period.

  The dummy data generated by the dummy data generation circuit may have a fixed data change rate or may change dynamically. When the data change rate is a fixed value, the data change rate is about 50%. When the data change rate is dynamically changed, the data change rate is set according to the data change rate of the data output immediately before the data invalid period.

  According to the present invention, when the data valid period and the data invalid period are switched, the current consumed by the transmitting device can be prevented from greatly fluctuating. This is because dummy data having a small difference in data change rate from data output in the data valid period is output in the data invalid period.

  Next, the best mode for carrying out the invention will be described in detail with reference to the drawings.

[First Embodiment]
Referring to FIG. 1, the first embodiment of the present invention comprises a transmitting device 30 for transferring data using SPI-3 and a receiving device 40 for receiving data using SPI-3. Has been.

  The transmission device 30 includes a dummy data generation circuit 17 instead of the “0” output circuit 101, a parity operation circuit 103a instead of the parity operation circuit 103, and a parity output circuit 104. The transmission device 30 shown in FIG. 10 is different from the transmission device 30 in that the parity output circuit 104a is provided.

  The dummy data generation circuit 17 generates dummy data 5. The dummy data 5 is parallel data having a 32-bit configuration. In this embodiment, the dummy data 5 is generated so that the data change rate H of the data at each bit position is 50%. The data change rate H of data indicates the maximum number of times that the data can change state per unit time T (change from “Lo” to “Hi” and change from “Hi” to “Lo”). This is the ratio of the number of state changes per unit time T of data to the number of changes. Since the data state can be changed once per clock, the data change rate H can be expressed by the following equation (1), for example.

  Data change rate H = (the total value of the number of times the data state has changed from “Lo” to “Hi” and the number of times the data state has changed from “Hi” to “Lo” during N clocks) / N × 100 (1) )

  Therefore, the data change rate of data whose state changes every clock is 100%. Further, the data change rate of data whose state changes N / 2 times during N clocks is 50%. FIG. 2 shows examples of dummy data with data change rates of 100%, 50%, and 25%.

  When the packet identification signal 102 is “Hi”, the parity calculation circuit 103a outputs a parity calculation result 108 indicating whether or not the number of “1” included in the data D1 is an odd number, and the packet identification signal 102 is In the case of “Lo”, a parity calculation result 108 indicating whether or not the number of “1” included in the 32-bit dummy data 5 is an odd number is output.

  The parity output circuit 104a outputs “0” as the parity bit 107 when the parity calculation result 108 indicates an odd number, and sets “1” as the parity bit 107 when the parity calculation result 108 indicates an even number. Output.

  The receiving device 40 is different from the receiving device 20 shown in FIG. 10 in that it includes a detection circuit 105a instead of the detection circuit 105.

  The detection circuit 105a always uses the parity bit 107 to verify whether there is an error in the data D1 and dummy data sent via the data bus DB.

[Description of Operation of First Embodiment]
Next, the operation of the present embodiment will be described with reference to the time chart of FIG.

  Data D1 and a packet identification signal 102 are input from the outside to the transmission device 30, and the data D1 is input to the selector 16 and the parity calculation circuit 103a. The packet identification signal 102 includes the T / RSX generation circuit 11, the T / RSX Input to the RENB generation circuit 12 and the parity operation circuit 103a.

  When the T / RSX generation circuit 11 detects the address existing immediately before the data D1 based on the packet identification signal 102 at time t31, the T / RSX signal S2 is set to “Hi”, and then at time t32, the data D1 When the head portion is detected, the T / RSX signal S2 is set to “Lo”. Further, when the T / RENB generation circuit 12 detects the leading portion of the data D1 based on the packet identification signal 102 at time t32, the T / RENB signal S3 is set to “Lo”, and then the invalid portion is detected at time t33. Then, the T / RENB signal S3 is set to “Hi”.

  When the T / RSX signal S2 becomes “Hi” at time t31, the switching control circuit 15 sets the transfer / interrupt signal S8 to “Hi” to indicate that the data is valid, and at time t33, the T / RENB signal S3 When “Hi” becomes “Hi”, the transfer / interrupt signal S8 is set to “Lo” to indicate the data invalid period.

  The selector 16 outputs the address and data D1 to the data bus DB when the transfer / interrupt signal S8 becomes “Hi” at time t31, and the dummy data generation circuit when the transfer / interrupt signal S8 becomes “Lo” at time t33. The dummy data 5 generated by 17 is output to each bit of the data bus DB. In this embodiment, as described above, dummy data 5 having a data change rate H of 50% is output. Note that the data transferred from the transmitting device 30 to the receiving device 40 when the T / RENB signal S3 is “Hi” is not stipulated by the OFI, and the data processing circuit 18 in the receiving device 40 When the signal S3 is “Hi” (when the T / RENB signal S6 is “Hi”), the data sent via the data bus DB is ignored, so what data is used as the dummy data 5. However, it does not affect the output data D2. As described above, in the data invalid period (time t33 to t34), the dummy data 5 with the data change rate of 50% is output, thereby suppressing fluctuations in power consumption when switching between the data valid period and the data invalid period. Can do.

  While the packet identification signal 102 indicates that data exists (time t31 to t33), the parity calculation circuit 103a indicates a parity calculation result 108 indicating whether the number of “1” s in the data D1 is odd or even. Is output. Further, while the packet identification signal 102 indicates that no data exists (time t33 to t34), the parity calculation result 108 indicating whether the number of “1” of the dummy data 5 is odd or even is output.

  The parity output circuit 104a receives the parity calculation result 108 as an input, outputs “0” as the parity bit 107 when the parity calculation result 108 indicates an odd number, and when the parity calculation result 108 indicates an even number, “1” is output as the parity bit 107. Thus, in the present embodiment, the parity bit 107 is transmitted from the transmitting device 30 to the receiving device 40 not only during the data valid period but also during the data invalid period, and the parity check is performed in the detection circuit 105a of the receiving device 40. Is called.

[Effect of the first embodiment]
According to the present embodiment, it is possible to prevent the current consumed by the transmission device 30 from greatly fluctuating when the data valid period and the data invalid period are switched. This is because the dummy signal generation circuit 17 that generates dummy data having a small difference between the data change rate and the data output in the data valid period is provided as dummy data output in the data invalid period.

  Further, the present embodiment includes a parity output circuit 104a that outputs the parity bit 107 for the data D1 in the data valid period and outputs the parity bit 107 for the dummy data 5 in the data invalid period. It becomes possible to detect a failure even in a period.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. In the present embodiment, the data change rate of data output from the transmission device immediately before the data invalid period is actually detected, and dummy data corresponding to the detected data change rate is output from the transmission device during the data invalid period. It is characterized by.

  Referring to FIG. 4, the present embodiment includes a transmitting device 50 that transmits data using SPI-3 and a receiving device 60 that receives data using SPI-3.

  The receiving device 60 of this embodiment is different from the receiving device 20 of the first embodiment shown in FIG. 1 in that it does not include the detection circuit 105a.

  The transmission device 50 according to the present embodiment also includes a change rate detection circuit 21, a dummy data generation circuit 201 instead of the dummy data generation circuit 17, and a parity operation circuit 103 a. 1 and the point that the parity output circuit 104a is not provided is different from the transmission device 30 of the first embodiment shown in FIG.

  The change rate detection circuit 21 detects the data change rates h0 to h31 at each bit position in the data D1 having a 32-bit configuration.

  FIG. 5 is a block diagram illustrating a configuration example of the change rate detection circuit 21, which includes a counter unit 211 and a control unit 212.

  The counter unit 211 includes 32 counters 211-0 to 211-31, and the counters 211-0 to 211-31 each have data 0 to bit 0 to bit 31 of data D1. d31 is entered. Each counter 211-0 to 211-31 increments the count value at the rising and falling edges of the data d0 to d31 (in this embodiment, +1), and when the reset signal is input, the counter value is set to “0”. "

  The control unit 212 includes control circuits 212-0 to 212-31 for the counters 211-0 to 211-31. Each of the control circuits 212-0 to 212-31 outputs a reset signal to the counters 211-0 to 211-31 when the packet identification signal 102 becomes “Hi” (at the start of the data valid period) Thereafter, a reset signal is output to the counters 211-0 to 211-31 every predetermined time on condition that the packet identification signal 102 is “Hi”. Further, when the packet identification signal 102 becomes “Lo” (at the start of the data invalid period), the control circuits 212-0 to 212-31 are based on the count values of the counters 211-0 to 211-31 at that time. Thus, the data change rates h0 to h31 at the respective bit positions of the data D1 are calculated and output to the dummy data generation circuit 201.

  Here, the shorter the reset interval of the counters 211-0 to 211-31, the more accurately the data change rate immediately before the data invalid period can be detected. However, since it is better to ignore current fluctuations for a minute time to some extent, in this embodiment, the counters 211-0 to 211-31 are reset every 16 clocks. In the change rate detection circuit 21 of the present embodiment, the data change rate for 16 clocks immediately before the data invalid period may not be detected depending on the data length of the data D1, but the data length is 16 If the data is a multiple of bits, the data change rate for 16 clocks immediately before the data invalid period can be detected.

  The dummy data generation circuit 201 generates dummy data at each bit position based on the data change rate at each bit position detected by the change rate detection circuit 21.

  FIG. 6 is a block diagram illustrating a configuration example of the dummy data generation circuit 201. The dummy data output units 61-0 to 61-31 to which the data change rates h0 to h31 output from the change rate detection circuit 21 are input. And dummy data storage units 62-0 to 62-31 for the respective dummy data output units 61-0 to 61-31.

  In the dummy data storage units 62-0 to 62-31, dummy data having data change rates of 10%, 30%, 50%, 70%, and 90% are registered. Each dummy data output unit 61-0 to 61-31 has an input data change rate h0 to h31 of 0% to less than 20%, 20% to less than 40%, 40% to less than 60%, 60% to 80% Less than 80% to 100%, dummy data with a data change rate of 10%, 30%, 50%, 70%, 90% is read from the dummy data storage units 62-0 to 62-31, respectively, and the selector 16 Output for.

[Description of Operation of Second Embodiment]
Next, the operation of the present embodiment will be described. Since operations other than the change rate detection circuit 21 and the dummy data generation circuit 201 are the same as those in the first embodiment, only the operations of the change rate detection circuit 21 and the dummy data generation circuit 201 will be described here.

  The packet identification signal 102 is input to the change rate detection circuit 21, and the control circuits 212-0 to 212-31 in the change rate detection circuit 21 are at time t71 as shown in the time chart of FIG. When the packet identification signal 102 becomes “Hi”, a reset signal is output to the counters 211-0 to 211-31. Thereafter, the control circuits 212-0 to 212-31 output a reset signal to the counters 211-0 to 211-31 every 16 clocks on condition that the packet identification signal 102 is “Hi”.

  Each of the counters 211-0 to 211-31 receives the data d0 to d31 of the 0th bit to the 31st bit of the data D1, respectively, and increments the count value by 1 at the rising and falling of the data d0 to d31, When the reset signal is input, the count value is set to “0”.

  Thereafter, when the packet identification signal 102 becomes “Lo” at time t72, the control circuits 212-0 to 212-31 have data change rates h0 to h based on the count values of the counters 211-0 to 211-31 at that time. h31 is calculated, and the calculated data change rates h0 to h31 at the respective bit positions are output to the dummy data generation circuit 201. For example, when the count value of the counter 211-0 is “8”, the data change rate h0 is 50% (= 8 ÷ 16).

  The dummy data generation circuit 201 generates dummy data at each bit position based on the data change rates h0 to h31 at each bit position sent from the change rate detection circuit 21, and outputs the dummy data to the selector 16. For example, if the input data change rate h0 is 40%, the dummy data output unit 61-0 in the dummy data generation circuit 201 extracts data with a data change rate of 50% from the dummy data storage unit 62-0. , Output to the selector 16.

[Effects of Second Embodiment]
According to the present embodiment, it is possible to extremely reduce fluctuations in current consumption that occur when switching between a data valid period and a data invalid period. The reason is that the change rate detection circuit 21 detects the data change rate of the data output immediately before the data invalid period, and the dummy data that generates dummy data according to the data change rate detected by the change rate detection circuit 21 This is because the generation circuit 201 is provided.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. The present embodiment is characterized in that the data change rate immediately before the data invalid period can be detected regardless of the data length of the data D1. This embodiment is realized by using the change rate detection circuit 21 having the configuration shown in FIG. 8 as the change rate detection circuit 21 in FIG.

  Referring to FIG. 8, the change rate detection circuit 21 includes a counter unit 81 and a control unit 82.

  The counter unit 81 includes 32 counters 81-0 to 81-31. The counters 81-0 to 81-31 have data 0 to bit 31 of data D1 to bit 0 to bit 31 of data D1, respectively. d31 is entered. Each of the counters 81-0 to 81-31 increments the count value at the rising and falling edges of the data d0 to d31 (in this embodiment, +1), and when the reset signal is input, the counter value is set to “0”. "

  The control unit 82 includes 32 shift registers 821-0 to 821-31 and 32 control circuits 822-0 to 822-31.

  The shift registers 821-0 to 821-31 have a 16-stage configuration, and take and shift the count values output from the counters 81-0 to 81-31 according to the clock signal that is the drive clock of the transmission device 50. To do. In this embodiment, since the data change rate for 16 clocks immediately before the data invalid period is detected, the number of stages of the shift registers 821-0 to 821-31 is 16, but the shift register The number of stages of 821-0 to 821-31 is not limited to this.

  The control circuits 822-0 to 822-31 output reset signals to the counters 81-0 to 81-31 when the packet identification signal 102 becomes “Hi” (when the data valid period is reached), When the packet identification signal 102 becomes “Lo”, the data change rates h0 to h31 are calculated based on the count values set in the input stage and output stage of the shift registers 821-0 to 821-31, and dummy data Output to the generation circuit 201.

[Operation of Third Embodiment]
Next, the operation of the present embodiment will be described. Since the operation other than the operation of the change rate detection circuit 21 is the same as that of the second embodiment, only the operation of the change rate detection circuit 21 will be described here.

  When the packet identification signal 102 becomes “Hi”, the control circuits 822-0 to 822-31 output a reset signal to the counters 81-0 to 81-31. When the reset signal is input, the counters 81-0 to 81-31 set the count value to “0”. The counters 81-0 to 81-31 increment the count value by 1 at the rising and falling edges of the data d0 to d31. The shift registers 821-0 to 821-31 capture and shift the count values output from the counters 81-0 to 81-31 according to the clock signal. Therefore, the count values of the counters 81-0 to 81-31 for the past 16 clocks are held in the shift registers 821-0 to 821-31.

  When the packet identification signal 102 becomes “Lo”, the control circuits 822-0 to 822-31 change the data based on the count values set in the input stage and output stage of the shift registers 821-0 to 821-31. The ratios h0 to h31 are calculated and output to the selector 202. More specifically, the data change rate is calculated by performing an operation of {(count value set in the input stage) − (count value set in the output stage)} / 16.

[Effect of the third embodiment]
According to the present embodiment, even if the data output from the transmission device 50 is variable length data, it is possible to output dummy data according to the data change rate of the data output immediately before the data invalid period become. The reason is that the counters 81-0 to 81-31 incremented when the data D1 rises and falls, and the shift register 821 with a predetermined number of stages that takes in and shifts the count values of the counters 81-0 to 81-31 according to the clock signal. -0 to 821-31 and a control circuit 822- that calculates the data change rate based on the count values held in the input stage and output stage of the shift registers 821-0 to 821-31 at the start of the data invalid period This is because the change rate detection circuit 21 having 0 to 822-31 is provided.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. Referring to FIG. 9, the present embodiment includes a transmitting device 70 that transmits data using SPI-3 and a receiving device 40 that receives data using SPI-3.

  The difference between the present embodiment and the first embodiment shown in FIG. 1 is that a transmission device 70 is provided instead of the transmission device 30. The transmission device 70 differs from the transmission device 30 shown in FIG. 1 in that a change rate detection circuit 21 is added and a dummy data generation circuit 201 is provided instead of the dummy data generation circuit 17. Yes.

[Description of Operation of Fourth Embodiment]
Next, the operation of the present embodiment will be described.

  The change rate detection circuit 21 detects the data change rates h0 to h31 at the respective bit positions of the data D1, and outputs them to the dummy data generation circuit 201. The dummy data generation circuit 201 outputs dummy data D1 corresponding to the data change rates h0 to h31 output from the change rate detection circuit 21 to the selector 16. The parity calculation circuit 103a outputs the parity calculation result 108 for the data D1 while the packet identification signal 102 is “Hi”, and is output from the dummy data generation circuit 201 while the packet identification signal 102 is “Lo”. The parity calculation result 108 for the dummy data is output. The parity output circuit 104a outputs a parity bit 107 corresponding to the parity operation result 108 output from the parity operation circuit 103a to the receiving device 40.

[Effect of the fourth embodiment]
According to the present embodiment, in addition to the effect obtained by the second and third embodiments that it is possible to suppress fluctuations in power consumption when switching between the data valid period and the data invalid period, the data invalid period In this case, it is possible to obtain an effect that failure detection can be performed. The reason is that a parity output circuit 104a is provided that outputs the parity bit 107 for the data D1 in the data valid period and outputs the parity bit 107 for the dummy data 5 in the data invalid period.

  The present invention can be applied to a transmission device that transmits data using SPI-3.

It is a block diagram which shows the structural example of 1st Embodiment of the transmission device concerning this invention. It is a figure for demonstrating a data change rate. It is a time chart for demonstrating operation | movement of 1st Embodiment. It is a block diagram which shows the structural example of 2nd Embodiment of the transmission device concerning this invention. It is a block diagram which shows the structural example of the change rate detection circuit 21 used in 2nd Embodiment. 3 is a block diagram illustrating a configuration example of a dummy data generation circuit 201. FIG. It is a time chart for demonstrating operation | movement of 2nd Embodiment. It is a block diagram which shows the structural example of the change rate detection circuit 21 used in 3rd Embodiment. It is a block diagram which shows the structural example of 4th Embodiment of the transmission device concerning this invention. It is a block diagram which shows the structural example of the conventional general transmission device and reception device which use SPI-3. It is a time chart for demonstrating the operation | movement of FIG. It is a figure for demonstrating the problem of a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 30, 50, 70 ... Transmission device 11 ... T / RSX generation circuit 12 ... T / RENB generation circuit 15 ... Switching control circuit 16 ... Selector 17, 201 ... Dummy data generation circuit 21 ... Change rate detection circuit 81, 211 ... Counter unit 81-0 to 81-31, 211-0 to 211-31 ... Counter 82, 212 ... Control unit 821-0 to 821-31 ... Shift register 212-0 to 212-31, 822-0 to 822-31 Control circuit 61-0 to 61-31 Dummy data output unit 62-0 to 62-31 Dummy data storage unit 101 "0" output circuit 103, 103a Parity operation circuit 104, 104a Parity output circuit 20, 40, 60 ... receiving device 13 ... T / RSX receiving circuit 14 ... T / RENB receiving circuit 18 ... data processing circuit 105, 105a ... detecting circuit

Claims (14)

A transmission device that outputs the data in a data valid period in which data to be output exists and outputs dummy data in a data invalid period that does not exist,
A transmission device comprising a dummy data generation circuit that generates dummy data having a small difference in data change rate from data output during a data valid period as the dummy data. The transmitting device according to claim 1, wherein
A transmission device, wherein a data change rate of dummy data generated by the dummy data generation circuit is a fixed value. The transmitting device according to claim 2, wherein
A transmission device, wherein a data change rate of dummy data generated by the dummy data generation circuit is approximately 50%. The transmitting device according to claim 1, wherein
A transmission device, wherein a data change rate of dummy data generated by the dummy data generation circuit dynamically changes. The transmitting device according to claim 4, wherein
The transmission device, wherein the dummy data generation circuit generates dummy data having a data change rate corresponding to a data change rate of data output immediately before a data invalid period. The transmitting device according to claim 5, wherein
A change rate detection circuit for detecting a data change rate of data output immediately before the data invalid period, and
The transmission device, wherein the dummy data generation circuit generates dummy data according to the data change rate detected by the change rate detection circuit. The transmitting device according to claim 6, wherein
The rate of change detection circuit is
A counter that is incremented at the rise and fall of the data and is reset every predetermined time;
A transmission device comprising: a control circuit that inputs a count value of the counter at the start of a data invalid period and obtains a data change rate based on the input count value. The transmitting device according to claim 6, wherein
The rate of change detection circuit is
A counter that is incremented when the data rises and falls;
A shift register having a predetermined number of stages for capturing and shifting the count value of the counter according to a clock signal;
A transmission device comprising: a control circuit that calculates a data change rate based on count values held in an input stage and an output stage of the shift register at the start of a data invalid period. The transmission device according to any one of claims 1 to 8,
A transmission device comprising a parity output circuit that outputs a parity bit for the data during a data valid period and outputs a parity bit for the dummy data during a data invalid period. A power circuit;
The transmission device according to any one of claims 1 to 9 connected to the power supply circuit;
An electric circuit comprising: an analog circuit connected to the power supply circuit. A method for stabilizing current consumption in a transmitting device that outputs the data in a data valid period in which data to be output exists and outputs dummy data in a non-existent data invalid period,
As the dummy data, dummy data having a small difference in data change rate from data output during a data valid period is generated. In the consumption current stabilization method according to claim 11,
A method for stabilizing current consumption, characterized in that the data change rate of dummy data is a fixed value. In the consumption current stabilization method according to claim 11,
A method for stabilizing current consumption, characterized in that the data change rate of dummy data changes dynamically. The current consumption stabilization method according to claim 13,
A method for stabilizing current consumption, comprising generating dummy data having a data change rate corresponding to a data change rate of data output immediately before a data invalid period.

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