CN112531018A - Novel IGBT power semiconductor device - Google Patents
Novel IGBT power semiconductor device Download PDFInfo
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- CN112531018A CN112531018A CN202011552683.3A CN202011552683A CN112531018A CN 112531018 A CN112531018 A CN 112531018A CN 202011552683 A CN202011552683 A CN 202011552683A CN 112531018 A CN112531018 A CN 112531018A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 abstract description 9
- 230000008569 process Effects 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a novel IGBT power semiconductor device, comprising: a substrate; a buffer region disposed on the substrate; the base region is arranged on the buffer region; the grid electrode structure comprises a base region, a plurality of real grid electrode units and a plurality of grid electrode units, wherein the real grid electrode units are arranged on the base region, false groove units are arranged on two sides of each real grid electrode unit respectively, and contact holes of each real grid electrode unit are connected with contact holes of the false groove units on two adjacent sides. The invention can increase the width of the source region, improve the consistency of the process, and improve the consistency and uniformity of the characteristics of the device such as threshold voltage and the like in the wafer, thereby solving the manufacturability problem of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a novel IGBT power semiconductor device.
Background
With the upgrading of the technology, the IGBT has completed many changes, such as the transition of the back surface of the IGBT from the thick PT type to the thin NPT, and then the upgrading to the FS field termination of the ultrathin sheet; for example, the front surface of the IGBT is upgraded into a groove type from a plane structure, and then is upgraded into a micro-groove structure shown in FIG. 1. However, as the size of the unit cell of the trench structure is reduced to be within 2um, and the current density per unit area is greatly increased, the short circuit and the RBSOA capability are weakened.
In order to solve the above problems, it has been proposed to replace part of the real gate with the dummy trench structure shown in fig. 2, or even the mixed structure of the dummy trench and the dummy gate shown in fig. 3, to reduce the effective channel and improve the short circuit and RBSOA capability, but the distance between the contact hole and the gate trench is very small, typically less than 0.5um, due to the small unit cell size, and in addition, the drift of the alignment of the hole lithography process and the loading effect of the etching process may further result in poor uniformity and uniformity of the device, thereby posing a challenge to the manufacturability of the device.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the art described above. Therefore, the invention aims to provide a novel IGBT power semiconductor device, which can increase the width of a source region, improve the consistency of the process, improve the consistency and the uniformity of the characteristics of the device such as the threshold voltage and the like in a wafer, and further solve the manufacturability problem of the device.
In order to achieve the above object, an embodiment of the present invention provides a novel IGBT power semiconductor device, including: a substrate; a buffer region disposed on the substrate; the base region is arranged on the buffer region; the grid electrode structure comprises a base region, a plurality of real grid electrode units and a plurality of grid electrode units, wherein the real grid electrode units are arranged on the base region, false groove units are arranged on two sides of each real grid electrode unit respectively, and contact holes of each real grid electrode unit are connected with contact holes of the false groove units on two adjacent sides.
According to the novel IGBT power semiconductor device provided by the embodiment of the invention, the substrate is arranged, and the buffer region, the base region and the plurality of real grid units are sequentially arranged on the substrate, wherein the dummy groove units are respectively arranged at two sides of each real grid unit, and the contact hole of each real grid unit is connected with the contact holes of the dummy groove units at two adjacent sides, so that the width of a source region can be increased, the consistency of the process is improved, the consistency and the uniformity of the characteristics of the device such as threshold voltage and the like in a wafer are improved, and the manufacturability problem of the device is solved.
In addition, the novel IGBT power semiconductor device proposed according to the above example of the present invention may also have the following additional technical features:
according to one embodiment of the invention, the contact hole of each real gate unit is not continuously connected with the contact holes of the dummy trench units on two adjacent sides, so that a plurality of combined contact holes arranged at equal intervals are formed on two sides of each real gate unit.
According to an embodiment of the invention, a well region is further arranged between each real gate unit and the dummy trench units on two adjacent sides, and the well region is arranged on the base region.
According to an embodiment of the invention, source regions are further disposed on two sides of each true gate unit, and the source regions are disposed on the well region.
According to an embodiment of the present invention, the source region is connected to the dummy trench unit through the merging contact hole.
According to an embodiment of the invention, each real gate unit is further provided with an emitter, and the emitter is connected with the plurality of merging contact holes which are formed on two sides of each real gate unit and are arranged at equal intervals.
According to one embodiment of the invention, the substrate is an N-type substrate.
According to one embodiment of the present invention, the well region is a P-type well region.
According to one embodiment of the present invention, the source region is N+A source region.
Drawings
FIG. 1 is a schematic structural diagram of a micro-trench IGBT in the prior art;
FIG. 2 is a schematic structural diagram of a dummy trench IGBT in the prior art;
FIG. 3 is a schematic structural diagram of a micro-trench IGBT with a mixed dummy trench and dummy gate in the prior art;
FIG. 4 is a schematic structural diagram of a novel IGBT power semiconductor device according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of a novel IGBT power semiconductor device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 4 is a schematic structural diagram of the novel IGBT power semiconductor device according to the embodiment of the present invention.
As shown in fig. 4, the novel IGBT power semiconductor device according to the embodiment of the present invention includes: a substrate 10; a buffer region 20, the buffer region 20 being disposed on the substrate 10; a base region 30, the base region 30 being disposed on the buffer region 20; and a plurality of real gate units 40, wherein the plurality of real gate units 40 are arranged on the base region 30, dummy trench units 50 are respectively arranged on two sides of each real gate unit 40, and the contact hole of each real gate unit 40 is connected with the contact holes of the dummy trench units 50 on two adjacent sides.
Specifically, as shown in fig. 5, the contact hole of each real gate unit 40 is discontinuously connected with the contact holes of the dummy trench units 50 on two adjacent sides, so as to form a plurality of merging contact holes 100 arranged at equal intervals on two sides of each real gate unit 40, thereby increasing the width of the source region, improving the uniformity of the process, improving the uniformity and uniformity of characteristics such as the threshold voltage of the device in the wafer, and solving the manufacturability problem of the device. Wherein, each real Gate unit 40 is provided with a Gate contact hole 200 therein, and each real Gate unit 40 includes a Gate.
In one embodiment of the present invention, the substrate 10 may be an N-type substrate, and in particular, the N-type substrate may be an N-type single crystal silicon substrate. In addition, in other embodiments of the present invention, the substrate 10 may also be other semiconductor materials, such as polysilicon or amorphous silicon, and may also include mixed semiconductor structures, such as silicon carbide, alloy semiconductors, or combinations thereof, which are not limited herein.
In another embodiment of the present invention, the contact hole of each real gate unit 40 is not connected with the contact holes of the dummy trench units 50 on two adjacent sides, and a plurality of merged contact holes 100 arranged at unequal intervals may be formed on two sides of each real gate unit 40, so that the distance from the patch hole on two sides of each real gate unit 40 to the gate may be increased, the threshold voltage characteristic of the device may be ensured, and the uniformity and uniformity of the wafer in the device may be ensured.
In one embodiment of the present invention, the buffer region 20 may be a SIC buffer region, and may be epitaxially formed on the substrate 10, and further, the base region 30 may be epitaxially formed on the buffer region 20. The buffer region 20 may be an N-type SIC buffer region, and the base region 30 may be an N-base region. In addition, in other embodiments of the present invention, the buffer region and the base region can be configured as other types, for example, the buffer region 20 can be a P-type SIC buffer region, which is not limited herein.
Further, as shown in fig. 4, a well region 60 is further disposed between each real gate unit 40 and the dummy trench units 50 on two adjacent sides, and the well region 60 is disposed on the base region 30, wherein the well region 60 may be a P-type well region.
Further, as shown in fig. 4, source regions 70 are disposed on two sides of each true gate unit 40, and the source regions 70 are disposed on the well region 60, wherein the source regions 70 may be N+The source region may be specifically disposed on a well region 60, such as a P-type well region, between the true gate cell 40 and the adjacent dummy trench cell 50. As further shown in fig. 4, the source region 70 may be connected to the dummy trench cell 50 through the merged contact hole 100, whereby the width of the source region can be increased, so that the threshold voltage characteristic of the device can be ensured, and the uniformity and uniformity of the wafer in the device can be ensured.
Further, as shown in fig. 4, each real gate unit 40 is further provided with an Emitter 80, i.e., Emitter, and the Emitter 80, i.e., Emitter, is connected to a plurality of merging contact holes 100 formed at two sides of each real gate unit 40 and arranged at equal intervals. It should be further noted that, as shown in fig. 5, the width dimension of each merging contact hole 100 and the pitch dimension between adjacent merging contact holes 100 are not unique and can be adjusted according to the actual production conditions, for example, the width dimension a of the merging contact holes 100 arranged at equal intervals on both sides of each real gate unit 40, the longitudinal pitch b between the merging contact holes 100 arranged at equal intervals, and the diagonal pitch c between the merging contact holes 100 arranged in a staggered manner can be adjusted according to the actual production conditions.
It should be further noted that the manufacturing process of the novel IGBT power semiconductor device proposed by the present invention is the same as that of the existing micro-trench gate IGB, and no additional process flow is required, so that the increase of the production cost due to the process improvement can be avoided.
For example, the manufacturing process of the novel IGBT power semiconductor device proposed by the present invention is as follows: 1, injecting a push junction to form a P-type PW conductive layer; 2, injecting push junctions at two sides of the real grid unit to form an N-type conducting layer N+Source region, the rest is N-free+A source region; 3, the real grid unit is connected with the emitter through the contact hole; and 4, connecting the dummy trench unit to the emitter through the contact hole of the real grid unit.
According to the novel IGBT power semiconductor device provided by the embodiment of the invention, the substrate is arranged, and the buffer region, the base region and the plurality of real grid units are sequentially arranged on the substrate, wherein the dummy groove units are respectively arranged at two sides of each real grid unit, and the contact hole of each real grid unit is connected with the contact holes of the dummy groove units at two adjacent sides, so that the width of a source region can be increased, the consistency of the process is improved, the consistency and the uniformity of the characteristics of the device such as threshold voltage and the like in a wafer are improved, and the manufacturability problem of the device is solved.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The meaning of "plurality" is two or more unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (9)
1. A novel IGBT power semiconductor device is characterized by comprising:
a substrate;
a buffer region disposed on the substrate;
the base region is arranged on the buffer region;
the grid electrode structure comprises a base region, a plurality of real grid electrode units and a plurality of grid electrode units, wherein the real grid electrode units are arranged on the base region, false groove units are arranged on two sides of each real grid electrode unit respectively, and contact holes of each real grid electrode unit are connected with contact holes of the false groove units on two adjacent sides.
2. The novel IGBT power semiconductor device as claimed in claim 1, wherein the contact holes of each real gate unit are discontinuously connected with the contact holes of the dummy trench units on two adjacent sides, so as to form a plurality of combined contact holes arranged at equal intervals on two sides of each real gate unit.
3. The novel IGBT power semiconductor device as claimed in claim 2, wherein a well region is further arranged between each real gate unit and the dummy trench units on two adjacent sides, and the well region is arranged on the base region.
4. The novel IGBT power semiconductor device according to claim 3, characterized in that source regions are further arranged on two sides of each real gate unit, and the source regions are arranged on the well region.
5. The novel IGBT power semiconductor device of claim 4, wherein said source region is connected to said dummy trench cell through said merged contact hole.
6. The novel IGBT power semiconductor device as claimed in claim 5, wherein each real gate unit is further provided with an emitter, and the emitter is connected with a plurality of merging contact holes which are formed on two sides of each real gate unit and are arranged at equal intervals.
7. The novel IGBT power semiconductor device of claim 6, characterized in that the substrate is an N-type substrate.
8. The novel IGBT power semiconductor device of claim 7, wherein the well region is a P-type well region.
9. The IGBT power semiconductor device of claim 8, wherein the source region is N+A source region.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011552683.3A CN112531018A (en) | 2020-12-24 | 2020-12-24 | Novel IGBT power semiconductor device |
| PCT/CN2021/118047 WO2022134664A1 (en) | 2020-12-24 | 2021-09-13 | Novel igbt power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011552683.3A CN112531018A (en) | 2020-12-24 | 2020-12-24 | Novel IGBT power semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| CN112531018A true CN112531018A (en) | 2021-03-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011552683.3A Pending CN112531018A (en) | 2020-12-24 | 2020-12-24 | Novel IGBT power semiconductor device |
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| Country | Link |
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| CN (1) | CN112531018A (en) |
| WO (1) | WO2022134664A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022134664A1 (en) * | 2020-12-24 | 2022-06-30 | 江苏宏微科技股份有限公司 | Novel igbt power semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389901B (en) * | 2018-04-24 | 2020-07-31 | 四川大学 | Carrier storage enhancement type super-junction IGBT |
| CN108389902B (en) * | 2018-04-28 | 2020-06-26 | 四川大学 | Reverse conducting IGBT with back groove grid |
| CN110890422A (en) * | 2019-12-02 | 2020-03-17 | 江苏宏微科技股份有限公司 | Groove IGBT and manufacturing method thereof |
| CN112531018A (en) * | 2020-12-24 | 2021-03-19 | 江苏宏微科技股份有限公司 | Novel IGBT power semiconductor device |
-
2020
- 2020-12-24 CN CN202011552683.3A patent/CN112531018A/en active Pending
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2021
- 2021-09-13 WO PCT/CN2021/118047 patent/WO2022134664A1/en active Application Filing
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022134664A1 (en) * | 2020-12-24 | 2022-06-30 | 江苏宏微科技股份有限公司 | Novel igbt power semiconductor device |
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| WO2022134664A1 (en) | 2022-06-30 |
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