CN112530891A - 半导体封装结构和其制造方法 - Google Patents

半导体封装结构和其制造方法 Download PDF

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CN112530891A
CN112530891A CN201911284154.7A CN201911284154A CN112530891A CN 112530891 A CN112530891 A CN 112530891A CN 201911284154 A CN201911284154 A CN 201911284154A CN 112530891 A CN112530891 A CN 112530891A
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region
copper
conductive pillars
type conductive
semiconductor package
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林咏胜
高金利
方绪南
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN112530891A publication Critical patent/CN112530891A/zh
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Abstract

本公开提供了一种半导体封装结构，所述半导体封装结构包含：半导体管芯表面，所述半导体管芯表面具有较窄间距区域和与所述较窄间距区域相邻的较宽间距区域；多个第一类型导电柱，所述第一类型导电柱位于所述较窄间距区域中，所述第一类型导电柱中的每个第一类型导电柱具有铜‑铜界面；以及多个第二类型导电柱，所述第二类型导电柱位于所述较宽间距区域中，所述第二类型导电柱中的每个第二类型导电柱具有铜‑焊料界面。还公开了一种用于制造本文所述的半导体封装结构的方法。

Description

半导体封装结构和其制造方法
技术领域
本公开涉及一种具有金属-金属接合和金属-焊料接合的半导体封装结构。
背景技术
半导体工艺技术一直朝着越来越小的设备几何结构的方向发展，从而显著增加可以放置在单个芯片上的电路系统的量(即，增加电路密度)。通常，以定制和半定制设备的形式向公众提供的集成电路技术也遵循这一路线，从而以越来越低的成本在单个芯片上提供越来越多的门。一种特定类型的半定制集成电路设备被称为ASIC(专用集成电路)，所述ASIC通常包含标准单元和门阵列技术。目前，可以为ASIC提供成千上万个门，即使体积相对较小也是如此。
在某种程度上，ASIC技术受益于如存储器和微处理器技术等其它领域中的工艺技术进步。这些领域也一直趋向于实现更小的设备几何结构和更高的电路密度。存储器技术，特别是DRAM(动态随机存取存储器)技术现在通常在单个存储器芯片上提供400万到1600万位的存储。微处理器技术已经发展到通常可以获得百万门(million-gate)微处理器的程度。
上述趋势通常伴随着对到芯片的输入/输出(I/O)连接的需求增加。随着I/O计数增加，接触衬垫之间的间距缩小，并且桥接相邻的焊料连接表面。另外，需要较低的接触电阻，特别是对于高I/O计数的产品。
发明内容
在一些实施例中，本公开提供了一种半导体封装结构，所述半导体封装结构包含第一载体，所述第一载体具有第一表面，所述第一表面具有第一区域和第二区域。所述半导体封装结构进一步包含第二载体，所述第二载体具有与所述第一表面相对的第二表面，所述第二表面具有对应于所述第一区域的第三区域和对应于所述第二区域的第四区域。所述半导体封装结构进一步包含多个第一类型导电柱，所述第一类型导电柱位于所述第一表面的所述第一区域与所述第二表面的所述第三区域之间；多个第二类型导电柱，所述第二类型导电柱位于所述第一表面的所述第二区域与所述第二表面的所述第四区域之间。所述第一类型导电柱中的每个第一类型导电柱的接触电阻低于所述第二类型导电柱中的每个第二类型导电柱的接触电阻。
在一些实施例中，本公开提供了一种半导体封装结构，所述半导体封装结构包含：半导体管芯表面，所述半导体管芯表面具有较窄间距区域和与所述较窄间距区域相邻的较宽间距区域；多个第一类型导电柱，所述第一类型导电柱位于所述较窄间距区域中，所述第一类型导电柱中的每个第一类型导电柱具有铜-铜界面；以及多个第二类型导电柱，所述第二类型导电柱位于所述较宽间距区域中，所述第二类型导电柱中的每个第二类型导电柱具有铜-焊料界面。
在一些实施例中，本公开提供了一种用于制造半导体封装结构的方法，所述方法包含：提供具有第一表面的第一晶圆；在所述第一表面的第一区域中电镀多个第一导电柱并且在所述第一表面的第二区域中电镀多个第二导电柱；使所述多个第一导电柱和所述多个第二导电柱平坦化；以及在所述多个第二导电柱中的每个第二导电柱上选择性地形成焊料凸点。
附图说明
当与附图一起阅读以下详细描述时，可以根据以下详细描述容易地理解本公开的各方面。应当注意的是，各种特征可能不一定按比例绘制。实际上，为了讨论的清楚起见，可以任意增大或减小各种特征的尺寸。
图1A展示了根据本公开的一些实施例的半导体封装结构的横截面视图。
图1B展示了根据本公开的一些实施例的在接合操作之前的半导体封装结构的横截面视图。
图2A展示了根据本公开的一些实施例的半导体封装结构的横截面视图。
图2B展示了根据本公开的一些实施例的在接合操作之前的半导体封装结构的横截面视图。
图3A展示了根据本公开的一些实施例的半导体封装结构的横截面视图。
图3B展示了根据本公开的一些实施例的在接合操作之前的半导体封装结构的横截面视图。
图3C1、图3C2、图3C3和图3C4展示了根据本公开的一些实施例的在各种制造操作期间的中间半导体封装结构的横截面视图。
图4A、图4B、图4C和图4D展示了根据本公开的一些实施例的半导体封装结构的一部分的各种制造操作。
图5A、图5B、图5C和图5D展示了根据本公开的一些实施例的半导体封装结构的一部分的各种制造操作。
图6A、图6B、图6C和图6D展示了根据本公开的一些实施例的半导体封装结构的一部分的各种制造操作。
图7A、图7B和图7C展示了根据本公开的一些实施例的在各种制造操作期间的中间半导体封装结构的横截面视图。
具体实施方式
贯穿附图和详细描述，使用共同的附图标记来指示相同或类似的组件。根据以下结合附图进行的详细描述将容易理解本公开的实施例。
如“上方”、“下方”、“向上”、“左侧”、“右侧”、“向下”、“顶部”、“底部”、“竖直”、“水平”、“侧面”、“更高”、“更低”、“上部”、“之上”、“之下”等空间描述是关于某个组件或某组组件或组件或一组组件的某个平面针对所述一或多个组件的朝向而指定的，如相关附图所示。应当理解，本文所使用的空间描述仅仅是出于说明的目的，并且本文所描述的结构的实际实施方案可以在空间上以任何朝向或方式布置，条件是这种布置不偏离本公开的实施例的优点。
为了实现高I/O计数场景并降低接触电阻，采用了混合接合，所述混合接合包含同一表面处的金属-金属接合和电介质-电介质接合。然而，在接合操作之前，需要进行复杂的平坦化操作以控制金属表面凹陷(dishing)的程度，从而促进接合操作。例如，需要进行至少三种化学机械抛光(CMP)操作以抛光电镀金属、溅射晶种层以及围绕金属和晶种层的介电表面。介电表面的表面粗糙度对后续的接合操作至关重要。一般来说，电介质-电介质接合在金属-金属接合之前发生，电介质接合强度可能难以控制并且可能影响混合接合的质量。此外，对混合接合中的金属-金属表面和电介质-电介质表面之间的对准要求非常高，例如，在1μm的工艺窗口内。
本公开提供了一种具有以下接合类型的半导体封装结构：在较窄间距区域中采用金属-金属界面，而在较宽间距区域中采用金属-焊料界面，使得可以放宽混合接合中的复杂平坦化操作、表面粗糙度控制和精确对准。在较宽间距区域中采用金属-焊料有助于较窄间距区域中的金属-金属界面对准。还提供了一种用于制造具有上述接合类型的半导体封装结构的方法。
参照图1A，图1A展示了根据本公开的一些实施例的半导体封装结构10的横截面视图。半导体封装结构10包含载体101和接合到所述载体的载体102。载体101可以包含面向载体102的第一表面1011，并且载体102可以包含面向载体101的第二表面1021。可以在第一表面1011上标识至少两个区域，例如，连接到第一类型导电柱131的第一区域111和连接到第二类型导电柱132的第二区域112。第一类型导电柱131和第二类型导电柱132的组成不同，并且第二类型导电柱132可以侧向包围第一类型导电柱131，如图1A所示。在一些实施例中，相比载体101的边缘，第一类型导电柱131更靠近中心。在一些实施例中，第一类型导电柱131和第二类型导电柱132各自包含多个导电柱。当在本文中指示第一类型导电柱131时，可以引用一个导电柱或多个同一类型的导电柱。例如，第一类型导电柱131的间距(其是紧邻的第一类型导电柱131之间的距离)可以小于第二类型导电柱132的间距(其是紧邻的第二类型导电柱132之间的距离)。换句话说，第一类型导电柱131定位在第一表面1011的较窄间距区域中，并且第二类型导电柱132定位在第一表面1011的较宽间距区域中。在一些实施例中，第一类型导电柱131的间距小于约20μm，例如，介于10μm与20μm之间。在一些实施例中，第二类型导电柱132的间距大于约20μm，例如，介于20μm与40μm之间。
类似地，可以在第二表面1021上标识至少两个区域，例如，连接到第一类型导电柱131的第三区域113和连接到第二类型导电柱132的第四区域114。第二表面1021的第三区域113以第一类型导电柱131连接第一区域111和第三区域113的方式对应于第一表面1011的第一区域111。第二表面1021的第四区域114以第二类型导电柱132连接第二区域112和第四区域114的方式对应于第一表面1011的第二区域112。在一些实施例中，相比载体101的边缘，第一类型导电柱131更靠近中心。在一些实施例中，第一类型导电柱131和第二类型导电柱132各自包含多个导电柱。例如，第一类型导电柱131的间距(其是紧邻的第一类型导电柱131之间的距离)可以小于第二类型导电柱132的间距(其是紧邻的第二类型导电柱132之间的距离)。换句话说，第一类型导电柱131定位在第二表面1021的较窄间距区域中，并且第二类型导电柱132定位在第二表面1021的较宽间距区域中。在一些实施例中，第一类型导电柱131的间距小于约20μm，例如，介于10μm与20μm之间。在一些实施例中，第二类型导电柱132的间距大于约20μm，例如，介于20μm与40μm之间。在一些实施例中，相邻的第一类型导电柱131与第二类型导电柱132之间的距离D大于所述多个第一类型导电柱131的间距。
在一些实施例中，载体101可以是具有不同区域I/O密度的半导体管芯，例如，专用集成电路(ASIC)管芯、或高带宽存储器(HBM)管芯、或具有多个管芯区域的半导体晶圆，每个管芯区域具有不同的区域I/O密度。在一些实施例中，载体102可以是具有不同区域I/O密度的半导体管芯或具有多个管芯区域的半导体晶圆，每个管芯区域具有不同的区域I/O密度。
在一些实施例中，第一类型导电柱131由单种导电材料(例如，铜)构成。第一类型导电柱131可以包含铜-铜界面131A，相比第二表面1021，所述铜-铜界面更靠近第一表面1011。在一些实施例中，第二类型导电柱132由多于一种导电材料构成，包含但不限于铜、焊料(例如，SnAg)等。在一些实施例中，第二类型导电柱132由铜、焊料(例如，SnAg)和镍构成。第二类型导电柱132可以包含铜-焊料界面132A，相比第一表面1011，所述铜-焊料界面更靠近第二表面1021。因此，由于不存在异质界面并且铜的电阻低于焊料的电阻，第一类型导电柱131的接触电阻小于第二类型导电柱132的接触电阻。
第二类型导电柱132可以包含位于第一表面1011近侧的第一铜区段、位于第二表面1021近侧的第二铜区段、位于第一铜区段与第二铜区段之间的焊料(例如，SnAg)区段1321。如图1A所示，可以在第二类型导电柱132上观察到铜-焊料界面132A。在一些实施例中，在第一铜区段与焊料区段1321之间安置有粘合区段1322，例如，镍区段。在一些实施例中，在粘合区段1322与焊料区段1321之间安置有第三铜区段。
在图1A中，第一类型导电柱131上的铜-铜界面131A可以与第二类型导电柱132上的铜-焊料界面132A处于不同水平。例如，相比第二表面1021，铜-铜界面131A可以更靠近第一表面1011，并且相比第一表面1011，铜-焊料界面132A可以更靠近第二表面1021。在一些实施例中，第二类型导电柱132的第一铜区段可以具有约10μm的厚度。在一些实施例中，第二类型导电柱132的第二铜区段可以具有约5μm的厚度(未按比例绘制)。在一些实施例中，第一类型导电柱131的位于第一表面1011与铜-铜界面131A之间的铜区段约为10μm。在一些实施例中，第一类型导电柱131的位于第二表面1021与铜-铜界面131A之间的铜区段小于30μm，例如，介于28μm与30μm之间。
图1B展示了根据本公开的一些实施例的在接合操作之前的半导体封装结构的横截面视图。在一些实施例中，载体101可以是晶圆级的单切功能管芯或管芯区域，并且载体102可以是接合晶圆。在接合操作之前，第一表面1011的第二区域112中的中间导电柱的铜区段的厚度与第一表面1011的第一区域111中的中间导电柱的铜区段的厚度基本相同。第二区域112中的中间导电柱进一步包含粘合区段1322(例如，镍)和焊料区段1321。另一方面，在接合操作之前，第二表面1021的第三区域113中的中间导电柱的铜区段的厚度基本上大于第二表面1021的第四区域114中的中间导电柱的铜区段的厚度。如图1B所示，将在接合操作之后形成铜-铜界面131A和铜-焊料界面132A。
在接合操作期间，使焊料区段1321与第二表面1021的第四区域114中的铜区段接触，并且通过适当的对准和退火操作使第一区域111中的铜区段与第三区域113中的铜区段接触。然而，当发生未对准时，例如，焊料区段1321的中心与第二表面1021上的铜区段的中心不重叠，或者第一区域111中的铜区段的中心与第三区域113中的铜区段的中心不重叠，熔融焊料区段1321的粘聚力可以对两个管芯的每个区域上的中间导电柱施加拉力，从而使中间导电柱以自组装方式对准。
图2A展示了根据本公开的一些实施例的半导体封装结构20的横截面视图。半导体封装结构20类似于半导体封装结构10，但具有以下差异。第一类型导电柱131的侧壁涂覆有焊料层1311，例如，SnAg。在一些实施例中，在第一类型导电柱131中形成有铜-焊料界面，这是因为第一类型导电柱131的侧壁与焊料层1311接触并且可能在界面处形成金属间化合物。在一些实施例中，在第一类型导电柱131与焊料层1311之间形成有另外的粘合层1312，例如，镍。在一些实施例中，第一类型导电柱131上的铜-铜界面131A可以与第一类型导电柱131上另外的焊料-焊料界面和/或镍-镍界面齐平。
图2B展示了根据本公开的一些实施例的在接合操作之前的半导体封装结构的横截面视图。在一些实施例中，载体101可以是晶圆级的单切功能管芯或管芯区域，并且载体102可以是接合晶圆。在接合操作之前，第一表面1011的第二区域112中的中间导电柱的铜区段的厚度与第一表面1011的第一区域111中的中间导电柱的铜区段的厚度基本相同。第二区域112中的中间导电柱进一步包含粘合区段1322(例如，镍)和焊料区段1321。另一方面，在接合操作之前，第二表面1021的第三区域113中的中间焊料涂覆导电柱的铜区段的厚度基本上大于第二表面1021的第四区域114中的中间导电柱的铜区段的厚度。如图2B所示，将在接合操作之后形成铜-铜界面131A和铜-焊料界面132A。
在接合操作期间，使焊料区段1321与第二表面1021的第四区域114中的铜区段接触，并且通过适当的对准和退火程序使第一区域111中的焊料涂覆铜区段与第三区域113中的焊料涂覆铜区段接触。然而，当发生未对准时，例如，焊料区段1321的中心与第二表面1021上的铜区段的中心不重叠，或者第一区域111中的焊料涂覆铜区段的中心与第三区域113中的焊料涂覆铜区段的中心不重叠，熔融焊料区段1321和熔融焊料层1311的粘聚力可以对两个管芯的每个区域上的中间导电柱施加拉力，从而使中间导电柱以自组装方式对准。此外，如果铜-铜界面131A不是通过电连接形成或者甚至其接触电阻不大于期望电阻，则焊料层1311可以在接合之后提供必要的电连接。
图3A展示了根据本公开的一些实施例的半导体封装结构30的横截面视图。半导体封装结构30类似于半导体封装结构10，但具有以下差异。铜膏区段1313位于第一表面1011的第一区域111中的铜区段与第二表面1021的第三区域113中的铜区段之间。图3A用于示出铜膏的位置，并且因此未按比例绘制。铜膏可以是连接相对铜区段的薄层。在一些实施例中，如果相对的铜区段未被适当接合，则施涂铜膏以减小接触电阻。将在图3C1、图3C2、图3C3和图3C4中描述对上述场景的说明。
图3B展示了根据本公开的一些实施例的在接合操作之前的半导体封装结构的横截面视图。在一些实施例中，载体101可以是晶圆级的单切功能管芯或管芯区域，并且载体102可以是接合晶圆。在接合操作之前，第一表面1011的第二区域112中的中间导电柱的铜区段的厚度与第一表面1011的第一区域111中的中间导电柱的铜区段的厚度基本相同。第二区域112中的中间导电柱进一步包含粘合区段1322(例如，镍)和焊料区段1321。另一方面，在接合操作之前，第二表面1021的第三区域113中的中间焊料涂覆导电柱的铜区段的厚度基本上大于第二表面1021的第四区域114中的中间导电柱的铜区段的厚度。如图2B所示，将在接合操作之后形成铜-铜界面131A和铜-焊料界面132A。
在接合操作期间，使焊料区段1321与第二表面1021的第四区域114中的铜区段接触，并且通过适当的对准和退火程序使第一区域111中的铜区段与第三区域113中的铜区段接触。然而，当发生未对准时，例如，焊料区段1321的中心与第二表面1021上的铜区段的中心不重叠，或者第一区域111中的铜区段的中心与第三区域113中的铜膏的中心不重叠，熔融焊料区段1321的粘聚力可以对两个管芯的每个区域上的中间导电柱施加拉力，从而使中间导电柱以自组装方式对准。
图3C1、图3C2、图3C3和图3C4展示了根据本公开的一些实施例的在各种制造操作期间的中间半导体封装结构的横截面视图。在图3C1中，在载体301上形成多个铜区段131'。在图3C2中，将所述多个铜区段131'浸入到铜膏300中，从而在铜区段131'中的每个铜区段之上形成铜膏区段313。然后，使载体301与具有对应铜区段131”的另一载体302接触并进行接合操作。接合操作可以包含促进相对铜区段131'、131”之间的铜互扩散的退火工艺。相对铜区段131'、131”之间可能发生未对准的情况：因为(1)铜区段131'的中心可能偏离铜区段131”的中心；(2)铜区段131'在退火工艺之后可能与铜区段131”不接触，使得它们之间存在小的缝隙；(3)铜区段131'、131”之一的接合表面可能不平坦，使得接合表面的一部分未连接到其对应物；或上述各项的组合。在铜膏存在的情况下，可以通过向相对铜区段提供另外的导电通道以应用铜膏，从而减轻增加接触电阻的上述情况。
图4A、图4B、图4C和图4D展示了根据本公开的一些实施例的半导体封装结构的一部分的各种制造操作。在图4A中，提供第一载体101，例如，具有第一表面1011的第一晶圆。在图4B中，在第一表面1011之上形成多个第一导电区段131B和多个第二导电区段132B。具体地，在第一表面1011上的第一区域111以间距P1形成导电区段131B，并且在第一表面1011上的第二区域112中以间距P2形成第二导电区段132B。间距P1小于间距P2。在一些实施例中，第一区域111是管芯内的密集区域，并且第二区域112是同一管芯内的隔离区域。在图4C中，执行平坦化操作以使第一导电区段131B和第二导电区段132B平坦化。在一些实施例中，平坦化操作包含展平第一导电区段131B和第二导电区段132B的上表面的化学机械抛光(CMP)。在图4D中，在第二区域112中的第二导电区段132B之上选择性地形成焊料区段1321，例如，焊料凸点。焊料区段1321可以通过电镀、化学镀或印刷操作形成。在图2A和图2B的半导体封装结构20中，焊料区段1321选择性地形成于第二区域112中的第二导电132B之上，并且焊料层1311形成于第一导电区段131B的侧壁处。在一些实施例中，焊料区段1321和焊料层1311可以以单个操作或单独的操作形成。在一些实施例中，在焊料区段1321之前，在第二导电区段132B之上形成粘合区段1322。在一些实施例中，在焊料区段1321之前，在粘合区段1322之上形成铜区段1323。
图5A、图5B、图5C和图5D展示了根据本公开的一些实施例的半导体封装结构的一部分的各种制造操作。在图5A中，提供第二载体102，例如，具有第二表面1021的第二晶圆。在图5B中，在第二表面1021之上形成多个第三导电区段131C和多个第四导电区段132C。具体地，在第二表面1021上的第三区域113中以间距P1形成第三导电区段131C，并且在第二表面1021上的第四区域114中以间距P2形成第四导电区段132C。间距P1小于间距P2。在一些实施例中，第三区域113是管芯内的密集区域，并且第四区域114是同一管芯内的隔离区域。在图5C中，执行平坦化操作以选择性地使第三导电区段131C平坦化。在一些实施例中，平坦化操作包含展平第三导电区段131C的上表面的化学机械抛光(CMP)。在图5D中，任选地，在第二晶圆102上的第三导电区段131C和第四导电区段132C之上执行等离子活化501操作，以提高铜-铜接合强度。
图6A、图6B、图6C和图6D展示了根据本公开的一些实施例的半导体封装结构的一部分的各种制造操作。图6A到图6D例示了用于接合来自第一载体101和第二载体102的管芯的方法。在图6A中，第一载体101包含多个半导体管芯101A。半导体管芯101A中的每个半导体管芯包含之前在图4B中描述的第一区域111和第二区域112。在图6B中，从第一载体101上划片出所述多个半导体管芯101A并将其放置在第三载体103上。在一些实施例中，还将从另一载体上划片而来的其它类型的半导体管芯101B放置在具有半导体管芯101A的第三载体103之上，并且形成混合管芯集成。任选地，在图6C中，可以在第三载体103上的半导体管芯之上执行等离子活化601。在图6D中，可以将从第二载体102上划片而来的半导体管芯102A接合到第三载体103上的半导体管芯并且完成管芯-晶圆接合操作。半导体管芯101A上的第二导电区段132B中的每个第二导电区段通过促进焊接接合的回焊操作接合到半导体管芯102A上的第四导电区段132C。可替代地，在将第二载体102划片成单独的半导体管芯102A之前，将第二载体102接合到具有混合管芯的第三载体103。可替代地，在不将任何晶圆划片成单独的管芯情况下将第一晶圆101接合到第二晶圆12。在回焊操作之后，通过退火操作将第一表面1011上的第一导电区段131B中的每个第一导电区段连接到第三导电区段131C中的每个第三导电区段，以促进铜-铜界面处的铜-铜扩散。
图7A、图7B和图7C展示了根据本公开的一些实施例的在各种制造操作期间的中间半导体封装结构的横截面视图。在图7A中，首先通过回焊操作将第二导电区段132B中的每个第二导电区段连接到第四导电区段132C中的每个第四导电区段，从而将第一载体101接合到第二载体102。回焊操作允许第二导电区段132B上的焊料区段熔化并连接到第四导电区段132C对应物。如图7B所示，当第一载体101和第二载体102上的对应导电区段之间发生未对准时，熔融焊料的内聚力可以向相对载体施加水平拉力f1和f2并且以自组装方式将两者对准。在图7C中，在自对准之后进行退火操作以促进铜-铜界面131A处的铜-铜扩散并且促进接合工艺。在图7C之后，可以单切第一载体101和第二载体102，并且形成多个半导体封装结构。
如本文所使用的并且未另外定义的，术语“基本上”、“基本”、“大约”和“约”被用来描述和解释小变化。当结合事件或情形使用时，所述术语可以涵盖事件或情形精确发生的实例以及事件或情形接近发生的实例。例如，当结合数值使用时，所述术语可以涵盖小于或等于所述数值的±10％，如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或者小于或等于±0.05％的变化范围。术语“基本上共面”可以指两个表面沿同一平面定位的位置差处于数微米内，如沿同一平面定位的位置差处于40μm内、30μm内、20μm内、10μm内或1μm内。
如本文所使用的，除非上下文另有明确指示，否则单数形式“一个/种(a/an)”和“所述(the)”可以包含复数指代物。在一些实施例的描述中，设置在一个组件“上”或“上方”的另一个组件可以涵盖前一组件直接位于后一组件上(例如，与其物理接触)的情况以及在前一组件与后一组件之间定位有一或多个中间组件的情况。
虽然已经参考本公开的具体实施例描述和展示了本公开，但是这些描述和图示并非限制性的。本领域技术人员应当理解，在不脱离如由权利要求限定的本公开的精神和范围的情况下，可以作出各种改变并且可以取代等同物。图示可能不一定按比例绘制。由于制造工艺和公差，本公开中的艺术再现与实际装置之间可能存在区别。可能存在未具体展示的本公开的其它实施例。说明书和附图应被认为是说明性而非限制性的。可以作出修改以使特定情况、材料、物质构成、方法或过程适于本公开的目标、精神和范围。所有这种修改均旨在落入所附权利要求的范围内。虽然已经参考以特定顺序执行的特定操作描述了本文所公开的方法，但是应理解，可以在不脱离本公开的教导的情况下对这些操作进行组合、细分或重新排列以形成等效方法。因此，除非本文中另有明确指示，否则操作的顺序和分组并非限制。

Claims (20)

1.一种半导体封装结构，其包括：
第一载体，所述第一载体具有第一表面，所述第一表面包括第一区域和第二区域；
第二载体，所述第二载体具有与所述第一表面相对的第二表面，所述第二表面包括对应于所述第一区域的第三区域和对应于所述第二区域的第四区域；
多个第一类型导电柱，所述第一类型导电柱位于所述第一表面的所述第一区域与所述第二表面的所述第三区域之间；以及
多个第二类型导电柱，所述第二类型导电柱位于所述第一表面的所述第二区域与所述第二表面的所述第四区域之间；
其中所述第一类型导电柱中的每个第一类型导电柱的接触电阻低于所述第二类型导电柱中的每个第二类型导电柱的接触电阻。
2.根据权利要求1所述的半导体封装结构，其中所述多个第一类型导电柱中的每个第一类型导电柱包括铜-铜界面。
3.根据权利要求2所述的半导体封装结构，其中所述多个第二类型导电柱中的每个第二类型导电柱包括铜-焊料界面。
4.根据权利要求1所述的半导体封装结构，其中所述第一区域中的所述第一类型导电柱的间距小于所述第二区域中的所述第二类型导电柱的间距。
5.根据权利要求4所述的半导体封装结构，其中所述第一区域中的所述第一类型导电柱的所述间距小于20μm。
6.根据权利要求1所述的半导体封装结构，其中所述第一类型导电柱中的每个第一类型导电柱的侧壁进一步包括焊料涂层。
7.根据权利要求1所述的半导体封装结构，其中所述第一载体包括半导体管芯，并且相比所述半导体管芯的边缘，所述第一表面的所述第一区域更靠近中心。
8.一种半导体封装结构，其包括：
半导体管芯表面，所述半导体管芯表面具有较窄间距区域和与所述较窄间距区域相邻的较宽间距区域；
多个第一类型导电柱，所述第一类型导电柱位于所述较窄间距区域中，所述第一类型导电柱中的每个第一类型导电柱具有铜-铜界面；以及
多个第二类型导电柱，所述第二类型导电柱位于所述较宽间距区域中，所述第二类型导电柱中的每个第二类型导电柱具有铜-焊料界面。
9.根据权利要求8所述的半导体封装结构，其中所述铜-铜界面与所述铜-焊料界面处于不同的水平。
10.根据权利要求8所述的半导体封装结构，其中所述多个第二类型导电柱的间距大于20μm。
11.根据权利要求8所述的半导体封装结构，其中相邻的第一类型导电柱与第二类型导电柱之间的距离大于所述多个第一类型导电柱的间距。
12.根据权利要求8所述的半导体封装结构，其中所述第一类型导电柱中的每个第一类型导电柱的侧壁进一步包括焊料涂层。
13.一种用于制造半导体封装结构的方法，其包括：
提供具有第一表面的第一晶圆；
在所述第一表面的第一区域中电镀多个第一导电区段并且在所述第一表面的第二区域中电镀多个第二导电区段；
使所述多个第一导电区段和所述多个第二导电区段平坦化；以及
在所述多个第二导电区段中的每个第二导电区段上选择性地形成焊料区段。
14.根据权利要求13所述的方法，其进一步包括：
提供具有第二表面的第二晶圆；
在所述第二表面的第三区域中电镀多个第三导电区段并且在所述第二表面的第四区域中电镀多个第四导电区段，所述第三导电区段中的每个第三导电区段的高度大于所述第四导电区段中的每个第四导电区段的高度；以及
选择性地使所述多个第三导电区段平坦化。
15.根据权利要求14所述的方法，其进一步包括：
通过回焊操作将所述第二导电区段中的每个第二导电区段连接到所述第四导电区段中的每个第四导电区段，从而将所述第一晶圆与所述第二晶圆接合。
16.根据权利要求14所述的方法，其进一步包括：在所述回焊操作之后，通过退火操作将所述第一导电区段中的每个第一导电区段连接到所述第三导电区段中的每个第三导电区段。
17.根据权利要求15所述的方法，其进一步包括：在将所述第一晶圆与所述第二晶圆接合之后，对所述第一晶圆和所述第二晶圆进行划片。
18.根据权利要求14所述的方法，其进一步包括：
将所述第一晶圆划片成多个半导体管芯，所述半导体管芯中的每个半导体管芯包括所述第一区域和所述第二区域；以及
通过回焊操作将所述第二导电区段中的每个第二导电区段连接到所述第四导电区段中的每个第四导电区段，从而将所述多个半导体管芯中的每个半导体管芯接合到所述第二晶圆。
19.根据权利要求18所述的方法，其进一步包括：在所述回焊操作之后，通过退火操作将所述第一导电区段中的每个第一导电区段连接到所述第三导电区段中的每个第三导电区段。
20.根据权利要求14所述的方法，其进一步包括：在所述选择性平坦化操作之后，在所述多个第三导电区段和所述多个第四导电区段之上执行等离子活化操作。
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