CN112514367A

CN112514367A - Electronic front curtain timing control device and method and image acquisition device

Info

Publication number: CN112514367A
Application number: CN202080004205.0A
Authority: CN
Inventors: 刘瑛; 孙德超
Original assignee: SZ DJI Technology Co Ltd
Current assignee: SZ DJI Technology Co Ltd
Priority date: 2020-01-13
Filing date: 2020-01-13
Publication date: 2021-03-16
Also published as: WO2021142587A1

Abstract

The device and the method for controlling the timing of the electronic front curtain and the image acquisition device are provided, the time delay parameter of the timing control signal of the electronic front curtain is obtained, a plurality of pulses are generated according to the time delay parameter, and the timing control signal is output according to the pulses. The scheme can stably and accurately simulate the nonlinear electronic front curtain exposure time sequence control based on the time delay parameter of the timing control signal, and achieves the purpose of replacing a mechanical front curtain.

Description

Electronic front curtain timing control device and method and image acquisition device

Technical Field

The disclosure relates to the technical field of drive control, in particular to an electronic front curtain timing control device and method and an image acquisition device.

Background

The mechanical shutter has a front curtain and a rear curtain mechanical structure, and shake is inevitably introduced in the movement process of the front curtain and the rear curtain, so that the imaging quality of a camera is influenced. Due to the above drawbacks, electromechanical hybrid shutters have been introduced. The electromechanical hybrid shutter adopts an electronic front curtain and a mechanical rear curtain structure. The introduction of the electronic front curtain can radically avoid the shaking influence caused by the mechanical front curtain. The electronic front curtain needs to simulate the exposure opening time sequence of the mechanical front curtain to achieve the effect of the mechanical front curtain. However, the conventional control method for the exposure opening timing of the electronic front curtain cannot accurately simulate the control timing of the mechanical front curtain.

Disclosure of Invention

In view of this, the embodiments of the present disclosure provide an electronic front curtain timing control device and method, and an image acquisition device, so as to solve the technical problem in the related art that the control timing sequence of a mechanical front curtain cannot be accurately simulated.

According to a first aspect of an embodiment of the present disclosure, there is provided an electronic front curtain timing control device, the device including:

a first control unit and a pulse generating unit;

the first control unit is used for acquiring a time delay parameter of a timing control signal of the electronic front curtain; the timing control signal comprises a plurality of pulses, and the time delay parameter is used for representing the delay time of each pulse relative to the previous pulse in the timing control signal;

the pulse generating unit is used for generating the plurality of pulses according to the time delay parameter under the control of the first control unit and outputting the timing control signal according to the plurality of pulses.

According to a second aspect of the embodiments of the present disclosure, an image capturing device is provided, where the image capturing device includes the electronic front curtain timing control device according to any one of the embodiments.

According to a third aspect of the embodiments of the present disclosure, there is provided an electronic front curtain timing control method, the method including:

acquiring a time delay parameter of a timing control signal of the electronic front curtain; the timing control signal comprises a plurality of pulses, and the time delay parameter is used for representing the delay time of each pulse relative to the previous pulse in the timing control signal;

and generating the plurality of pulses according to the time delay parameters, and outputting the timing control signals according to the plurality of pulses.

According to a fourth aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, on which computer instructions are stored, and when executed, the computer instructions implement the steps of the method according to any one of the embodiments.

According to a fifth aspect of the embodiments of the present disclosure, a computer device is proposed, which comprises a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method according to any of the embodiments when executing the program.

By applying the scheme of the embodiment of the specification, the time delay parameter of the timing control signal of the electronic front curtain is obtained, the plurality of pulses are generated according to the time delay parameter, and the timing control signal is output according to the plurality of pulses. The scheme of the embodiment of the specification can stably and accurately simulate the nonlinear electronic front curtain exposure time sequence control based on the time delay parameter of the timing control signal, and achieves the purpose of replacing a mechanical front curtain.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.

Fig. 1 is a timing diagram illustrating a mechanical front curtain exposure in accordance with an embodiment of the present disclosure.

Fig. 2 is a block diagram illustrating an electronic front curtain timing control apparatus according to an embodiment of the present disclosure.

Fig. 3 is a schematic diagram of a timing control signal of the electronic front curtain timing control apparatus of fig. 2.

Fig. 4 is a schematic diagram illustrating a parameter storage format according to an embodiment of the present disclosure.

Fig. 5A is a block diagram illustrating an electronic front curtain timing control apparatus according to an embodiment of the present disclosure.

Fig. 5B is a block diagram illustrating an electronic front curtain timing control apparatus in accordance with another particular embodiment of the present disclosure.

Fig. 6A is a schematic diagram of a pulse generation unit shown in accordance with an embodiment of the present disclosure.

Fig. 6B is a timing diagram of the pulse generating unit in fig. 6A.

Fig. 7A is a schematic diagram of a pulse generation unit shown in accordance with an embodiment of the present disclosure.

Fig. 7B is a timing diagram of the pulse generating unit in fig. 7A.

Fig. 8A is a schematic diagram illustrating a pulse generating unit according to another embodiment of the present disclosure.

Fig. 8B is a timing diagram of the pulse generating unit in fig. 8A.

Fig. 9 is a schematic diagram illustrating an electronic front curtain timing control apparatus according to an embodiment of the present disclosure.

FIG. 10 is a flow chart illustrating an electronic front curtain timing control method in accordance with an embodiment of the present disclosure.

FIG. 11 is a block diagram illustrating a computer device for implementing the methods of the present disclosure, in accordance with an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the specification, as detailed in the appended claims.

The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information, without departing from the scope of the present specification. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

A shutter is a basic component of an image capture device (e.g., a camera). The shutter can be divided into an inter-mirror shutter and a focal plane shutter according to the position of the shutter. The inter-lens shutter is placed in the camera lens and the focal plane shutter is placed in front of a sensor module in the camera body. Among them, focal plane shutters are divided into global shutters and rolling shutters.

The global shutter is that the sensor module performs overall simultaneous exposure operation on the optical signal of the scenery transmitted by the lens, and the shutter operation is considered to be operation from full close to full open to full close. During the full-open period, the whole sensor module performs photoelectric conversion at the same time, the operation is performed by taking an image frame as a unit, the independent capacitor of each pixel accumulates charges of the photoelectric conversion during the exposure period, and the photoelectric conversion result of each pixel is stored in the independent capacitor of the pixel. The global shutter then closes, stopping the pixel photoelectric conversion process, so that the individual capacitance charge result of the pixel needs to be preserved, requiring that the capacitance leak slowly. Thus, an analog-to-Digital (AD) conversion circuit common to the sensor modules can convert the signals according to the lines to obtain Digital conversion results, and then read the Digital conversion results according to the lines. The leakage time requirement of the capacitor will impose requirements on the design of the sensor chip, thereby greatly increasing the manufacturing cost of the sensor chip. Therefore, the sensor module supporting the global shutter is generally used in a high-end single lens reflex camera or a movie camera.

And the rolling shutter structure comprises a front curtain and a rear curtain, wherein the front curtain is used for opening exposure, and the rear curtain is used for ending exposure. The rolling shutter refers to that the sensor module performs photoelectric conversion on one or two rows of pixel points at each time, performs photoelectric conversion during exposure, can reset a charging capacitor of the exposed pixel points when exposure is started, then accumulates charges of the photoelectric conversion during exposure, and requires an AD conversion circuit common to the sensor module to perform conversion according to rows to obtain a digital conversion result and perform quick reading according to rows when the row of exposure is finished. The leakage time requirement on the independent capacitance of the pixel is low, so that the design requirement of the sensor chip can be greatly reduced, and the manufacturing cost of the sensor chip is reduced.

Most sensors support rolling shutters, which are classified as mechanical shutters and electromechanical hybrid shutters. The mechanical shutter adopts a front curtain and a rear curtain to realize a structure, and is divided into two closed modes from left to right or from top to bottom, and the specific direction of the mechanical shutter is related to the exposure and reading time sequence of the sensor module.

Since the mechanical shutter has a front curtain mechanical structure and a rear curtain mechanical structure, shake is inevitably introduced during the movement of the front curtain and the rear curtain, thereby affecting the imaging quality of the camera. In addition, the mechanical structure inevitably has service life problems. Because play when the back curtain is closed and block the photoelectric conversion's of sensor module light signal input for the electric capacity no longer charges. If the mechanical rear curtain does not exist, a pure electronic shutter is used, the electronic front curtain and the electronic rear curtain only can complete the function of a rolling shutter, and if all rows cannot be read in a short time, a serious jelly effect is generated.

Due to the above drawbacks, electromechanical hybrid shutters have been introduced. The electromechanical hybrid shutter adopts an electronic front curtain and a mechanical rear curtain structure. The introduction of the electronic front curtain can radically avoid the shaking influence caused by the mechanical front curtain, and can further reduce the thickness and the manufacturing cost of the camera. And the mechanical rear curtain is used for completely blocking the photoelectric conversion optical signal input of the sensor module.

The electronic front curtain needs to simulate the exposure opening time sequence of the mechanical front curtain to achieve the effect of the mechanical front curtain. When a non-linear mechanical front curtain is used, the exposure on timing for each line is different from that of the previous line because the moving speed of the mechanical front curtain is not constant but sweeps across each line at a mechanical acceleration. An electronic shutter that simulates the timing of a nonlinear mechanical front curtain exposure is referred to as a nonlinear electronic shutter.

Since the mechanical front curtain exists outside the sensor module, the exposure timing of the mechanical front curtain cannot be directly acquired by the sensor module itself. To obtain the exposure timing of the mechanical front curtain, the sensor module may provide an external timing input pin, the camera main chip driving software simulates the exposure timing of the mechanical front curtain, and the sensor module performs an exposure start operation according to the input timing, as shown in fig. 1. Here, VSYNC refers to a frame synchronization signal, HSYNC refers to a line synchronization signal, and NLST (Non-linear Shutter) refers to a Non-linear electronic front curtain timing control input.

The linear electronic front curtain exposure timing control uses an input frame synchronization signal (HSYNC), and since the HSYNC is generated by an external chip in an image frame format, configuration of a driving software of a sensor module is not required. When the driving software of the sensor module needs to realize the non-linear electronic front curtain exposure time sequence control, the time sequence control concentrated on the rear half part of the image is harsh (as shown in last 4 lines in fig. 1), and the MCU processor executing the driving software frequently responds to interruption, thereby generating serious MCU load overhead. The nonlinear electronic front curtain exposure timing control results are also unstable and inaccurate if the MCU also performs other tasks at this time. The control timing of the mechanical front curtain cannot be accurately simulated if the nonlinear electronic front curtain exposure timing control is implemented with driving software.

Based on this, the embodiment of the present disclosure provides an electronic front curtain timing control device. The electronic front curtain timing control device is positioned outside the camera main chip. That is, the device operates independently with respect to the MCU when generating the timing control signal of the electronic front curtain, thereby not causing frequent interrupts of the MCU processor. As shown in fig. 2, the apparatus includes:

a first control unit 201 and a pulse generating unit 202;

the first control unit 201 is configured to obtain a time delay parameter of a timing control signal of the electronic front curtain; the timing control signal comprises a plurality of pulses, and the time delay parameter is used for representing the delay time of each pulse relative to the previous pulse in the timing control signal;

the pulse generating unit 202 is configured to generate the multiple pulses according to the time delay parameter under the control of the first control unit 201, and output the timing control signal according to the multiple pulses.

According to an embodiment of the present invention, the delay time of each pulse with respect to the previous pulse is a delay time of each pulse obtained from a time point after the end of the previous pulse of each pulse as a calculation starting point.

Wherein the timing control signal of the electronic front curtain comprises a plurality of pulses. In order to reproduce the timing control signal, it is necessary to determine the time at which each pulse is generated. The disclosed embodiment determines the generation time of each pulse in the timing control signal by obtaining a time delay parameter of the timing control signal, where the time delay parameter corresponding to a first pulse is a time interval between the generation time of the pulse and the generation time of an initial trigger signal for triggering the pulse generation unit 202 to output the pulse, that is, delay 1. As shown in fig. 3, the time of delay1 is the time interval between the time corresponding to the falling edge of the trigger signal (which may be a frame synchronization signal) and the falling edge of the first pulse of the timing control signal. The delay parameters delay2, delay3, … …, delayN for each pulse starting from the second pulse may be calculated using the time interval between the instant corresponding to the falling edge of the pulse and the instant corresponding to the falling edge of the previous pulse.

The first control unit 201 may obtain the above delays 1 to delayN, and control the pulse generating unit 202 to generate the 1 st pulse after delaying the time corresponding to delay1 after receiving the trigger signal, generate the 2 nd pulse after delaying the time corresponding to delay2 after generating the 1 st pulse, and so on. The time delay parameters corresponding to each pulse in the timing control signal may be the same or different. For example, the value of delay1 may be equal to d0, the values of delay2 and delay3 may be equal to d1, the values of delay4 to delay6 may be equal to d2, and the value of delay7 may be equal to d3 in fig. 3, where the values of d0, d1, d2, d3 are not the same.

For the linear electronic front curtain, the time delay parameters corresponding to each pulse are the same, so that each pulse in the timing control signal can be generated by only acquiring one time delay parameter. For the nonlinear electronic front curtain, the time delay parameters corresponding to each pulse are different, and therefore, the time delay parameter corresponding to each pulse needs to be acquired respectively.

In some embodiments, as shown in fig. 4, the delay parameter includes a delay amount parameter for indicating a time length of the delay time, and includes a number of pulses parameter for which the delay amount is effective. Wherein, para1_ delay to para N _ delay are respectively N delay parameter, and Num1 to NumN are respectively pulse number parameters corresponding to para1_ delay to para N _ delay. Assuming Num1 is 1, Num2 is 4, and Num3 is 3, it indicates that the number of validation times of para1_ delay, para2_ delay, and para3_ delay is 1, 4, and 3, respectively. That is, the delay amount corresponding to one pulse is para1_ delay, the delay amounts corresponding to the four pulses after the pulse are respectively para2_ delay, and the delay amounts corresponding to the three pulses after the four pulses are respectively para3_ delay. If the pulse number parameter corresponding to the delay parameter is 0, it indicates that the delay parameter generated this time is invalid, and the process of generating the timing control signal is ended.

And the time delay parameter and the pulse number parameter are determined according to the nonlinear characteristic of the electronic front curtain. The non-linear characteristic mainly refers to the scanning acceleration of each row of pixels in the scanning image of the electronic front curtain. The larger the acceleration is, the faster the delay parameter changes, that is, the fewer the pulse number parameters corresponding to the same delay parameter are; conversely, the smaller the acceleration is, the slower the delay parameter changes, that is, the more the number of pulses corresponding to the same delay parameter.

In some embodiments, as shown in fig. 5A, the apparatus further comprises: a buffer unit 203 for buffering the delay parameter; the first control unit 201 is configured to read the delay parameter from the buffer unit 203. The buffer unit 203 of this embodiment may be a FIFO (First In First Out) memory, and may sequentially store the delay parameters corresponding to each pulse into the FIFO memory according to the sequence In which each pulse is generated, and when the timing control signal is generated, sequentially write the delay parameters corresponding to each pulse into the First control unit 201 from the FIFO memory.

Further, the apparatus further comprises: a storage unit 204 and a second control unit 205; the storage unit 204 is configured to store the time delay parameter; the second control unit 205 is configured to establish a communication connection with the cache unit 203, and after the communication connection is successfully established, read the delay parameter from the storage unit 204, and write the delay parameter into the cache unit 203. The storage unit 204 may be a Random Access Memory (RAM), and the second control unit 205 may be a Direct Memory Access Controller (DMAC). In this embodiment, the buffer unit 203 may send a handshake signal to the second control unit 205 to establish a communication connection with the second control unit 205. The communication connection may be a TCP/IP (Transmission Control Protocol/Internet Protocol ) connection, a bluetooth connection, a bus connection, or the like. In the embodiment shown in fig. 5A, the cache unit 203, the storage unit 204, and the second control unit 205 are connected by an on-chip interconnect bus. After the communication connection is successfully established, the second control unit 205 may read the delay parameter from the storage unit 204 and write the delay parameter into the memory of the buffer unit 203.

In other embodiments, as shown in fig. 5B, the apparatus further comprises: an interface unit 206 and a register 207; the delay parameter is written into the register 207 through the interface unit 206; the first control unit 201 is configured to read the delay parameter from the register 207. In this embodiment, the delay parameter is configured in the register 207 through the interface unit 206, and the RAM storage space does not need to be occupied, thereby saving the storage space. In one embodiment, in the manual mode, the time delay parameter and the pulse width parameter are determined according to an exposure parameter selected by a user in the interface. In another embodiment, in the automatic mode, the driver software of the chip is calculated from the exposure parameters.

In some embodiments, the first control unit 201 is further configured to obtain a pulse width parameter (width) of the pulse; the pulse generating unit 202 is configured to generate the plurality of pulses according to the time delay parameter and the pulse width parameter under the control of the first control unit 201. Since the pulse signal has a certain width, a pulse signal having a certain width can be generated by obtaining the pulse width parameter.

In some embodiments, the pulse generating unit 202 includes N pulse generating sub-units 2021 to 202N, and a selecting unit 202a connected to the output terminals of the pulse generating sub-units 2021 to 202N; wherein, the output terminal of the ith pulse generation subunit 202i is connected to the input terminal of the (i + 1) th pulse generation subunit 202i +1 to output the trigger signal of the (i + 1) th pulse generation subunit 202i + 1; the output end of the nth pulse generation subunit 202N is connected to the first input end of the 1 st pulse generation subunit 2021 to output the trigger signal of the 1 st pulse generation subunit 2021; n and i are positive integers, i is more than or equal to 2 and is less than N; each pulse generating subunit 2021 to 202N generates a pulse in the timing control signal according to the time delay parameter each time it receives its own trigger signal; the 1 st pulse generating subunit 2021 uses the trigger signal accessed by the second input terminal as an initial trigger signal; and the selection unit 202a is used for sequentially selecting the pulses generated by the respective pulse generation sub-units 2021 to 202N to output the timing control signal.

Please refer to fig. 6A and 6B. Fig. 6A is a schematic diagram of a pulse generation unit shown in accordance with an embodiment of the present disclosure. Fig. 6B is a timing diagram of the pulse generating unit in fig. 6A. PTG is a pulse generating subunit, delay and width are respectively a time delay parameter and a pulse width parameter, and Trigger _ in is a Trigger signal. The timing sequence of the pulse generating subunit is as shown in fig. 6B, assuming that the delay parameters of the first pulse and the second pulse of the timing control signal are delay1 and delay2, respectively, if a falling edge of the Trigger signal (Trigger _ in) is detected, delaying the delay1 time and outputting the first pulse of the timing control signal; if the next falling edge of the trigger signal is detected, delay2 is delayed and the second pulse of the timing control signal is output.

A schematic diagram of a pulse generating unit according to an embodiment of the disclosure is shown in fig. 7A. The scheme of the embodiment of the present disclosure is illustrated in the figure by taking the case where the number of pulse generating subunits is 2 as an example. It will be appreciated that in practical applications the number of pulse generating subunits may also be larger than 2. In the figure, PTG1 and PTG2 are the 1 st pulse generation subunit and the 2 nd pulse generation subunit, delay and width are the delay parameter and the pulse width parameter, respectively, Trigger _ in is the Trigger signal, NLST _ OUT is the pulse output by PTG1 and PTG2, and NLST is the timing control signal. As shown in fig. 7A, trig _ sel is used to select one signal in the middle of VSYNC and NLST _ OUT as Trigger signal Trigger _ in. NLST _ OUT is used to control PTG1 and PTG2 to perform a combinational logic operation, thereby generating NLST signals.

In the present embodiment, the PTG1 is first triggered by an initial trigger signal, i.e., a frame synchronization signal (VSYNC), and when a falling edge of VSYNC is detected, the PTG1 reads the delay parameter and the width parameter and outputs one pulse (e.g., pulse 1) as a trigger signal of the PTG 2. When the PTG2 detects the falling edge of the pulse output by the PTG1, the delay parameter and the width parameter are read, and one pulse (for example, pulse 2) is output. The PTG2 outputs a pulse as a trigger signal of the PTG1, and when the PTG1 detects a falling edge of the pulse output by the PTG2, reads the delay parameter and the width parameter, and outputs one pulse (e.g., pulse 3). After the initial trigger signal triggers for the first time, the PTGs 1 and 2 use the output pulses of the other side as trigger signals, and continuously and alternately generate pulses according to the delay parameter and the width parameter until the value of the number of pulses in the delay parameter is 0. In some embodiments, the initial trigger signal is a frame synchronization signal.

The NLST signals generated by PTGs 1 and 2 are shown in fig. 7B, taking the delay parameter content as follows as an example.

1	d0
		4	d1
3	d2
		0	d3

When PTG1 detects the falling edge of VSYNC, a pulse with width of width (1 st pulse) is generated after d0 time, PTG2 generates a pulse with width of width (2 nd pulse) after d1 time under the trigger of 1 st pulse, PTG1 generates a pulse with width of width (3 rd pulse) after d1 time under the trigger of 2 nd pulse, and 4 pulses with delay amount of d1 and 3 pulses with delay amount of d2 are continuously generated in the manner described above. Through two PTG modules which are mutually trigger sources, the generation time sequence of the complex NLST signal can be realized only by small logic.

In addition to the above embodiments, the number of pulse generating subunits may also be 1. Please refer to fig. 8A and 8B. Fig. 8A is a schematic diagram illustrating a pulse generating unit according to another embodiment of the present disclosure. Fig. 8B is a timing diagram of the pulse generating unit in fig. 8A. In this case, the output terminal (e.g., NLST _ OUT in fig. 8A) of the pulse generation subunit (PTG) is connected to the first input terminal (e.g., the input terminal to which Trigger _ in1 in fig. 8A is connected) of the pulse generation subunit, and the second input terminal (e.g., the input terminal to which Trigger _ in2 in fig. 8A is connected) of the pulse generation subunit is connected to the initial Trigger signal. Initially, the 1 st pulse is output under the trigger of an initial trigger signal (for example, a frame synchronization signal), and then the 1 st pulse is used as a trigger signal to trigger the pulse generation subunit, so that the pulse generation subunit generates a new pulse. The pulse generating unit of the present embodiment and its timing diagram are shown in fig. 8B. Where Clk is the clock signal, the first pulse of the trigger signal is provided by the initial trigger signal and the remaining pulses are provided by the output signal of the PTG. According to another embodiment of the present invention, the first input terminal and the second input terminal are the same input terminal, the first trigger pulse input from the input terminal is a pulse of the initial trigger signal, and the remaining trigger pulses input from the input terminal are pulses output from the output terminal of the PTG.

The embodiment of the disclosure can remarkably reduce the cost of MCU load for implementing nonlinear electronic front curtain exposure time sequence control by executing the driving software, stably and accurately simulate the nonlinear electronic front curtain exposure time sequence control based on delay and width parameters configured by the driving software, and achieve the purpose of replacing a mechanical front curtain.

Fig. 9 is a diagram illustrating a logic circuit implementation according to an embodiment of the present disclosure. The whole solution works as follows: the driving software selects the calibrated nonlinear electronic front curtain customization parameters to write into the parameter cache RAM according to the exposure time parameters; the driver software is configured with DMAC which is set from the parameter cache RAM to the NLST _ GEN module and is configured with the total data transmission length, wherein the setting of DMAC can reduce the load of MCU for storage processing; starting an electronic front curtain timing control device (NLST _ GEN) to work; the FIFO in the LST _ GEN module sends a handshake request to the DMAC according to the internal state (for example, the number of idle addresses) of the current FIFO, the DAMC writes delay parameters into the FIFO, the CTRL reads the delay parameters from the FIFO, the PTG1 is controlled according to the time sequence, the PTG2 generates each pulse in the NLST signal, the selection unit MUX sequentially selects the PTG1 and the PTG2 so as to generate the NLST signal, and the generated NLST signal is output to the sensor module of the camera. In one embodiment, the LST GEN module determines whether to send a handshake signal to the DMA according to the size of the free storage space (i.e., the number of free addresses) existing inside the FIFO. In one embodiment, when the hardware function is turned on by the driver software (e.g., ISP driver software), the reading of the delay parameter is started if an external frame synchronization signal is received. FIFO is used as a parameter transmission interface of a system RAM and an NLST _ GEN module, so that logic implementation is simplified.

The embodiment is realized by adopting the logic circuit, the logic circuit can generate the NLST signal according to the appointed time sequence only by software initialization, the NLST generation process is stable and accurate, and the electronic front curtain can be adopted to simulate the control time sequence of the mechanical front curtain to the maximum extent. The instability of a scheme for simulating the mechanical front curtain control time sequence by adopting a software driving scheme and the rigor of the rear half time sequence requirement are avoided.

The delay parameter storage required by the whole scheme is shared with a system RAM of a chip, and the storage control of the delay parameter can be flexibly carried out according to the control time sequence precision required to be simulated. And FIFO is realized, the logic cost of the PTG module is low, and the influence on the cost of a chip is small.

In some embodiments, the present disclosure also provides an image capture device comprising the electronic front curtain timing control device of any embodiment. The embodiment of the electronic front curtain timing control device in the embodiment of the present disclosure is the same as the above embodiment of the electronic front curtain timing control device, and is not described herein again.

In some embodiments, as shown in fig. 10, the present disclosure also provides an electronic front curtain timing control method, the method comprising:

step S1001: acquiring a time delay parameter of a timing control signal of the electronic front curtain; the timing control signal comprises a plurality of pulses, and the time delay parameter is used for representing the delay time of each pulse relative to the previous pulse in the timing control signal;

step S1002: and generating the plurality of pulses according to the time delay parameters, and outputting the timing control signals according to the plurality of pulses.

In some embodiments, the method further comprises: and reading the time delay parameter from the buffer unit.

In some embodiments, the latency parameter is read from the storage unit and written to the buffer unit by the second control unit.

In some embodiments, the pulses in the timing control signal are generated by N pulse generation subunits; the output end of the ith pulse generation subunit is connected to the input end of the (i + 1) th pulse generation subunit so as to output a trigger signal of the (i + 1) th pulse generation subunit; the output end of the Nth pulse generation subunit is connected to the first input end of the 1 st pulse generation subunit so as to output the trigger signal of the 1 st pulse generation subunit; n and i are positive integers, i is more than or equal to 2 and is less than N; each pulse generating subunit generates a pulse in the timing control signal according to the time delay parameter when receiving the respective trigger signal each time; the 1 st pulse generation subunit takes the trigger signal accessed by the second input end as an initial trigger signal; the method further comprises the following steps: and sequentially selecting the pulses generated by the pulse generating subunits to output the timing control signals.

In some embodiments, the method further comprises: reading the time delay parameter from a register; and the time delay parameter is written into the register in advance through an interface unit.

In some embodiments, the delay parameter includes a delay amount parameter for indicating a time length of the delay time, and includes a number of pulses parameter at which the delay amount is effective.

In some embodiments, the time delay amount parameter and the pulse number parameter are determined according to a nonlinear characteristic of the electronic front curtain.

In some embodiments, the step of generating the plurality of pulses according to the time delay parameter comprises: acquiring a pulse width parameter of the pulse; generating the plurality of pulses according to the time delay parameter and the pulse width parameter.

In some embodiments, the pulse width parameter is read from a buffer unit; or the pulse width parameter is written into a register through an interface unit and read from the register.

In some embodiments, the initial trigger signal is a frame synchronization signal.

The method may be implemented by a driving device, the driving device may include the electronic front curtain timing control device in any embodiment of the present disclosure, and other embodiments of the electronic front curtain timing control device in the driving device are the same as those of the electronic front curtain timing control device, and are not described herein again.

The electronic front curtain timing control device of the embodiments of the present specification may be, for example, a server or a terminal device. The method embodiments may be implemented by software, or by hardware, or by a combination of hardware and software. The software implementation is taken as an example, and as a logical device, the device is formed by reading corresponding computer program instructions in the nonvolatile memory into the memory for operation through the processor in which the file processing is located. From a hardware aspect, as shown in fig. 11, for a hardware structure of an electronic front curtain timing control device implementing the method of the present specification, in addition to the processor 1101, the memory 1102, the network interface 1103 and the nonvolatile memory 1104 shown in fig. 11, the electronic front curtain timing control device used for implementing the method of the present specification in the embodiment may also include other hardware according to an actual function of the electronic front curtain timing control device, which is not described again.

In some embodiments, the present disclosure also provides a computer-readable storage medium having stored thereon a number of computer instructions which, when executed, implement the steps of the method of any of the embodiments.

In some embodiments, the present disclosure also provides a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method of any of the embodiments when executing the program.

The various technical features in the above embodiments can be arbitrarily combined, so long as there is no conflict or contradiction between the combinations of the features, but the combination is limited by the space and is not described one by one, and therefore, any combination of the various technical features in the above embodiments also falls within the scope disclosed in the present specification.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

The above description is only exemplary of the present disclosure and should not be taken as limiting the disclosure, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims

1. An electronic front curtain timing control apparatus, comprising:

a first control unit and a pulse generating unit;

2. The apparatus of claim 1, further comprising:

a buffer unit for buffering the delay parameter;

the first control unit is used for reading the time delay parameter from the buffer unit.

3. The apparatus of claim 2, further comprising:

a storage unit and a second control unit;

the storage unit is used for storing the time delay parameter;

the second control unit is used for establishing communication connection with the cache unit, reading the time delay parameter from the storage unit after the communication connection is successfully established, and writing the time delay parameter into the cache unit.

4. The apparatus of claim 1, wherein the pulse generating unit comprises:

the pulse generator comprises N pulse generating subunits and a selection unit respectively connected with the output end of each pulse generating subunit;

the output end of the ith pulse generation subunit is connected to the input end of the (i + 1) th pulse generation subunit so as to output a trigger signal of the (i + 1) th pulse generation subunit;

the output end of the Nth pulse generation subunit is connected to the first input end of the 1 st pulse generation subunit so as to output the trigger signal of the 1 st pulse generation subunit; n and i are positive integers, i is more than or equal to 2 and is less than N;

each pulse generating subunit generates a pulse in the timing control signal according to the time delay parameter when receiving the respective trigger signal each time; the 1 st pulse generation subunit takes a trigger signal accessed by a second input end as an initial trigger signal; and

the selection unit is used for sequentially selecting the pulses generated by each pulse generation subunit so as to output the timing control signal.

5. The apparatus of claim 2, further comprising:

an interface unit and a register;

the time delay parameter is written into the register through the interface unit;

the first control unit is used for reading the time delay parameter from the register.

6. The apparatus of claim 1, wherein the delay parameter comprises a delay parameter for indicating a time length of the delay time, and a number of pulses parameter for the delay to take effect.

7. The apparatus of claim 6, wherein the delay amount parameter and the number of pulses parameter are determined according to a non-linear characteristic of the electronic front curtain.

8. The apparatus of claim 1, wherein the first control unit is further configured to obtain a pulse width parameter of the pulse;

the pulse generating unit is used for generating the plurality of pulses according to the time delay parameter and the pulse width parameter under the control of the first control unit.

9. The apparatus of claim 8, wherein the pulse width parameter is read from a buffer unit by the first control unit; or

The pulse width parameter is written into a register through an interface unit and is read from the register by the first control unit.

10. The apparatus of claim 4, wherein the initial trigger signal is a frame synchronization signal.

11. An image capturing device, characterized in that it comprises an electronic front curtain timing control device according to any one of claims 1 to 10.

12. An electronic front curtain timing control method, comprising:

13. The method of claim 12, further comprising:

and reading the time delay parameter from the buffer unit.

14. The method of claim 13, wherein the latency parameter is read from a memory location and written to the buffer location by a second control unit.

15. The method of claim 12, wherein the pulses in the timing control signal are generated by N pulse generating subunits; the output end of the ith pulse generation subunit is connected to the input end of the (i + 1) th pulse generation subunit so as to output a trigger signal of the (i + 1) th pulse generation subunit; the output end of the Nth pulse generation subunit is connected to the first input end of the 1 st pulse generation subunit so as to output the trigger signal of the 1 st pulse generation subunit; n and i are positive integers, i is more than or equal to 2 and is less than N; each pulse generating subunit generates a pulse in the timing control signal according to the time delay parameter when receiving the respective trigger signal each time; the 1 st pulse generation subunit takes the trigger signal accessed by the second input end as an initial trigger signal;

the method further comprises the following steps:

and sequentially selecting the pulses generated by the pulse generating subunits to output the timing control signals.

16. The method of claim 13, further comprising:

reading the time delay parameter from a register; and the time delay parameter is written into the register in advance through an interface unit.

17. The method of claim 12, wherein the delay parameter comprises a delay amount parameter indicating a time length of the delay time, and a number of pulses parameter for which the delay amount is effective.

18. The method of claim 17, wherein the delay amount parameter and the number of pulses parameter are determined based on a non-linear characteristic of the electronic front curtain.

19. The method of claim 12, wherein generating the plurality of pulses according to the delay parameter comprises:

acquiring a pulse width parameter of the pulse;

generating the plurality of pulses according to the time delay parameter and the pulse width parameter.

20. The method of claim 19, wherein the pulse width parameter is read from a buffer unit; or

The pulse width parameter is written into a register through an interface unit and read from the register.

21. The method of claim 15, wherein the initial trigger signal is a frame synchronization signal.

22. A computer readable storage medium having stored thereon computer instructions, wherein the computer instructions, when executed, implement the steps of the method of any one of claims 12 to 21.

23. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method of any one of claims 12 to 21 when executing the program.