JP7110007B2 - IMAGE PROCESSING DEVICE, IMAGING DEVICE, CONTROL METHOD FOR IMAGE PROCESSING DEVICE, PROGRAM AND STORAGE MEDIUM - Google Patents

Description

The present invention relates to an image processing apparatus for displaying and recording image data captured by an image sensor, an image capturing apparatus, a control method for the image processing apparatus, a program, and a storage medium.

2. Description of the Related Art In recent years, imaging devices such as digital cameras have increased the number of pixels, increased the speed of continuous shooting of still images, and improved the frame rate of moving images, and the amount of data processed per unit time has increased. An image processing device inside an imaging device such as a digital camera performs processing (capture) of writing data captured by an imaging element into a memory such as a DRAM. Then, the image processing device reads out the data written in the memory, performs image processing, and records the processed image on a medium or the like, and displays the image currently stored in the memory on the rear liquid crystal display of the imaging device. to display. Further, in mirrorless cameras and the like in recent years, instead of the optical viewfinder, the imaging device displays the data currently stored in the memory with an electronic viewfinder.

For example, when the continuous shooting frame speed of still images is increased, the output speed at which the imaging device outputs image data is also increased. As the image data output speed increases, the amount of data processed per unit time at the time of capture increases, and the amount of data accessible to the DRAM (hereinafter referred to as transmission band) approaches its limit. When the transmission band of the DRAM approaches its limit, the data captured in the DRAM cannot be read out at the same time, and display output becomes impossible. When the captured data cannot be output for display, the display may be blacked out, and the display of the most recent captured image may continue to be displayed. For this reason, it is difficult for the photographer to continue framing during photographing. The technique of Patent Document 1 has been proposed for the above problems. The image processing apparatus in this technique performs reduction processing on image data of multiple fields and generates data for display processing during still image recording.

JP 2007-243819 A

In the technique of Patent Document 1, reduction processing is performed without capturing the image data output by the imaging means, and image data for display can be generated while still images are being recorded (configuration capable of on-the-fly processing). ). However, for example, when the imaging means outputs image data at high speed, the reduction processing circuit needs to reduce the imaging data output by the imaging means at high speed. If the processing speed of the reduction processing circuit does not keep up with the speed at which the imaging means outputs the imaged data, a delay will occur in the display and recording of the image data.

An object of the present invention is to provide an image processing device, an imaging device, a control method for the image processing device, a program, and a storage medium that suppress delays between display and recording based on image data captured by an imaging device.

In order to achieve the above object, the image processing apparatus of the present invention includes dividing means for dividing image data acquired from an image sensor into first data and second data according to bit depth; a second memory for storing the first data read out from the first memory and storing the first data and the second data read out from the first memory; output means for outputting data combined with the second data read out from the recording control means to a recording control means for recording the data on a recording medium.

According to the present invention, it is possible to suppress the delay between display and recording based on captured image data.

1 is a perspective view of a digital camera as an imaging device; FIG. 1 is a block diagram showing the configuration of an imaging device according to a first embodiment; FIG. It is a figure which shows a part of imaging device containing an imaging control part. It is a figure which shows an example of the method which divides|segments imaging data. 4 is a flowchart showing an example of the flow of processing according to the first embodiment; 4 is a timing chart showing an imaging sequence of an imaging element; 4 is a timing chart showing control timings of display data and print data when the first embodiment is applied; 4 is a timing chart when reading of recording data and writing to a recording medium are not completed within one frame period; 9 is a timing chart showing control timings of display data and print data when the second embodiment is applied; FIG. 10 is a diagram showing an example of cropped output image data;

Hereinafter, each embodiment of the present invention will be described in detail with reference to the drawings. However, the configurations described in each embodiment below are merely examples, and the scope of the present invention is not limited by the configurations described in each embodiment.

<First Embodiment>
FIG. 1 is a perspective view of a digital camera 10 as an example of an imaging device (imaging device 200) according to each embodiment. The digital camera 10 is provided with a rear liquid crystal display 12 such as an LCD on the rear side. The rear liquid crystal display 12 is a display device 210 described below. The imaging device of this embodiment is not limited to a digital camera. FIG. 2 is a block diagram showing the configuration of the imaging device 200 according to this embodiment. The imaging device 200 has an imaging device 201, an imaging control unit 204, a bus 205, DRAMs 206-1 to 206-N, a recording control unit 207, a recording medium 208, a display control unit 209, a display device 210, a CPU 211, and operation buttons 212. .

The imaging element 201 is an imaging element such as a CMOS sensor. The imaging control unit 204 is an image processing device that performs correction processing for image deterioration caused by the sensor, defective pixel correction, and the like on the imaging data output from the imaging device 201, and generates image data converted into a predetermined format. . The imaging control unit 204 outputs the generated image data to the bus 205 . The imaging control unit 204 generates an imaging control signal for controlling synchronization of exposure and reading of imaging data according to instructions from the CPU 211 , and outputs the imaging control signal to the imaging element 201 via the imaging control signal transmission path 202 . The imaging element 201 outputs captured imaging data to the imaging control unit 204 via the imaging transmission path 203 . A plurality of DRAMs 206 - 1 to 206 -N (N is an integer equal to or greater than 2) are memories that store or hold various data via the bus 205 . The DRAMs 206-1 to 206-N may be collectively referred to as the DRAM 206 hereinafter. For example, the CPU 211 and the imaging control unit 204 read data stored in the DRAM 206 and write data to the DRAM 206 .

The recording control unit 207 performs processing for developing image data such as YUV and optical system correction processing on the data output from the imaging control unit 204, and converts data in a recording format (recording data) according to the recording medium 208. ) is a recording control means for generating The recording control unit 207 performs, for example, a predetermined compression process (such as JPEG compression) on the image data output from the imaging control unit 204 and controls recording on the recording medium 208 . A recording medium 208 is a recording medium that finally stores the recording data output from the recording control unit 207, and for example, an SD card or the like is applied.

The display control unit 209 performs processing to develop the data output by the imaging control unit 204 into a format corresponding to the display device 210 and resize processing to match the output size of the display device 210 . The display device 210 is a display unit that displays the data output by the display control unit 209 at constant synchronous timing, and for example, the rear liquid crystal display 12 described above is applied. The CPU 211 outputs control instructions to the imaging control unit 204 , each DRAM 206 , the recording control unit 207 and the display control unit 209 . Also, the CPU 211 detects that the operation button 212 has been pressed. An operation button 212 is a shooting button of the imaging device 200 .

FIG. 3 is a diagram showing part of the imaging device 200 including the imaging control unit 204. As shown in FIG. FIG. 3 shows some sub-blocks inside the imaging control unit 204 and the relationship between the sub-blocks and peripheral units. The imaging control unit 204 has a division unit 220 and an output unit 221 . The dividing unit 220 is dividing means for dividing the imaging data acquired from the imaging transmission line 203 . FIG. 4 is a diagram showing an example of a method by which the dividing unit 220 divides imaging data. In the example of FIG. 4, the bit depth of each pixel data in the imaging data acquired from the imaging element 201 is 12 bits. The bit depth of each pixel data may be a bit depth other than 12 bits. The division unit 220 divides the 12-bit pixel data into upper 8 bits and lower 4 bits. The number of bits divided by dividing section 220 is not limited to 8 bits and 4 bits. The divided upper 8-bit data (upper bit data) and lower 4-bit data (lower bit data) are stored in different DRAMs 206, respectively. As shown in FIG. 3, dividing section 220 outputs the divided upper bit data to bus 205 via data path 101-1. The upper 8-bit data output to bus 205 is stored in DRAM 206-1 via data path 101-2. Further, dividing section 220 outputs the divided lower bit data to bus 205 via data path 102-1. The lower bit data output to bus 205 is stored in DRAM 206-2 via data path 102-2.

The DRAM 206-1 is, for example, a high-bandwidth first memory employing a data width of 32 bits. The DRAM 206-1 stores high-order 8-bit data (high-band bit data) having a large number of bits. The DRAM 206-2 is, for example, a low-bandwidth second memory employing a data width of 16 bits. The DRAM 206-2 stores low-order 4-bit data (low-band bit data) with a small number of bits. The DRAM 206-1 has a wider transmission band than the DRAM 206-2. Therefore, according to the bit depth of each pixel data, the dividing unit 220 divides the data into first data, which is high-order bit data with a large number of bits, and second data, which is low-order bit data with a smaller number of bits than the high-order bit data. split into Divider 220 stores the first data (upper bit data) in high-band DRAM 206-1 and the second data (lower bit data) in low-band DRAM 206-2.

Data read from DRAM 206-1 is input to output section 221 via data path 101-3, bus 205 and data path 101-4. Data read from DRAM 206-2 is input to output section 221 via data path 102-3, bus 205 and data path 102-4. The output unit 221 performs correction processing and the like on the input data, and outputs the corrected data to the bus 205 via the data path 105 . Although data paths 101-1 and 102-1 in FIG. 3 are shown as different data paths, data paths 101-1 and 102-1 are one data path, for example, in the case of time division data transmission. may Data paths 101-2 and 102-2 are similar, and so are data paths 101-3 and 102-3.

Next, the flow of processing in this embodiment will be described with reference to the flowchart of FIG. 5 and the timing charts of FIGS. FIG. 6 is a timing chart showing the imaging sequence of the imaging device 201. As shown in FIG. FIG. 7 is a timing chart showing control timings of display data and print data. The imaging control unit 204 drives the imaging element 201 in a live view mode (LV mode) during continuous shooting standby (step S401). In the timing chart of FIG. 6, the LV mode period corresponds to the period T1. As shown in the timing chart of FIG. 6, when the imaging state is the LV mode, a synchronizing signal is output at predetermined intervals, and the display control unit 209 displays image data on the display device 210 according to the synchronizing signal. .

The CPU 211 determines whether or not the operation button 212 that triggers the imaging start of the imaging device 200 (camera) has been pressed (step S402). If NO is determined in step S402, step S402 is repeated because there is no instruction to start shooting. If determined as YES in step S402, the image capturing control unit 204 causes the image sensor 201 to transition once to the IDLE mode via the image capturing control signal transmission path 202, and then to the still image capturing mode (step S403). In the timing chart of FIG. 6, the period between T1 and T2 is the IDLE mode period. The CPU 211 sets the recording and display of still images during the period of the IDLE mode (step S404). Then, the imaging control unit 204 outputs a still image driving synchronization signal to the imaging element 201 via the imaging control signal transmission path 202, and causes the imaging element 201 to transition to the still image driving mode (still image continuous shooting mode). (Step S405). In step S<b>405 , the still image driving imaging data is input to the imaging control unit 204 via the imaging transmission path 203 . The operation sequence after step S405 will be described with reference to the timing chart of FIG. A period T601 indicates an output period of image data from the image sensor 201 in one frame period (predetermined cycle). A period other than the hatched period is a V blanking period, which is a waiting time until the next frame. During the V blanking period, no imaging data is input from the imaging device 201 .

During the period T602, the high-order bit data generated by the division unit 220 dividing each pixel data (12 bits) of the imaging data output from the imaging device 201 is stored in the DRAM 206-1, which is a high-bandwidth memory. indicates the period until In a period T603, the lower bit data generated by the division unit 220 dividing each pixel data (12 bits) of the imaging data output from the imaging device 201 is stored in the DRAM 206-2, which is a low-band memory. indicates the period until In period T604, the output unit 221 starts reading the high-order bit data stored in the DRAM 206-1, which is a high-bandwidth memory. At this time, the output unit 221 starts reading via the data path 101-3 after an offset time with a sufficient margin has elapsed so as not to overtake the upper bit data stored in the DRAM 206-1.

In the example of FIG. 7, the read time is longer than the write time for storing data in the DRAMs 206-1 and 206-2. The reason why the read time is longer than the write time is that there is no need to display or record at the same speed as the input speed of image data from the image sensor 201 . For example, in the case of an electronic shutter, image pickup data input from the image sensor 201 may be subjected to rolling shutter distortion reduction processing or the like. Therefore, the read time is longer than the write time.

In the period T605, the output unit 221 performs sensor correction or the like on the data read in the period T604 (data read from the DRAM 206-1), and then outputs the data from the data path 105 to the bus 205. . The data output to the bus 205 is stored in the DRAM 206 and input to the display control unit 209 . The display control unit 209 performs predetermined processing on display data for display on the display device 210 and outputs the display data to the display device 210 .

At this time, the image displayed on the display device 210 is equivalent to 8 bits for 12 bits, which is the bit depth of one pixel of the imaging data input from the image sensor 201. The bit depth is sufficient for the image quality of the framing image. The CPU 211 determines whether display data output to the display device 210 has been completed (step S406). Whether or not the display data output is completed may be detected by the display control unit 209 generating an interrupt indicating that the display data output is completed to the CPU 211 . If the determination in step S406 is NO, step S406 is repeated because display data output has not been completed. If the determination in step S406 is YES, display data output has been completed. In this case, the CPU 211 performs setting for combining the data (recorded data) read from the DRAM 206-1 and the data (recorded data) read from the DRAM 206-2 (step S407).

Based on the above settings, in period T606, the output unit 221 reads the upper bit data already stored in the DRAM 206-1 via the data path 101-3. Similarly, in period T607, output unit 221 reads the lower bit data already stored in DRAM 206-2 via data path 102-3. Data from data path 101-3 is input to output 221 via bus 205 and data path 101-4. Data from data path 102-3 is input to output 221 via bus 205 and data path 102-4. In period T608, the output unit 221 combines the upper bit data input from the DRAM 206-1 and the lower bit data input from the DRAM 206-2 to generate 12-bit data (combined data).

Therefore, as shown in FIG. 7, the output unit 221 reads the high-order bit data in period T604, outputs it to the display control unit 209, and then outputs the combined data to the recording control unit 207 in periods T606 and T607. Output. As a result, image data (image data composed of high-order bit data) can be displayed on the display device 210 and image data (image data composed of combined data) can be recorded on the recording medium 208 . Since the output unit 221 reads the upper bit data from the DRAM 206-1 in periods T604 and T606, the upper bit data is read twice during one frame period. On the other hand, since the output unit 221 reads the lower bit data from the DRAM-2 in the period T607, the number of times of reading the upper bit during one frame period is one, which is smaller than the number of times of reading the upper bit data. High-order bit data is used for both display and recording. Lower bit data is not used for display, but used for recording. Therefore, the number of times the lower bit data is read during one frame period is smaller than the number of times the upper bit data is read. For example, when the high-order bit data is used for other purposes, the high-order bit data may be read a predetermined number of times, 3 or more, during one frame period.

The output unit 221 outputs the generated 12-bit data to the data path 105 after performing correction processing and the like in the same manner as the processing at the time of display. The data (recording data) output to the bus 205 is stored in the DRAM 206 and output to the recording control unit 207 . The recording control unit 207 processes the recording data according to the recording medium 208 and outputs the processed data to the recording medium 208 . As a result, image data composed of 12-bit pixel data is generated.

The CPU 211 determines whether the output of the recording data has been completed, that is, whether the writing of the recording data to the recording medium 208 has been completed (step S408). The recording control unit 207 detects the writing status of the recording data to the recording medium 208, and causes the CPU 211 to generate an interrupt when the writing completion is detected. Thereby, the CPU 211 can make the determination in step S408. If the determination in step S408 is NO, step S408 is repeated because writing of recording data has not been completed. If the determination in step S408 is YES, writing of recording data has been completed. In this case, the CPU 211 determines whether to record the next shot frame (determines whether continuous shooting is finished) (step S409). If continuous shooting has not ended, the determination in step S409 is NO. In this case, the flow moves to step S404. If continuous shooting has ended, the determination in step S409 is YES. In this case, the flow moves to step S401, and the imaging state transitions to the LV mode (standby) again. In the timing chart of FIG. 7, this corresponds to the period of T3.

As described above, in the present embodiment, the dividing unit 220 divides the image data input from the image sensor 201 into upper bits and lower bits according to the bit depth of pixel data. High-order bit data with a large number of bits is stored in a high-bandwidth DRAM 206-1 with a wide transmission band, and low-order bit data with a small number of bits is stored in a low-bandwidth DRAM 206-2 with a narrower transmission band than the DRAM 206-1. be. Then, the output unit 221 reads the high-order bit data stored in the high-band DRAM 206 - 1 and outputs it to the display control unit 209 . As a result, the display device 210 displays image data composed of high-order bit data. On the other hand, the output unit 221 reads and combines the high-order bit data stored in the high-band DRAM 206-1 and the low-order bit data stored in the low-band DRAM 206-2. The combined data is output to the recording control unit 207 , and the recording control unit 207 records the combined data on the recording medium 208 .

The bit depth of each pixel data of the image data displayed on the display device 210 is part of bit data obtained by dividing the bit data of the imaging data input from the imaging element 201 . Therefore, the bit depth of each pixel data of the image data displayed on the display device 210 is lower than the bit depth of each pixel data of the image data recorded on the recording medium 208 . Therefore, the image quality of the image data displayed on the display device 210 is lower than the image quality of the image data recorded on the recording medium 208 . However, the framing image for confirming the composition during continuous shooting is not required to have image quality as high as the image quality of the image data recorded on the recording medium 208 . Therefore, even image data composed of partial bit data obtained by division is sufficient as a framing image for confirming the composition during continuous shooting.

Then, the output unit 221 reads the high-order bit data stored in the high-band DRAM 206-1 and outputs it to the display control unit 209. The display control unit 209 outputs the image data composed of the high-order bit data to the display device. 210. The display device 210 displays image data composed of not all the bits of the pixel data of the imaging data input from the imaging device 201 but part of the divided high-order bit data. The image data displayed on the display device 210 is image data composed of high-order bit data. Therefore, the amount of image data read out for display (image data composed of high-order bit data) is smaller than the data amount of combined data combining high-order bit data and low-order bit data. Therefore, when displaying and recording image data, combined data having a large amount of data will not be read multiple times. Therefore, even when the imaging device 201 outputs imaging data with a large number of pixels at high speed, it is possible to speed up the display of the image data. In particular, the output unit 221 stores high-order bit data in the high-bandwidth DRAM 206-1 with a wide transmission band and reads the high-order bit data from the DRAM 206-1 when displaying the image data. Further speedup can be realized.

After the above display control, the output unit 221 reads and combines the upper bit data stored in the high band DRAM 206-1 and the lower bit data stored in the low band DRAM 206-2, and converts the combined data into It is output to the recording control unit 207 . Since the speed of the display control can be increased, the timing at which the output unit 221 starts reading the upper bit data and the lower bit data is also earlier. Therefore, the completion timing of writing data to the recording medium 208 is also earlier. Therefore, it is possible to suppress the delay between display and recording based on the captured image data.

Here, the imaging control unit 204 performs predetermined processing on the imaging data output from the imaging element 201 to generate image data, and the imaging control unit 204 performs display control without storing the image data in the DRAM 206. Output to the unit 209 can be considered. In this case, image data display processing is performed on-the-fly. In this case, if the imaging device 201 outputs image data at high speed, the operation speed of the circuit that displays and processes the image data on-the-fly is low, and the delay in displaying and recording based on the image data increases. On the other hand, the above delay can be reduced by using a circuit that performs image data display processing on the fly at high speed, but the circuit that performs image data display processing on the fly must operate at high speed. As a result, it is necessary to apply advanced hardware to the circuit, which increases the hardware cost. In the first embodiment, since image data is not processed on-the-fly, it is possible to suppress delays between display and recording based on captured image data while reducing hardware costs.

In the first embodiment, an example using a DRAM as the first memory and the second memory has been described. may apply. Also, although an example has been described in which a high-bandwidth DRAM is applied to the DRAM 206-1 and a low-bandwidth DRAM is applied to the DRAM 206-2, the transmission bandwidths of the DRAMs 206-1 and 206-2 may be the same. However, by storing the high-order bit data divided by the dividing unit 220 in the high-bandwidth DRAM 206-1, the speed of display control can be increased. For this reason, it is preferable that the high-order bit data divided by the dividing unit 220 is stored in the high-bandwidth DRAM 206-1, and the low-order bit data is stored in the low-bandwidth DRAM 206-2.

<Second embodiment>
Next, a second embodiment will be described. Since FIGS. 1 to 4 are the same as those of the first embodiment, description thereof is omitted. FIG. 8 is a timing chart when reading of recording data and writing to the recording medium 208 are not completed within one frame period. Also in the second embodiment, the same control as in the first embodiment is performed. However, when the number of pixels of the imaging data output from the imaging element 201 is large, or when the output speed of the imaging data is high, the reading of the recorded data and the writing to the recording medium 208 are performed during one frame period. It may not complete.

If the reading of the upper 8-bit data in the period T706 and the reading of the lower 4-bit data in the period T707 are not completed within one frame period, the periods T706 and T707 are applied to the next frame period. In this case, the output unit 221 cannot read the upper bit data of the next frame from the DRAM 206-1. Therefore, the display control unit 209 performs control to display the previous frame on the display device 210 or blackout control for a frame whose display cannot be read. As a result, images cannot be displayed on the display device 210 during periods T704 and T705.

FIG. 9 is a timing chart showing control timings of display data and print data when the second embodiment is applied. In the second embodiment, the output unit 221 completes reading of recording data and writing to the recording medium 208 during one frame period (during a predetermined period or less). Therefore, in periods T802 and T803, the dividing unit 220 performs crop processing for deleting part of the imaging data input from the image sensor 201 in period T801 (deleting from the readout target). In this case, the dividing unit 220 performs crop processing for cutting the top, bottom, left, and right images of the captured data within an allowable range. FIG. 10 shows an example of cropped image data (image data based on image data of all angles of view of the image sensor 201). The allowable range is the sum of a period T805 during which the output unit 221 outputs the upper bit data to the display control unit 209 and a period T808 during which the upper bit data and the lower bit data are combined and output to the recording control unit 207. It is a range within one frame period. As a result, the angle of view of the imaging data is narrowed, but the amount of data to be captured is reduced. Accordingly, the reduced upper bit data is stored in the DRAM 1206-1, and the lower bit data similarly reduced in data amount is stored in the DRAM 206-2.

Note that the data reduction is performed by dividing the imaging data into high-order bit data and low-order bit data, and then reducing each data so that the sum of the period T805 and the period T808 is within one frame period. You may

Since the data amount of the imaging data is reduced, the time for outputting the display data and the time for outputting the recording data can be reduced, and the reading of the recording data and the writing to the recording medium 208 can be performed in one frame period. It is possible to collect. This prevents the display of the next frame from being hindered. In the above, the dividing unit 220 performs crop processing, but the image sensor 201 deletes part of the captured image data, adjusts the data size of the captured image data, and sends the adjusted captured image data to the dividing unit 220. may be output. The imaging device 201 outputs the upper bit data to the display control unit 209 during a period T805 and the upper bit data and the lower bit data are combined and output to the recording control unit 207. The sum of the period T808 is one frame period. Adjust the data size to fit within the range.

Although preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and changes are possible within the scope of the gist of the present invention. The present invention supplies a program that implements one or more functions of each of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors of the computer of the system or apparatus executes the program. It can also be realized by reading and executing processing. The invention can also be implemented by a circuit (eg, an ASIC) that implements one or more functions.

200 imaging device 201 imaging device 204 imaging control unit 206 DRAM
207 recording control unit 208 recording medium 209 display control unit 210 display device 211 CPU
220 division unit 221 output unit

Claims (16)

a dividing means for dividing imaging data acquired from an imaging element into first data and second data according to bit depth;
outputting the first data read out from the first memory storing the first data to display control means for displaying an image on a display unit, and outputting the first data and the second data read out from the first memory; output means for outputting data combined with the second data read out from a second memory to a recording control means for recording on a recording medium;
An image processing device comprising: the first memory has a larger transmission band than the second memory;
2. The image processing according to claim 1, wherein said first data is data corresponding to upper bits of said imaging data, and said second data is data corresponding to lower bits of said imaging data. Device. 3. The image processing apparatus according to claim 2, wherein the number of high-order bits is greater than the number of low-order bits. The dividing means obtains imaging data from the imaging device at predetermined intervals,
4. The output means reads the first data a predetermined number of times, which is two or more, and reads the second data a number of times less than the predetermined number of times in the predetermined cycle. 1. The image processing apparatus according to claim 1. the dividing means stores the first data in the first memory and the second data in the second memory;
a period during which the output means outputs the first data read from the first memory to display control means for displaying an image on a display unit; 2. The dividing means divides the first data and the second data so that the sum of the data combined with the second data read out from the memory and the period for outputting the data to the recording control means is equal to or less than the predetermined cycle. 5. The image processing apparatus according to claim 4, wherein part of the data is deleted from the object of storage. After the display of the image on the display unit by the display control means is completed, the recording control means is controlled to start recording the combined data on the recording medium;
5. The image processing apparatus according to any one of claims 1 to 4, characterized by: an image processing apparatus according to any one of claims 1 to 6 ;
the imaging element;
the display control means;
the display unit;
the recording control means;
An imaging device comprising: The imaging device has a period during which the output means outputs the first data read from the first memory to display control means for displaying an image on a display unit, and a period during which the output means outputs the first data read from the first memory. The data size of the imaging data is adjusted so that the sum of the period for outputting the combined data of the one data and the second data read from the second memory to the recording control means is equal to or less than a predetermined period. 8. The imaging apparatus according to claim 7 , characterized by: A control method for an image processing device,
a step of dividing imaging data acquired from an imaging device into first data and second data according to bit depth;
outputting the first data read out from the first memory storing the first data to display control means for displaying an image on a display unit, and outputting the first data and the second data read out from the first memory; a step of outputting data combined with the second data read out from the second memory to a recording control means for recording on a recording medium;
A control method for an image processing device, comprising: the first memory has a larger transmission band than the second memory;
10. The image processing according to claim 9 , wherein said first data is data corresponding to upper bits of said imaging data, and said second data is data corresponding to lower bits of said imaging data. How to control the device. 11. The method of controlling an image processing apparatus according to claim 10 , wherein the number of bits of said high-order bits is greater than the number of bits of said low-order bits. Acquiring imaging data from the imaging device at predetermined intervals,
12. The method according to any one of claims 9 to 11 , wherein in the predetermined period, the first data is read a predetermined number of times equal to or more than two, and the second data is read a number of times less than the predetermined number of times. image processing device control method. storing the first data in the first memory and storing the second data in the second memory;
a period for outputting the first data read from the first memory to display control means for displaying an image on a display unit; and the first data read from the first memory and the second data read from the second memory. A part of the first data and the second data is deleted from the object of storage so that the sum of the combined data and the period for outputting the data to the recording control means is equal to or less than the predetermined cycle. 13. The method for controlling an image processing apparatus according to claim 12 . After the display of the image on the display unit by the display control means is completed, performing control to start recording the combined data on the recording medium;
13. The control method for an image processing apparatus according to any one of claims 9 to 12 , characterized in that: A program for causing a computer to execute the image processing apparatus control method according to any one of claims 9 to 14 . A computer-readable storage medium storing a program for causing a computer to execute the image processing apparatus control method according to any one of claims 9 to 14 .

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