JP6521008B2 - Imaging display device, control method of imaging display device - Google Patents

Description

The present invention relates to an imaging apparatus and a control method thereof, and more particularly to live view display.

2. Description of the Related Art Conventionally, it has been known that an image of a subject is displayed delayed from the subject in an imaging device that displays a live view. In Patent Document 1, the frame rate of the display element is set to be an integral fraction of the frame rate of the imaging element, and control is performed so that the delay time until the captured image by the imaging element is displayed on the display element becomes substantially constant. Are described (paragraphs 0038 to 0047). Also, it is described that the delay time is controlled to be less than the frame period of the imaging device (paragraph 0037).

JP, 2009-159067, A

The display screen of the display unit displays an image (live view) of an object generated based on output data of the imaging sensor, or displays information such as imaging conditions in an area different from the area for displaying the live view Various display targets can be displayed, such as the display. When the aspect ratio of the imaging sensor is the same as the aspect ratio of the display screen of the display unit and no area other than the area for displaying the image of the subject is provided on the display screen, the imaging sensor and the display unit are synchronized (shooting It is considered that it is not so difficult to display one frame in a period as long as the frame imaging cycle of the sensor. However, in the case where various display targets such as live view and information other than live view are displayed on the display screen, it is not easy to synchronize the imaging sensor and the display unit. Although Patent Document 1 describes that control is performed so that the delay time in units of frames is substantially constant, no particular mention is made of the configuration of the display screen. The present invention has been made in view of the above problems, and displays image data generated based on output data of the imaging sensor and information other than the image data in a period of the same length as the frame imaging cycle of the imaging sensor The purpose is to

An imaging apparatus for achieving the above object includes an image data generation unit, a buffer, and a display control unit. The image data generation unit generates, for each line of the display unit, image data representing an image of the subject based on output data of an imaging sensor for imaging the subject. The buffer has a capacity for accumulating a plurality of lines of generated image data. The display control unit is configured to store image data of a plurality of lines (one or more lines) in the buffer in the first display area of the display screen of the display unit including the first display area and the second display area. Is displayed in a line display cycle having a length of a or more and b or less, and display data not including image data is displayed in a line display cycle of a length in the second display area. a indicates the shortest length of the line display cycle of the display unit having a frame rate as a display capability higher than the frame rate of the imaging sensor. b indicates the longest length of a cycle in which image data for one line is generated when the imaging sensor is operating at the frame rate of the imaging sensor. The time required to generate one line of image data may vary from line to line. b refers to the longest of the variable time. And there is a relation of a <b. The first display area is an area constituted by a plurality of lines, and the width (horizontal length) is equal to the width of the display screen (horizontal length). The second display area is an area formed by a plurality of lines, and the width (horizontal length) is equal to the width of the display screen (horizontal length). Note that “frame rate as display capability” in the display unit actually displays an image of one frame when “waiting to start the display of the next display target line until the display condition is satisfied” described later. Means a frame rate that can be done. Further, the frame rate of the imaging sensor means the frame rate of the imaging sensor at the time of performing so-called live view display in which the image data generated based on the output data of the imaging sensor is displayed on the display unit.

In the case where display of the first display area is started in a state where a plurality of lines have not been accumulated in the buffer, a problem occurs when trying to display a line for which generation of image data has not been completed. By displaying the longest time (b) required for the line display cycle of the first display area one line at a time, it is possible to avoid the problem caused by displaying an ungenerated line. However, if this is done, the time required to display the first display area can not be shortened compared to the time in which the imaging sensor outputs one frame of output data. If the period required for displaying the first display area can not be shortened compared to the period in which the imaging sensor outputs one frame of output data, imaging within the same length of the frame imaging cycle of the imaging sensor In addition to the image data indicating the image of the subject generated based on the output data of the sensor, a sufficient period for displaying information other than the image data can not be provided. Therefore, in the present configuration, the display in the first display area is started after accumulation of image data for a plurality of lines is completed in the buffer. Since the image data stored in the buffer can be displayed immediately, it can be displayed with a line display cycle of the shortest length a permitted by the display unit. Therefore, for example, in the case of this configuration, the time required to display the first display area can be shortened compared to the configuration in which all the lines in the first display area are displayed with a line display cycle of length b Display delay in each line of the area can be shortened). As a result, in addition to the period for displaying the image data showing the image of the subject generated based on the output data of the imaging sensor, the period for displaying information other than the image data is the same as the frame imaging cycle of the imaging sensor Can be provided within the period of A second area for displaying information other than image data (for example, characters, graphics or still images indicating shooting conditions) indicating an image of a subject generated on the basis of output data of the shooting sensor continuously as a moving image It is called a display area.

Further, in the present configuration, in the second display area, all the lines are displayed in a line display cycle of a length, and therefore, all the lines are displayed in a line display cycle longer than a. The time required to display the can be shortened. By shortening the time required to display the second display area, the second display area is displayed in addition to the display period of the image data on the first display area within the same length of time as the frame imaging cycle of the imaging sensor. It can contribute to the achievement of the purpose of including the period. The second display area is an area for displaying display data (for example, characters and figures indicating shooting conditions and the like) which do not include image data generated based on output data of the imaging sensor. As for the shooting conditions and the like, information that can be displayed in advance is specified. Therefore, it is possible to record display data to be displayed in the second display area in the memory before the start of display, and when recording of the display data in the memory is completed, the memory is referred to with reference to the memory. Display on the display unit becomes possible by sequentially acquiring display data. For this reason, when displaying display data in the second display area, it is not necessary to provide a standby period such as waiting for each line until the generation process of the display data is completed, for example, and the shortest line display cycle in the display unit It is possible to display by length a.

As described above, the display sensor of the first display area is made one frame worth of display period by starting the display based on the image data in the first display area after the accumulation of the image data for a plurality of lines is completed in the buffer. It can be made shorter than the output data output period. The time that can be saved can be used for the display period of the second display area. In addition, since the second display area can be displayed with a line cycle of the shortest length a, the display cycle of the first display area is added in the same length as the frame imaging cycle of the imaging sensor. It is easy to include the display period of two display areas. Therefore, in the case of this configuration, information other than the image data indicating the image of the subject generated based on the output data of the imaging sensor is displayed in addition to the image data in a period of the same length as the frame imaging cycle of the imaging sensor. be able to. That is, the display of the first display area of the display unit is started after a predetermined display delay time from the output start timing of one frame of output data in the imaging sensor, and the frame imaging cycle and the frame display cycle have the same length. Shooting and display can be performed in a synchronized state. If synchronization between the two is not maintained, the display delay time (the time from the shooting by the shooting sensor to the display of the image data based on the shooting) may differ significantly from frame to frame, and the movement of the subject is not good. Because it looks natural, it is not easy to use as a live view. However, in the case of this configuration, it is possible to make the movement of the subject appear natural in the first display area, and to display the second display area in addition to the first display area in one frame.

Furthermore, in the imaging device for achieving the above object, the display control unit waits for the start of display of the next display target line until the display condition for displaying the next display target line is satisfied, After filling, the next display target line may be displayed. The processing time of the image data generation process may vary from line to line. Therefore, in the first display area, the display of the next display target line is waited until the display condition for displaying the next display target line is satisfied, and the display is performed after the display condition is satisfied. As a result, as compared with the configuration in which display is uniformly performed in the line display cycle of the same length for any line, it is possible to wait unnecessarily even though the display is ready, or a line that is not ready for display It is possible to prevent the occurrence of a defect due to displaying the Moreover, compared with the structure which displays by the line display period of the longest length b uniformly with respect to any line, this structure can shorten the time which display of a 1st display area requires.

The display condition for displaying the next display target line may be a condition indicating that the next display target line is ready to be displayed (does not cause a problem even if it is displayed), specifically Various modes can be adopted according to the internal specification of the imaging device. In addition, various configurations can be adopted according to the internal specification of the imaging apparatus also in the configuration in which the display control unit acquires the determination material for determining whether the display condition is satisfied. In addition, in the case where a phase difference of a common length is provided for each line (for example, in Japanese Patent Laid-Open No. 2007-243615, ΔT is given to each frame period in the same mode, and all lines of the image to be displayed are A common phase difference is given to the periods.
The display condition may be regarded as satisfied when the time corresponding to the phase difference has elapsed. In addition, as disclosed in Japanese Patent Application Laid-Open No. 2009-159067, in the case where a common phase difference is provided for each line, it is considered that the display condition is satisfied when the time corresponding to the phase difference has elapsed. good.

Furthermore, in the imaging device for achieving the above object, the display control unit waits for the start of display of the next display target line until the display condition for displaying the next display target line is satisfied in the first display area. If it is not necessary to display the current display target line with a line display cycle of a length. That is, when it is not necessary to stand by, the current display target line is displayed with the line display cycle of the shortest length a, and the line display cycle for rapidly displaying the next display target line may be transitioned. it can. Therefore, it can contribute to shortening of the period required for the display of a 1st display area. It is to be noted that line display in the first display area is provided by having a configuration for displaying the display target line after waiting and filling until the display condition is satisfied, and having a configuration for displaying with the shortest length a when it is not necessary to wait. The period fluctuates in the range of a or more and b or less for each line (the length b at the longest and the length b shorter than b if it does not take time as long as b).

Furthermore, in the imaging device for achieving the above object, the image data generation unit sequentially outputs the generated image data to the buffer. In addition, when the first display area is an area of m lines (m is a natural number) in which the first display area is continuous, the image data of the first line of the first display area is started to be accumulated in the buffer after the image data of the first line is started After the image data up to the eye (i is a natural number such that 1 ≦ i ≦ m) is accumulated in the buffer, the 1st to the mth lines of the first display area are based on the image data accumulated in the buffer It is displayed with a line display cycle of a length not less than b.

By starting display of the first display area in a state in which image data for the first line to the i line (for multiple lines) has already been accumulated in the buffer, at least the first line to the (i-1) line Since the image data can be displayed immediately, it can be displayed with a line display cycle of the shortest length a. Therefore, it can contribute to shortening of the period required for the display of a 1st display area.

Further, another imaging apparatus for achieving the above object includes an image data generation unit as described below, a buffer, and a display control unit. The image data generation unit generates, for each line of the display unit, image data representing an image of the subject based on output data of an imaging sensor for imaging the subject. The buffer stores the generated image data. The display control unit causes display data including the image data to be displayed in a first display area of a display screen of the display unit, and causes display data not including the image data to be displayed in a second display area of the display screen. In this configuration, the line display cycle of the display unit is shorter than the cycle in which the image data for one line is generated when the imaging sensor is operating at the frame rate of the imaging sensor. Further, in this configuration, the display control unit causes the display unit to display image data at a first frame rate higher than the frame rate of the imaging sensor after the image data for a plurality of lines is accumulated in the buffer. And displaying the first display area and the second display area at a first frame rate.

Further, in another imaging device for achieving the above object, the display control unit starts display of the next display target line in the first display area until the display condition for displaying the next display target line is satisfied. And the next display target line is displayed after the display condition is satisfied. The display control unit displays the first display area and the second display area at a second frame rate lower than the first frame rate until the image data for a plurality of lines is accumulated in the buffer.

Further, in another imaging apparatus for achieving the above object, the buffer is provided for a plurality of lines of the (N + 1) th frame while the display control unit is displaying the Nth frame at the second frame rate. Store the image data of

Further, in another imaging apparatus for achieving the above object, the display control unit performs control to display the first display area and the second display area after the image data for a plurality of lines is accumulated in the buffer. Do. Also, the buffer may be configured using the VRAM (Video RAM) as a buffer as long as the purpose of the application can be achieved.

Furthermore, as in the present invention, display data including image data is displayed in the first display area of the display screen in a line display cycle having a length of a or more and b or less, and image data is included in the second display area of the display screen. A method of displaying no display data in a line display cycle of a length is also established as an invention of a program or a method. In addition, the above-described apparatus, program, and method may be realized as a single apparatus or may be realized using a shared part in an apparatus having multiple functions, and various aspects Is included.

FIG. 2 is a block diagram showing the configuration of a photographing apparatus. (2A) is a schematic diagram which shows the read-out pixel at the time of live view mode of an imaging sensor, (2B) The schematic diagram which shows the structure at the time of live view mode of the display screen of a display part. 6 is a timing chart showing the operation of the imaging sensor and the display unit in the live view mode. (4A) and (4B) is a timing chart which shows the display timing in a display part. 7 is a timing chart showing the operation of the imaging sensor and the display unit in the live view mode according to the second embodiment. (6A) and (6B) are schematic diagrams which show the structural example of the display screen concerning other embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the attached drawings. The same reference numerals are given to corresponding components in the respective drawings, and the overlapping description will be omitted. 1. First embodiment 1-1. Configuration of Imaging Device FIG. 1 is a block diagram showing the configuration of an imaging device 1 according to an embodiment of the present invention. The imaging apparatus 1 includes an optical system 10, an imaging sensor 15, an ASIC 200, a timing control unit 30, a display unit 40, a CPU 50, a VRAM 51, an SD-RAM 52, a ROM 53, a RAM 54, and an operation unit 55. The CPU 50 can execute a program recorded in the ROM 53 by appropriately using the VRAM 51, the SD-RAM 52, and the RAM 54, and the CPU 50 can execute an object photographed by the photographing sensor 15 according to an operation on the operation unit 55 by the program. Execute a function to generate image data indicating. The operation unit 55 includes a shutter button, a dial switch as mode switching means for switching the mode, a dial switch for switching the aperture and the shutter speed, and a push button for operating various setting menus. The user can give various instructions to the photographing device 1 by operating the operation unit 55.

The optical system 10 includes a lens 11 for forming an object image on the imaging sensor 15, an aperture 12, a shutter 13, and a low pass filter 14. Among these, the lens 11 and the diaphragm 12 are exchangeably attached to a housing (not shown). The lens 11 is simplified and represented by a single lens in FIG. 1, but includes a plurality of lenses arranged in the optical axis direction, and each lens is supported at the outer edge. The low pass filter 14 prevents moiré in a captured image by blocking a spatial high frequency component in the imaging sensor 15 of imaging light. The diaphragm 12 is composed of a plurality of light shielding plates whose opening diameter can be changed. The shutter 13 is a mechanical focal plane type shutter.

The imaging sensor 15 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor including a color filter arranged in a Bayer array, and a plurality of photodiodes that accumulate charges corresponding to the amount of light for each pixel by photoelectric conversion, CCD (Charge Coupled) Device) A solid-state imaging device such as an image sensor is used. The position of the pixel of the imaging sensor 15 is defined by coordinates in the orthogonal coordinate system, and a plurality of pixels arranged in a direction parallel to one coordinate axis form a line, and a plurality of lines are arranged in a direction parallel to the other coordinate axis It is configured. In this specification, the direction parallel to the line is referred to as the horizontal direction, and the direction perpendicular to the line is referred to as the vertical direction. One screen composed of all the pixels of the imaging sensor 15 is called one frame.

The timing control unit 30 includes a sensor control unit 31 and a display control unit 32. In the present embodiment, the imaging sensor 15 operates in synchronization with various signals output from the sensor control unit 31 of the timing control unit 30. That is, the sensor control unit 31 defines a vertical synchronization signal (SVsync) that defines a period for reading out the detection result of the photodiode for one frame, and a horizontal for defining a period for reading out the detection result of the photodiode for one line. A synchronization signal (SHsync), a dot clock signal (SDotclock) defining the read timing of image data of each pixel, etc. are output. The imaging sensor 15 starts output of output data for one frame in response to the vertical synchronization signal SVsync, and one of the imaging sensors 15 at a timing according to the dot clock signal SDotclock within a period defined by the horizontal synchronization signal SHsync. Output data (SD) indicating the detection result of the photodiode corresponding to the pixel of the unit is sequentially read out.

The ASIC 200 uses the line buffers 52a to 52d for a plurality of lines secured in advance in the SD-RAM 52, and performs a process of generating image data for displaying an image of a subject by the display unit 40 by pipeline processing. And an image data generation unit 20 configured by The line buffers 52a to 52d for a plurality of lines may be provided in the image data generation unit 20 or the like. The ASIC 200 also includes an image data output unit 21. The image data output unit 21 displays image data (DD) recorded in the line buffer 52d when displaying a line belonging to a first display area R1 described later. Are output to the display unit 40 line-sequentially. As a result, the image of the subject photographed by the photographing sensor 15 is displayed in the first display area R1. When displaying a line belonging to the second display area R2, the image data output unit 21 outputs the OSD data recorded in the VRAM 51 line-sequentially to the display unit 40 as image data (DD). As a result, characters and figures such as shooting conditions are displayed in the second display area R2. The user can check the subject while using the display unit 40 as an EVF.

The display unit 40 is an EVF (Electronic View Finder) that displays an image showing a subject to be photographed and causes the user to grasp information such as the condition of the subject before photographing and photographing conditions, and the photographing according to the present embodiment. The device 1 is a mirrorless digital camera equipped with an EVF. The display unit 40 includes an interface circuit (not shown), a liquid crystal panel driver 41, a liquid crystal panel 42, an eyepiece lens (not shown) and the like. In the present embodiment, the liquid crystal panel 42 is a high temperature polysilicon TFT (Thin Film Transistor) including three sub-pixels corresponding to color filters of three colors for each pixel, and the position of the pixel is defined by coordinates in the orthogonal coordinate system. Ru. Further, a line is constituted by a plurality of pixels arranged in a direction parallel to one coordinate axis, and a plurality of lines are arranged in a direction parallel to the other coordinate axis. In this specification, the direction parallel to the line is referred to as the horizontal direction, and the direction perpendicular to the line is referred to as the vertical direction, and one screen composed of all the pixels of the liquid crystal panel 42 is referred to as one frame.

The liquid crystal panel driver 41 applies a voltage to each sub-pixel to output a signal for driving the liquid crystal to the liquid crystal panel 42. The liquid crystal panel 42 includes a gate driver and a source driver (not shown), and the gate driver controls the display timing of each pixel of each line according to the signal output from the liquid crystal panel driver 41, and the source driver displays the display timing. Display is performed by applying a voltage corresponding to the image data of each pixel to each pixel of the line. That is, the liquid crystal panel driver 41 performs various signals for displaying on the liquid crystal panel 42, for example, a vertical synchronization signal (DVsync) defining a period for displaying one frame, and displaying one line. Horizontal sync signal (DHsync) that defines the period of time, a data active signal (DDactive) that defines the capture period of image data in each line, a dot clock signal (DDotclock) that defines the timing of capture of image data of each pixel, etc. , And is configured to output image data (DD) of each pixel.

The display control unit 32 of the timing control unit 30 generates the vertical synchronization signal DVsync, the horizontal synchronization signal DHsync, the data active signal DDactive, and the dot clock signal DDotclock described above. In the present embodiment, the output timing of the horizontal synchronization signal DHsync is variable, and the output timing is determined depending on the processing result of the image data generation unit 20 as described later.

FIG. 2A is a schematic view showing readout pixels in the live view mode of the imaging sensor 15 in the present embodiment. In the live view mode, decimated readout performed in a horizontal direction and a vertical direction according to a predetermined method is performed without reading out the detection results of the photodiodes corresponding to all the pixels in the effective area of the imaging sensor 15. In the live view mode, as a result of thinning out and reading out, output data corresponding to a total of k × j pixels of k pieces in the horizontal direction and j pieces in the vertical direction are output from the imaging sensor 15 (in fact, imaging In order to output k × j pieces of output data from the sensor 15, a ring pixel for performing image processing is necessary around the effective pixel, so to output data of k pixels in the horizontal direction in FIG. Needs to read k + α pixels larger than k and j + β pixels larger than j in order to output vertical j-line data, and α pixels horizontally and β pixels vertically The output data of k × j pixels are output from the imaging sensor 15 by discarding the pixels in the image sensor 15. Here, the data of k pixels in the horizontal direction and j pixels in the vertical direction are for convenience for simplicity of description. Described as being force.). The aspect ratio k: j is different from the aspect ratio of the first display region R1 described later. Further, the number of lines j is larger than the number of lines m of the first display area R1 described later.

FIG. 2B is a schematic view showing a screen configuration in the live view mode of the display screen of the liquid crystal panel 42 in the present embodiment. In the present embodiment, the liquid crystal panel 42 is a panel provided with 1 effective pixels in the horizontal direction and (m + n) effective pixels in the vertical direction, and adjusts the content and output timing of the image data DD output by the liquid crystal panel driver 41. By this, it is possible to perform display of gradation corresponding to DD at an arbitrary position. In the present embodiment, the image of the subject is displayed based on the output data of the imaging sensor 15 in the first display area R1 which is an area of m lines from the top line of the liquid crystal panel 42, and continues to the first display area R1. Characters and figures indicating information such as imaging conditions are displayed in the second display area R2 which is an area of n lines. That is, on the liquid crystal panel 42, characters and figures indicating information such as shooting conditions are displayed on the screen together with the image of the subject. The aspect ratio l: (m + n) of the display screen of the liquid crystal panel 42 of the display unit 40 is, for example, 4: 3. The aspect ratio l: m of the first display region R1 is, for example, 3: 2.

In addition, when the user operates the operation unit 55 to issue an imaging instruction, the imaging sensor 15 starts output data output for one frame in response to the vertical synchronization signal SVsync in response to the imaging instruction. Output data indicating the detection results of the photodiodes corresponding to all effective pixels of the imaging sensor 15 is sequentially read out at a timing according to the dot clock signal SDotclock within a period defined by the synchronization signal SHsync. Then, the image data generation unit 20 generates image data of a format such as JPEG using the SD-RAM 52 and the like, and is recorded in a removable memory (not shown) and the like. That is, the user can generate image data indicating a subject.

1-2. Live View Display FIG. 3 is a timing chart showing the operation of the imaging sensor 15 and the display unit 40 in the live view mode. In the live view mode, the imaging sensor 15 outputs output data of one frame in a vertical synchronization period Tsv (frame imaging period) defined by the vertical synchronization signal SVsync. More specifically, the output data SD for one line of the imaging sensor 15 is output in the horizontal synchronization period (line imaging cycle) defined by the horizontal synchronization signal SHsync during the vertical synchronization period Tsv. The output data SD is temporarily recorded in the line buffer 52a. In the live view mode, the display unit 40 updates the display of one frame in the vertical synchronization period Tdv (frame display period) defined by the vertical synchronization signal DVsync. More specifically, the display of one line of the display unit 40 is updated in the horizontal synchronization period (line display cycle) defined by the horizontal synchronization signal DHsync during the vertical synchronization period Tdv.

A procedure for generating the image data DD based on the output data SD output from the imaging sensor 15 will be described with reference to FIG. When the output data SD is output from the imaging sensor 15 to the line buffer 52a, the image data generation unit 20 acquires the output data SD output from the imaging sensor 15 from the line buffer 52a. The pixel interpolation unit 20a performs interpolation processing using the tone values of the peripheral pixels of the target pixel for the target pixel, so that the two channels different from the color of the color filter provided in the photoelectric conversion element corresponding to each pixel Calculate the tone value of the color of. As a result, data in which gradation values of three channels are associated with each pixel is generated. The color reproduction processing unit 20b performs color conversion processing for reproducing a more correct color by performing a 3 × 3 matrix operation on the gradation value of each pixel of the data for which pixel interpolation has been completed.
Data generated by the color conversion process is temporarily recorded in the line buffer 52b.

The filter processing unit 20c performs filter processing such as sharpness adjustment and noise removal processing on the data temporarily recorded in the line buffer 52b after the color reproduction processing is completed. The gamma correction unit 20d performs processing to correct gradation characteristics at the time of image output. That is, gamma correction is performed on the data for which the filter processing has been completed, in which the color indicated by the tone value of the output data of the imaging sensor 15 is corrected by the gamma function according to the color characteristic in the display unit 40. The data after gamma correction processing is temporarily recorded in the line buffer 52c. The resize processing unit 20 e sequentially resizes the data after gamma correction processing temporarily recorded in the line buffer 52 c to a target size by referring to the data. In this embodiment, resizing is performed to the size of the first display area R1 shown in FIG. 2B. When resizing is completed in the resizing processing unit 20e, image data DD in which each image processing in the ASIC 200 is completed can be generated. The image data DD generated after the resizing process is temporarily recorded in the line buffer 52d. The line buffer is a FIFO type line buffer, and image data is read out line by line in the order of the image data recorded previously.

By the way, in order to perform display on the liquid crystal panel 42 by minimizing the delay period based on the output data output line-sequentially from the imaging sensor 15, in the present embodiment, display is performed on each line of the liquid crystal panel 42. The horizontal synchronization signal DHsync for displaying the line is output after the display conditions for the display are satisfied. Specifically, the display control unit 32 of the timing control unit 30 acquires, from the resize processing unit 20e, the line number Ld for which the generation processing of the image data in the resize processing unit 20e is completed and the output is completed in the line buffer 52d. Is possible. That is, the line number Ld means that the line before the line number indicated by Ld (the line from the first line to the Ld line) may be displayed. Since the image data is generated line by line, it means that image data of a line having a number smaller than the line number in one frame has already been generated and has been output to the line buffer 52d. Therefore, if the number Ln of the next display target line is equal to or less than Ld, the display condition for displaying the next display target line is satisfied. The line buffer 52d has a size capable of recording image data of at least m lines.

Therefore, the display control unit 32 of the timing control unit 30 outputs the horizontal synchronization signal DHsync in synchronization with the timing when the display condition is satisfied for each line, thereby starting the display of the line satisfying the display condition in the liquid crystal panel 42 To make it According to this configuration, display of each line is not started before preparation of image data is completed, and each line can be displayed immediately when display of each line is ready.

The value of the number Ln of the next display target line is counted up each time the display control unit 32 displays one line. The range of the value of the number Ln of the next display target line is 1 ≦ Ln ≦ (m + n). The value of the line number Ld is counted up by the resize processing unit 20e every time the output of the image data is completed in the line buffer 52d, and notified to the display control unit 32. The range of the line number Ld is 0 ≦ Ld ≦ m. When the value of Ld is 0, it means that no image data has been output to the line buffer 52d for one line in one frame. When the value of Ld becomes m (Ld = m), the frame data output completion flag Ldf flag is turned on, and the value of Ld is reset to 0 (Ld = 0). Even if Ld = 0, the period of Ldf flag = On means that all the image data of the first display area R1 has been output to the line buffer 52d, so the display side displays the next display target line number Ln. You may display The Ldf flag is reset when it is determined that the display of the m-th line is completed, and the Ldf flag returns to Off.

The operation will be described in detail with reference to FIG. In FIG. 3, after the vertical synchronization signal SVsync is output from the sensor control unit 31 at timing p1, the output data of the first line of the imaging sensor 15 is acquired at timing p2 when a period Tsv0 of a predetermined length has elapsed. The horizontal synchronization signal SHsync is output from the sensor control unit 31. When the output data of the first line of the imaging sensor 15 is output to the line buffer 52a, pipeline processing is performed by the image data generation unit 20 as described above, and the image data DD after the line resizing processing is line buffer 52d. Output and accumulated. ΔT1 means the time required at least from the start timing p2 of the output period of output data for one frame in the imaging sensor 15 to the display start of the first line of the first display region R1 of the display unit 40. The pipeline processing and the like by the image data generation unit 20 are included in ΔT1.

FIG. 4A is a timing chart showing display timing in the vertical synchronization period Tdv of the frame D1 of the display unit 40 shown in FIG. In the frame D1 corresponding to the first frame after the start of the live view mode, when the display condition of the image data of the first line is satisfied, the image data of the first line is displayed immediately without waiting. Therefore, when confirming that the value of the line number Ld is equal to the number Ln (= 1) of the next display target line, the display control unit 32 outputs the horizontal synchronization signal DHsync for displaying the first line (timing (timing) p3) The image data DD of the first line is displayed. Similarly, when it is confirmed that the display condition is satisfied, the display control unit 32 outputs and displays the horizontal synchronization signal DHsync. The length of the cycle in which the value of the line number Ld is updated is equal to the length of time required to generate image data for one line. Since the time required to generate image data for one line changes, the length of the cycle in which the value of the line number Ld is updated also changes. Line number L
Let b be the longest length of the cycle in which d is updated. For example, FIG. 4A shows that the length of the period in which the value of the line number Ld is 1 is b, this means that the generation of the image data of the first line is completed and the output to the line buffer 52d is This means that the time from the completed timing p3 to the timing p3 '' at which the generation of image data of the second line is completed and the output to the line buffer 52d is b is the longest length. Since the display control unit 32 waits until the next display target line number Ln ≦ line number Ld and outputs the horizontal synchronization signal DHsync according to the timing when Ln ≦ Ld, the horizontal synchronization period (line display The longest length of cycle) is also b. The display control unit 32 may confirm that the value of the line number Ld has changed from 0 to 1, and then may generate the vertical synchronization signal DVsync for starting the frame D1.

Specifically, the display control unit 32 outputs the horizontal synchronization signal DHsync at timing p3 and then synchronizes with the dot clock signal DDotclock (not shown) to display image data of one line for each pixel. The display of the image data for one line is already finished at timing p3 'at which the time of length a has elapsed from timing p3, and the value of the number Ln of the next display target line is 2. However, since the value of the line number Ld is still 1 at the timing p3 ', the display control unit 32 extends the length of the front porch period Tdh2 of the line display cycle of the first line which is the current display target line to Ln. It waits for the output of the horizontal synchronization signal DHsync for displaying the next display target line until ≦ Ld. Specifically, for example, the length of the front porch period Tdh2 is extended by generating a dummy dot clock signal DDotclock or extending the period of the dot clock signal DDotclock. When it is not necessary to wait until the display condition for displaying the next display target line is satisfied in the first display region R1, the line display cycle of the current display target line is finished with the shortest length a. For example, in the cycle of displaying the m-th line in FIG. 4A, it is not necessary to wait until the display condition of the (m + 1) -th line which is the next display target line is satisfied, as described later. The length of the line display cycle of a certain m-th line is the shortest length a. Specifically, in the cycle of displaying the m-th line in FIG. 4A, the frame data output completion flag Ldf flag is set to On. Since all image data in the first display area R1 has been completely output to the line buffer 52d during the Ldf flag = On period, the display side may display the number Ln of the next display target line, and the mth line may be displayed. The length of the displayed period is the shortest length a. As described later, the length of the display cycle of the (m + 1) line to the (m + n) line is also the shortest length a.

As shown in FIG. 2, the output data for j lines of the imaging sensor 15 is resized to image data for m lines by the resizing unit 20e. Therefore, as shown in FIG. 4A, during a period Tdv1 from the start timing p3 of the horizontal synchronization period for displaying the image data of the first line to the end timing p6 of the horizontal synchronization period for displaying the image data of the mth line, The display on the image data for m lines, ie, the first display area R1 is completed. As shown in FIG. 4A, when the display data of one line is generated and output to the line buffer 52d and the operation of displaying the line is repeated, as shown in FIG. 3, the first display area R1 in the frame D1. The length of the display period Tdv1 is substantially equal to the length of the period Tsv1 for outputting output data for one frame (output data for j lines).

After the display in the first display area R1 is completed, the m + 1st and subsequent lines become the display in the second display area R2. Here, the frame rate Fdmax as the display capability of the display unit 40 is higher than the frame rate Fs of the imaging sensor 15 (Fdmax> Fs). That is, when driving the display unit 40 at the frame rate Fdmax without waiting for the output of the horizontal synchronization signal DHsync until the display condition is satisfied, the vertical synchronization period (frame display cycle) of the display unit 40 is the imaging sensor 15 Shorter than the vertical synchronization period (frame imaging cycle) of Further, the length of the horizontal synchronization period when driving the display unit 40 at the frame rate Fdmax (that is, the shortest length of the line display cycle allowed in the display unit 40) a drives the imaging sensor 15 at the frame rate Fs. In this case, it is shorter than the longest length b of the cycle in which image data of one line is generated (a <b).

Data (OSD data) such as characters and figures indicating information such as shooting conditions to be displayed in the second display area R2 and still images other than live view are independent information regardless of the operation of the shooting sensor 15, It is possible to create and record in the VRAM 51. Alternatively, it is possible to create OSD data and still images as needed and record them in the VRAM 51 independently of live view display. Therefore, even if the display based on the OSD data or the still image is performed by the short horizontal synchronization period, it is possible to perform the proper display without causing overtaking of the data reading. Therefore, when displaying the OSD data in the second display area R2, the second line display cycle (horizontal synchronization period) has a length shorter than b and the shortest length a allowed in the display unit 40. Each line of the display area R2 is displayed.

As shown in FIG. 4A, the display control unit 32 outputs DHsync at a line display cycle of length a for the (m + 1) th line to the (m + n) th line, and outputs 1 for a line display cycle of length a. Display OSD data line by line. As a result, it is possible to display the second display region R2 in a period Tdv2 of a shorter length than when displaying the (m + 1) th to (m + n) th lines in a line display cycle longer than a. As shown in FIG. 3, after the display period Tdv2 of the second display area R2 ends at timing p7 and the front porch period Tdv3 of the frame D1 elapses, the display control unit 32 outputs the vertical synchronization signal DVsync. As shown in FIG. 3, the vertical synchronization period Tdv of the frame D1 includes a back porch period Tdv0, a display period Tdv1 of the first display region R1, a display period Tdv2 of the second display region R2, and a front porch period Tdv3. The vertical synchronization period Tsv of the imaging sensor 15 is composed of a period Tsv0 of a predetermined length, an output period Tsv1 of one frame, and a period Tsv2 of a predetermined length. The length of the output period Tsv1 of the frame S1 is substantially equal to the length of the display period Tdv1 of the first display region R1 of the frame D1 (the sensor has an extra output period peculiar to the sensor) and is not exactly equal. Despite the fact, the second display area R2 must still be displayed in the frame D1, and the front porch period Tdv3 must also be included in the frame D1. However, the length of (period Tdv2 + period Tdv3) is longer than the length of the remaining period Tsv2 of the vertical synchronization period Tsv of the imaging sensor 15. Therefore, in the frame D1, the vertical synchronization period Tdv of the display unit 40 is longer than the length (1 / Fs) of the vertical synchronization period Tsv of the imaging sensor 15.

Therefore, in the frame D2 immediately after the frame D1 in which the vertical synchronization period Tdv of the display unit 40 is longer than the length (1 / Fs) of the vertical synchronization period Tsv of the imaging sensor 15, the timing when ΔT1 has elapsed from timing p5 At p8, it is not possible to start the display of the first display area R1 of the next frame (in FIG. 3, timing p8 is still in the period of the previous frame D1). Compared with the fact that the display of the first display area R1 can be started at timing p3 when ΔT1 has elapsed from the timing p2 in frame D1, the display start timing of the first display area R1 is frame D1 and the frame D2 is further ΔT2. It will be late. On the other hand, after the timing p8 when ΔT1 has elapsed from the start timing p5 of the output period Tsv1 of the frame S2, the image data of the first and subsequent lines starts to be output to the line buffer 52d. Image data of the first line to a plurality of lines (here, i lines, i is a natural number of 1 ≦ i ≦ m) is already output to the line buffer 52 d in a period of ΔT2 from timing p8 to timing p9. (That is, ΔT2 can also be reworded as the time required to accumulate image data for i lines from the first line in the line buffer 52d). Therefore, as shown in FIG. 4B, the value of the line number Ld is i at timing p9.

As shown in FIG. 4B, at timing p9, that is, at timing p9 where the number Ln of the next display target line is 1 and the value of the line number Ld is i, the display condition (Ln ≦ Ld) is satisfied. In, the display control unit 32 outputs DHsync for displaying the first line, and displays the first line with the shortest length a. Also in the second and subsequent lines, when it is not necessary to extend the line display cycle longer than a and wait until the display condition (Ln ≦ Ld) is satisfied, the horizontal synchronization signal DHsync is output with a cycle of the shortest length a. Since the cycle in which the value of the line number Ld is updated is longer than a, while outputting the horizontal synchronization signal DHsync at a cycle of a length, a timing at which the display condition is not satisfied, that is, Ln> Ld occurs. sell. For example, after the horizontal synchronization signal DHsync for displaying the (m-1) th line is output at the timing p10 shown in FIG. 4B, the number Ln of the next display target line is Although it is m, since the value of the line number Ld is still (m-1), Ln> Ld. In that case, the display control unit 32 waits for the output of the horizontal synchronization signal DHsync until Ln ≦ Ld, and after Ln ≦ Ld, outputs the horizontal synchronization signal DHsync (timing p12).

After the horizontal synchronization signal DHsync for displaying the final line of the first display area R1 is output at timing p12, the second display area R2 is displayed in the same manner as described above. That is, display is performed in a cycle of a length for each line. As described above, in the first display area R1 of the frame D2, when the display of the first line is started, the image data for the first line to the i line is already accumulated in the line buffer 52d and the shortest length There can be at least (i-1) lines which can be displayed in the line display cycle of a. Therefore, the length of the display period Tdv1 'of the first display area R1 of the frame D2 is such that only the image data of the first line is accumulated in the line buffer 52d when the display of the first line is started like the frame D1. The length is shorter than the length of the display period Tdv1 of the first display region R1 in the case (see FIG. 3). In the display period Tsv2 of the second display region R2, neither the number of lines (n line) nor the horizontal synchronization period (length a) changes, so the length is the same in any frame.

As a result, the vertical synchronization period Tdv 'of the frame D2 is shorter than the vertical synchronization period Tdv of the frame D1. Also, in the frame D2, if the following equation (1) is satisfied, the vertical synchronization period Tdv ′ of the frame D2 can be made the same length as the vertical synchronization period Tsv of the imaging sensor 15. Length of display period Tdv1 ′ ≦ (length of vertical synchronization period Tsv of photographing sensor 15) − (length of period Tdv0 + length of period Tdv2 + reference length of period Tdv3) (1) Formula (1) It is obvious that the vertical synchronization period Tdv 'of the frame D2 has the same length as the vertical synchronization period Tsv of the imaging sensor 15 in the case where the left side of) equals the right side of the equation (1). Also in the case where the left side of equation (1) <the right side of equation (1), the front porch period Tdv3 of frame D2 should be extended beyond a predetermined reference length (for example, a dummy horizontal synchronization signal DHsync is generated). And the vertical synchronization period Tdv 'of the frame D2 is made the same length as the vertical synchronization period Tsv of the imaging sensor 15 by lengthening one or more horizontal synchronization periods during the front porch period Tdv3). it can.

The length of the display period Tdv1 ′ of the first display region R1 of the frame D2 is influenced by the number of lines accumulated in the line buffer 52d at timing p9. The number of lines may be the number of lines that satisfy the equation (1). As described above, the image data of the line stored in the line buffer 52 d in the first display area R1 is displayed with the shortest length a of the line display cycle in the display unit 40 (image data of the line not stored is the display condition The display period of the first display area R1 can be shortened than the period Tsv1 by waiting until the display condition is satisfied and then displaying the display condition. Further, by displaying all the lines with the shortest length a in the second display region R2, it is possible to shorten the time required for display as compared to the case where all the lines are displayed in a cycle longer than a. As a result, display data such as OSD can be displayed in addition to the image data based on the output data of the imaging sensor 15 during the same length of time as the vertical synchronization period Tsv of the imaging sensor 15. And can be operated synchronously. Even after the frame following the frame D2, the time difference (display delay time) between the start timing of the output period Tsv1 of the imaging sensor 15 and the start timing of the display period Tdv1 'of the first display region R1 of the display unit 40 is ΔT1 + ΔT2 The imaging sensor 15 and the display unit 40 can be operated in synchronization with each other. The time difference (display delay time) between the start timing of the output period Tsv1 of the imaging sensor 15 and the start timing of the display period of the first display area R1 of the display unit 40 from the first frame after the live view mode starts is ΔT1 + ΔT2. The operation timing of the display unit 40 may be controlled so that That is, in the example using FIG. 3, it has been described that control is performed so that the time difference becomes ΔT1 + ΔT2 from two frames onwards, but it is needless to say that control may be performed so that the time difference becomes ΔT1 + ΔT2 from the first frame.

Thus, the length of the frame display cycle changes in accordance with the change in phase difference (.DELTA.T1 in frames S1 and D1, but .DELTA.T1 + .DELTA.T2 in frames S2 and D2). By temporarily changing the frame display cycle, synchronization between the imaging sensor 15 and the display unit 40 can be realized in a subsequent frame.

In addition, since the length a of the shortest line display cycle is shortened as the frame rate Fdmax is higher, the length of the display period of the second display area R2 can be shortened. As a result, the phase difference between the imaging sensor 15 and the display unit 40 also decreases, and the display delay time also decreases. Further, by reducing the phase difference, it is possible to reduce the capacity of the buffer for storing the image data of the first display area R1 of the next frame. Further, as the shortest length a of the line display cycle is shorter than the longest length b of the cycle in which the image data of one line is generated, the display delay time can be shortened. Although the display delay time in the next frame becomes longer as the number of lines in the second display area R2 increases, the image data of the first display area R1 of the next frame is accumulated as the shortest length a of the line display cycle becomes shorter. The buffer capacity can be reduced, and the display delay time can also be shortened.

2. Second Embodiment FIG. 5 is a timing chart showing the operation of the imaging sensor and the display unit in the live view mode according to a second embodiment. In the frame DD1, the display of the first display area R1 is not started until the image data of a plurality of lines is accumulated in the line buffer 52d, and the image data of the first line of the first display area R1 is stored in the line buffer 52d. As soon as the image data is output, the image data of the first line is displayed, and thereafter, the display is performed each time the image data of one line is output to the line buffer 52d. This is the same operation content as the frame D1 of FIG. 3 in the first embodiment. As a result, similarly to the frame D1 of FIG. 3, the length of the frame display period (vertical synchronization period) Tdv of the frame DD1 of FIG. 5 of the second embodiment is greater than the frame imaging period (vertical synchronization period) Tsv of the imaging sensor 15. It also gets longer. That is, the frame rate (second frame rate) when the length of the frame display period Tdv of the frame DD1 continues as it is is lower than the frame rate of the imaging sensor 15.

Here, after the display period Tdv1 of the first display region R1 of the frame DD1 and the display period Tdv2 of the second display region R2 are finished, it is assumed that the vertical synchronization signal DVsync for starting the frame DD2 is generated delayed for some reason. Do. That is, it is assumed that the vertical synchronization signal DVsync is output at timing q9 slightly behind timing q8 when the front porch period Tdv3 of the frame DD1 ends. Since the output of the vertical synchronization signal DVsync for starting the frame DD2 is slightly delayed, vertical synchronization is performed at the start timing q10 of the display period Tdv1 'of the first display region R1 of the frame DD2 after the back porch period Tdv0 of the frame DD2. As compared with the case where the signal DVsync is not delayed and generated at timing q8, image data of many lines are accumulated in the line buffer 52d. That is, the number of lines stored at timing q10 when a period ΔT3 has elapsed after the time ΔT1 (period required to generate the image data of the first line) has elapsed from the timing q5 at which output of output data of one frame SS2 starts. Is greater than the number of accumulated lines at a timing (not shown) when a period shorter than .DELTA.T3 has elapsed after the period .DELTA.T1 from the timing q5.

Therefore, as compared with the case where the vertical synchronization signal DVsync is generated without delay and is generated at timing q8, the number of lines that can be displayed in the line display cycle of the shortest length a increases, so display of the first display area R1 in frame DD2 The length of the period Tdv1 'becomes short. The length of the display period Tdv2 of the second display area R2 is the same as that of the frame DD1. Assuming that the vertical synchronization signal DVsync for starting the frame DD3 is generated at timing q11 when the front porch period Tdv3 passes without delay, the length of the frame display period Tdv 'of the frame DD2 is the frame imaging cycle of the imaging sensor 15. It becomes shorter than the length of Tsv. That is, the frame rate (first frame rate) when the length of the frame display period Tdv 'of the frame DD2 continues as it is is higher than the frame rate of the imaging sensor 15. Since the frame rate of the imaging sensor 15 and the frame rate of the display unit 40 can be equalized after the frame DD3 as in the first embodiment, the description will be omitted.

Further, image data of a plurality of lines of the frame DD2 (the (N + 1) -th frame) can be accumulated in a period in which the frame DD1 (the N-th frame) is displayed at the second frame rate. That is, part of a period ΔT3 in which image data of a plurality of lines of the first display area R1 of the frame DD2 is stored is included in the frame display period Tdv of the frame DD1. Further, as shown in the frame DD2, after the image data for a plurality of lines is accumulated (after the period ΔT3), the display of the first display area R1 and the second display area R2 is performed.

3. Other Embodiments The technical scope of the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the present invention. For example, in the above embodiment, with regard to the determination of the display condition, the display control unit 32 acquires from the resize processing unit 20e the line number Ld for which the generation process of the image data is completed and the output is completed in the line buffer 52d. Although the structure which judges that display conditions are satisfy | filled when the relationship with (Ln <= Ld) is employ | adopted, various other embodiment is considered. For example, the image data generation unit outputs a pulse signal to the display control unit at a timing when generation of image data for one line is completed and output to a predetermined buffer is completed, and the display control unit outputs a pulse signal in one frame The counted number may be counted, and it may be determined that the display condition is satisfied if the line number indicated by the number is equal to or more than the number of the next display target line.

Further, for example, the image data generation unit counts up the counter at the timing when the processing of the resize processing unit is completed and the image data of the Nth line is generated, and the value of the counter is set to N. The image data generation unit outputs a pulse signal to the display control unit at the timing when the counter is counted up to notify that the counter has been counted up. The display control unit acquires the value of the counter indicating the line on which the generation of the image data is completed (indicating to what line the generation is completed) at the timing of acquiring the pulse signal. The display control unit may determine that the display condition is satisfied if the number of the next display target line is equal to or less than the value of the counter.

The screen configuration of the display unit 40 is not limited to the configuration adopted in the first embodiment. For example, as shown to FIG. 6A, 1st display area R1 and 2nd display area R2 may be reverse to 1st embodiment. That is, an area for n lines from the first line of the display screen is the second display area R2 for displaying the OSD data, and an area for m lines following the second display area R2 is based on the output data of the imaging sensor 15. It may be the first display area R1 for displaying the generated image data. In this case, the second display area R2 is displayed with a line display cycle of length a as in the above embodiment. Since image data of several lines to be displayed in the first display area R1 is accumulated in the line buffer 52d during the period in which the second display area R2 is displayed, the lines in the first display area R1 have already been accumulated in the line buffer 52d. Can be displayed in a line display cycle of the length a, and the display period of the first display area R1 can be shortened as in the above embodiment. As a result, display data such as OSD can be displayed in addition to the image data based on the output data of the imaging sensor 15 during the same length of time as the vertical synchronization period of the imaging sensor 15, and the imaging sensor 15 and the display unit 40 Can be synchronized. In the above embodiment, the first display area is an area constituted by a plurality of lines, and the width (horizontal length) is equal to the width of the display screen (horizontal length), but is shorter than the width of the display screen It is good.

Further, in the first embodiment and the example of FIG. 6A, the image data generated based on the output data of the imaging sensor 15 is displayed over the entire width in the horizontal direction of the display screen. As indicated by 101, the width of the area in which the image data generated based on the output data of the imaging sensor 15 may be displayed may be narrower than the width of the display screen. In the case of the example of FIG. 6B, an area (the width is the same as the width of the display screen) formed of lines including the live view image display area 101 is generated based on the first display area R1 (output data of the imaging sensor 15). It is an area for displaying display data including image data, and the other area (the width is the same as the width of the display screen) includes the image data generated based on the output data of the second display area R2 (the output data of the imaging sensor 15). Not display data). Display data of areas other than the live view image display area 101 (display areas of the histograms 1, 2, 3 and display areas such as shooting information and background areas other than them) are created and stored in the VRAM 51. The image data output unit 21 acquires image data from the line buffer 52 d when displaying the live view image display area 101, and acquires data from the VRAM 51 and outputs the data to the display unit 40 when displaying the other area. . Since the first display area R1 includes the live view image display area 101, it can be displayed with the shortest length a if image data for a plurality of lines are accumulated in the line buffer 52d, but until the display condition is not satisfied You need to wait for the display. Therefore, the first display area R1 is displayed in a line display cycle having a length of a or more and b or less. On the other hand, the second display area R2 can be displayed with a line display cycle of length a.

Note that even in the case where the screen configuration (layout) is changed during the live view mode (when the arrangement and ratio of the first display area R1 and the second display area R2 are switched), the above embodiment is described. Configuration (a buffer for storing a plurality of lines of image data of the first display area, and a configuration for displaying the stored image data and the display data of the second display area R2 with a length a shorter than b) Thus, the photographing sensor 15 and the display unit 40 can be synchronized after one frame has passed at the shortest. That is, even if the screen configuration is switched in the live view mode, the synchronization between the imaging sensor 15 and the display unit 40 can be stably realized at least two frames after switched.

In the first embodiment, when Fdmax> Fs and a <b, an embodiment in which the imaging sensor 15 and the display unit 40 operate in synchronization with each other has been described. However, the imaging sensor when Fdmax = Fs It is of course possible to operate the display unit 40 and the display unit 40 in synchronization. For example, if the display is started from the first line of the first display area R1 after the accumulation of the image data for m lines to be displayed in the first display area R1 in the line buffer 52d is completed, the length of the first display area R1 The display of m lines can be performed in the line display cycle of a (since it is not necessary to wait until the display condition is satisfied for any line). In this case, the length a may not necessarily be shorter than the length b, and may be, for example, a = b. Further, in the second display area R2, as in the first embodiment, it is possible to display n lines in a line display cycle of the length a using OSD data recorded in the VRAM 51. As described above, if the frame rate Fdmax of the display unit 40 in the case of outputting the horizontal synchronization signal DHsync in a line display cycle of the length a is the same as the actual frame rate Fs of the imaging sensor 15, the lengths of the vertical synchronization periods are equal. As a matter of course, synchronization between the imaging sensor 15 and the display unit 40 is possible. However, in the case of this example, after the image data for m lines of the first display area R1 is accumulated in the line buffer 52d, the display from the first line of the first display area R1 is started. The display delay time from when the output data of the line is output to when the display of the first display area R1 is started is longer than that of the first embodiment. Therefore, in order to keep the display delay time as short as possible and to synchronize the imaging sensor 15 and the display unit 40, it is desirable that the first embodiment has Fdmax> Fs and a <b.

DESCRIPTION OF SYMBOLS 1 ... imaging device, 10 ... optical system, 11 ... lens, 13 ... shutter, 14 ... low pass filter, 15 ... imaging sensor, 20 ... image data generation part, 20 ... image data generation part, 20a ... pixel interpolation part, 20b ... Color reproduction processing unit, 20c: filter processing unit, 20d: gamma correction unit, 20e: resize processing unit, 21: image data output unit, 30: timing control unit, 31: sensor control unit, 32: display control unit, 40 ... Display unit 41 Liquid crystal panel driver 42 Liquid crystal panel 50 CPU 51 VRAM 52 SD-RAM 52a to 52d Line buffer 53 ROM 54 RAM 55 Operation unit 101 Live view image display area, R1 ... first display area, R2 ... second display area

Claims (4)

An imaging sensor for imaging an object and outputting imaging data for one frame at a first frame rate;
And on the basis of the output imaging data from the imaging sensor, generates image data for display, image data generating unit the period in which the image data is generated for one line that increase or decrease,
An accumulation unit that accumulates the generated image data;
A display unit for displaying the image data stored in the storage unit;
A display control unit that controls the display unit;
Equipped with
The display control unit
In the case where the length of the horizontal synchronization period of each line of the display unit is driven at a second frame rate higher than the first frame rate according to increase or decrease of a cycle in which the image data for one line is generated . The length of any horizontal synchronization period is controlled from the length of the horizontal synchronization period to the length of the horizontal synchronization period when driving at a third frame rate lower than the first frame rate,
The image pickup display device, wherein a frame rate when displaying one frame in the display unit is set to be higher or lower than the first frame rate in accordance with control of a length of a horizontal synchronization period of each line. An imaging sensor for imaging an object and outputting imaging data for one frame at a first frame rate;
An image data generation unit that generates display image data based on the imaging data output from the imaging sensor and increases or decreases a cycle in which the image data of one line is generated ;
An accumulation unit that accumulates the generated image data;
A display unit for displaying the image data stored in the storage unit;
A display control unit that controls the display unit;
Equipped with
The display control unit
The length of the horizontal synchronization period of each line of the display unit is set to a second frame rate higher than the first frame rate and the first frame rate with an increase or decrease of a cycle in which the image data of one line is generated . Control the length of any horizontal sync period up to the length of the horizontal sync period when driving at frame rate,
The image pickup display device, wherein a frame rate at the time of displaying one frame on the display unit is made higher than the first frame rate in accordance with control of a length of a horizontal synchronization period of each line. An imaging sensor for imaging an object and outputting imaging data for one frame at a first frame rate;
An image data generation unit that generates display image data based on the imaging data output from the imaging sensor and increases or decreases a cycle in which the image data of one line is generated ;
An accumulation unit that accumulates the generated image data;
A display unit for displaying the image data stored in the storage unit;
And a display control unit configured to control the display unit .
The display control unit is a second frame in which a length of a horizontal synchronization period of each line of the display unit is higher than the first frame rate according to increase or decrease of a cycle in which the image data of one line is generated. The length of any horizontal synchronization period from the length of the horizontal synchronization period in the case of driving at a rate to the length of the horizontal synchronization period in the case of driving at a third frame rate lower than the first frame rate ,
In the image pickup display apparatus, the frame rate at the time of displaying one frame on the display unit is made higher or lower than the first frame rate according to increase or decrease of the length of the horizontal synchronization period of each line. Control method. An imaging sensor for imaging an object and outputting imaging data for one frame at a first frame rate;
An image data generation unit that generates display image data based on the imaging data output from the imaging sensor and increases or decreases a cycle in which the image data of one line is generated ;
An accumulation unit that accumulates the generated image data;
A display unit for displaying the image data stored in the storage unit;
And a display control unit configured to control the display unit .
The display control unit determines the length of the horizontal synchronization period of each line of the display unit from the first frame rate to the first frame according to increase or decrease of a cycle in which the image data for one line is generated. Control the length of any horizontal synchronization period up to the length of the horizontal synchronization period when driving at a second frame rate higher than the rate,
A control method of an image pickup display apparatus, wherein a frame rate at the time of displaying one frame on the display unit is made higher than the first frame rate in accordance with the control of the length of the horizontal synchronization period of each line. .

Images