JP2020005097A - Image processing apparatus, imaging apparatus, control method for image processing apparatus, program, and storage medium - Google Patents

Abstract

To provide an image processing apparatus that suppresses delay between display and recording on the basis of image data captured by an imaging element, an imaging apparatus, a control method for the image processing apparatus, a program, and a storage medium.SOLUTION: An image processing apparatus includes division means that divides imaging data obtained from an imaging element into first data and second data according to a bit depth, and output means that outputs the first data read from a first memory storing the first data to display control means that displays an image on a display unit, and outputs data obtained by combining the first data read from the first memory the second data read from the second memory storing the second data to recording control means for recording on a recording medium.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an image processing apparatus, an imaging apparatus, a control method of an image processing apparatus, a program, and a storage medium for displaying and recording image data captured by an image sensor.

  2. Description of the Related Art In recent years, imaging devices such as digital cameras have remarkably increased the number of pixels, increased the continuous shooting frame speed of still images, and improved the moving image frame rate, and the data processing amount per unit time has increased. An image processing device inside an imaging device such as a digital camera performs a process (capture) of writing data captured by an imaging device to a memory such as a DRAM. The image processing apparatus reads the data written in the memory, performs image processing, records the image processed image on a medium or the like, and displays the image currently stored in the memory on the rear liquid crystal display of the imaging apparatus. To display. In recent mirrorless cameras and the like, instead of the optical viewfinder, the imaging device displays the data currently stored in the memory at the electronic viewfinder.

  For example, when the continuous shooting frame speed of a still image becomes higher, the output speed at which the image sensor outputs image data becomes higher. When the output speed of the imaging data increases, the amount of data processing per unit time during the above-described capture increases, and the amount of data accessible to the DRAM (hereinafter, transmission band) approaches the limit. When the transmission band of the DRAM approaches the limit, data captured in the DRAM cannot be read at the same time, and display output cannot be performed. When the captured data cannot be displayed and output, the display may be blacked out, and the display of the latest captured image may be continuously displayed. For this reason, at the time of photographing, it has hindered the photographer from continuing to frame. To solve the above problems, a technique disclosed in Patent Document 1 has been proposed. An image processing apparatus according to this technique performs reduction processing on image data of a plurality of fields to generate data for display processing during recording of a still image.

JP 2007-243819 A

  In the technique of Patent Document 1, a configuration capable of performing reduction processing without generating image data output by an imaging unit and generating image data for display during recording of a still image (a configuration capable of performing on-the-fly processing) ). However, for example, when the imaging unit outputs image data at high speed, the reduction processing circuit needs to reduce the imaging data output by the imaging unit at high speed. If the processing speed of the reduction processing circuit is not enough for the speed at which the imaging means outputs the imaging data, a delay occurs in displaying and recording the image data.

  An object of the present invention is to provide an image processing device, an imaging device, a control method of the image processing device, a program, and a storage medium that suppress a delay between display and recording based on image data captured by an image sensor.

  In order to achieve the above object, an image processing apparatus according to the present invention includes: a dividing unit that divides image data acquired from an image sensor into first data and second data in accordance with a bit depth; A second memory for outputting the first data read from the first memory to be stored to display control means for displaying an image on a display unit, and storing the first data and the second data read from the first memory; And output means for outputting to the recording control means for recording on the recording medium data obtained by combining the second data read from the second data.

  According to the present invention, it is possible to suppress a delay between display and recording based on captured image data.

FIG. 2 is a perspective view of a digital camera as an imaging device. FIG. 2 is a block diagram illustrating a configuration of the imaging device according to the first embodiment. FIG. 2 is a diagram illustrating a part of an imaging device including an imaging control unit. FIG. 3 is a diagram illustrating an example of a method of dividing imaging data. 5 is a flowchart illustrating an example of a processing flow according to the first embodiment. 6 is a timing chart illustrating an imaging sequence of the imaging device. 6 is a timing chart showing control timings of display data and print data when the first embodiment is applied. 4 is a timing chart in a case where reading of recording data and writing to a recording medium are not completed during one frame period. 9 is a timing chart showing control timings of display data and print data when the second embodiment is applied. FIG. 4 is a diagram illustrating an example of crop output image data.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the configurations described in the following embodiments are merely examples, and the scope of the present invention is not limited by the configurations described in the embodiments.

<First embodiment>
FIG. 1 is a perspective view of a digital camera 10 as an example of an imaging device (imaging device 200) according to each embodiment. The digital camera 10 is provided with a rear liquid crystal display 12 such as an LCD on the rear side. The rear liquid crystal display 12 is the following display device 210. The imaging device according to the present embodiment is not limited to a digital camera. FIG. 2 is a block diagram illustrating a configuration of the imaging device 200 according to the present embodiment. The imaging device 200 includes an imaging element 201, an imaging control unit 204, a bus 205, DRAMs 206-1 to 206-N, a recording control unit 207, a recording medium 208, a display control unit 209, a display device 210, a CPU 211, and operation buttons 212. .

  The image sensor 201 is an image sensor such as a COMS sensor. The imaging control unit 204 is an image processing device that performs a process of correcting image deterioration due to a sensor, a correction of a defective pixel, and the like on the imaging data output by the imaging element 201, and generates image data converted into a predetermined format. . The imaging control unit 204 outputs the generated image data to the bus 205. The imaging control unit 204 generates an imaging control signal for controlling the synchronization from the exposure of the imaging data to the reading in accordance with an instruction from the CPU 211, and outputs the imaging control signal to the imaging element 201 via the imaging control signal transmission path 202. The imaging element 201 outputs the captured image data to the imaging control unit 204 via the imaging transmission path 203. The plurality of DRAMs 206-1 to 206-N (N is an integer of 2 or more) are memories that store or hold various data via the bus 205. Hereinafter, the DRAMs 206-1 to 206-N may be collectively referred to as a DRAM 206. For example, the CPU 211 and the imaging control unit 204 read data stored in the DRAM 206 and write data to the DRAM 206.

  The recording control unit 207 performs a process of developing the data output from the imaging control unit 204 into image data such as YUV or a correction process of an optical system, and performs recording processing on data (recording data) of a recording format corresponding to the recording medium 208. ) Is recording control means. The recording control unit 207 performs, for example, control of performing predetermined compression processing (JPEG compression or the like) on the image data output from the imaging control unit 204 and recording the image data on the recording medium 208. The recording medium 208 is a recording medium that finally stores the recording data output by the recording control unit 207, and for example, an SD card or the like is applied.

  The display control unit 209 performs a process of developing the data output by the imaging control unit 204 into a format corresponding to the display device 210 and a resizing process to match the output size of the display device 210. The display device 210 is a display unit that displays the data output by the display control unit 209 at a constant synchronization timing. For example, the above-described rear liquid crystal display 12 is applied. The CPU 211 outputs a control instruction to the imaging control unit 204, each DRAM 206, the recording control unit 207, and the display control unit 209. Further, the CPU 211 detects that the operation button 212 has been pressed. The operation button 212 is a shooting button of the imaging device 200.

  FIG. 3 is a diagram illustrating a part of the imaging device 200 including the imaging control unit 204. FIG. 3 illustrates a part of sub-blocks inside the imaging control unit 204 and a relationship between the sub-block and each unit in the vicinity. The imaging control unit 204 has a dividing unit 220 and an output unit 221. The division unit 220 is a division unit that divides the imaging data acquired from the imaging transmission path 203. FIG. 4 is a diagram illustrating an example of a method in which the division unit 220 divides imaging data. In the example of FIG. 4, the bit depth of each pixel data in the image data acquired from the image sensor 201 is 12 bits. The bit depth of each pixel data may be a bit depth other than 12 bits. The dividing unit 220 divides the 12-bit pixel data into upper 8 bits and lower 4 bits. The number of bits divided by dividing section 220 is not limited to 8 bits and 4 bits. The divided upper 8 bits data (upper bit data) and lower 4 bits data (lower bit data) are stored in different DRAMs 206 respectively. As illustrated in FIG. 3, the dividing unit 220 outputs the divided upper bit data to the bus 205 via the data path 101-1. The upper 8 bits of data output to the bus 205 are stored in the DRAM 206-1 via the data path 101-2. The dividing unit 220 outputs the divided lower bit data to the bus 205 via the data path 102-1. The lower bit data output to the bus 205 is stored in the DRAM 206-2 via the data path 102-2.

  The DRAM 206-1 is, for example, a high-bandwidth first memory that employs a 32-bit data width. The higher-order 8 bits of data having a larger number of bits (high-bandwidth bit data) are stored in the DRAM 206-1. The DRAM 206-2 is, for example, a low-bandwidth second memory that employs a data width of 16 bits. The lower 4-bit data (low-band bit data) having a small number of bits is stored in the DRAM 206-2. The DRAM 206-1 has a wider transmission band than the DRAM 206-2. Therefore, according to the bit depth of each pixel data, the dividing unit 220 determines whether the first data is the upper bit data having a larger number of bits and the second data is the lower bit data having a smaller number of bits than the upper bit data. Divided into Dividing section 220 stores the first data (upper bit data) in high-bandwidth DRAM 206-1 and stores the second data (lower-order bit data) in low-bandwidth DRAM 206-2.

  The data read from the DRAM 206-1 is input to the output unit 221 via the data path 101-3, the bus 205, and the data path 101-4. The data read from the DRAM 206-2 is input to the output unit 221 via the data path 102-3, the bus 205, and the data path 102-4. The output unit 221 performs a correction process or the like on the input data, and outputs the data after the correction process to the bus 205 via the data path 105. Although the data paths 101-1 and 102-1 in FIG. 3 are shown as different data paths, for example, in the case of time-division data transmission, the data paths 101-1 and 102-1 are one data path. May be. The same applies to the data paths 101-2 and 102-2, and the same applies to the data paths 101-3 and 102-3.

  Next, the processing flow of this embodiment will be described with reference to the flowchart of FIG. 5 and the timing charts of FIGS. FIG. 6 is a timing chart illustrating an imaging sequence of the imaging element 201. FIG. 7 is a timing chart showing the control timing of the display data and the recording data. The imaging control unit 204 drives the imaging element 201 in the live view mode (LV mode) during standby for continuous shooting (step S401). In the timing chart of FIG. 6, the period of the LV mode corresponds to the period of T1. As shown in the timing chart of FIG. 6, when the imaging state is in the LV mode, a synchronization signal is output at predetermined intervals, and the display control unit 209 displays image data on the display device 210 according to the synchronization signal. .

  The CPU 211 determines whether or not the operation button 212 that triggers the start of shooting of the imaging device 200 (camera) has been pressed (step S402). If NO is determined in step S402, there is no instruction to start shooting, so step S402 is repeated. If YES is determined in step S402, the imaging control unit 204 temporarily transitions the imaging device 201 to the IDLE mode via the imaging control signal transmission path 202 and transitions to the still image capturing mode (step S403). In the timing chart of FIG. 6, the period between T1 and T2 is the period of the IDLE mode. The CPU 211 sets recording and display of a still image during the period of the IDLE mode (step S404). Then, the imaging control unit 204 outputs a synchronization signal for driving a still image to the imaging device 201 via the imaging control signal transmission path 202, and changes the imaging device 201 to a still image driving mode (still image continuous shooting mode). (Step S405). In step S <b> 405, imaging data in still image driving is input to the imaging control unit 204 via the imaging transmission path 203. The operation sequence after step S405 will be described with reference to the timing chart of FIG. A period T601 indicates an output period of image data from the image sensor 201 in one frame period (predetermined cycle). A period other than the hatched period is a V blanking period, which is a standby time until the next frame. During the V blanking period, there is no input of imaging data from the imaging element 201.

  During the period T602, the higher-order bit data generated by the division unit 220 dividing each pixel data (12 bits) of the imaging data output from the imaging element 201 is stored in the DRAM 206-1 which is a high-bandwidth memory. Indicates the period up to. In the period T603, the lower-order bit data generated by the division unit 220 dividing each pixel data (12 bits) of the imaging data output from the imaging element 201 is stored in the DRAM 206-2, which is a low-bandwidth memory. Indicates the period up to. In the period T604, the output unit 221 starts reading upper bit data stored in the DRAM 206-1 which is a high-bandwidth memory. At this time, the output unit 221 starts reading via the data path 101-3 after the elapse of a sufficient margin offset time so as not to overtake the upper bit data stored in the DRAM 206-1.

  In the example of FIG. 7, the read time is longer than the write time for storing data in the DRAMs 206-1 and 206-2. The reason why the read time is longer than the write time is that there is no need to perform display or recording at a speed equivalent to the speed of inputting image data from the image sensor 201. For example, in the case of an electronic shutter, input of imaging data from the imaging element 201 may be performed by processing such as rolling shutter distortion reduction processing. Therefore, the read time is longer than the write time.

  The output unit 221 performs sensor correction or the like on the data read in the period T604 (data read from the DRAM 206-1) in the period T605, and then outputs the data to the bus 205 from the data path 105. . The data output to the bus 205 is stored in the DRAM 206 and input to the display control unit 209. The display control unit 209 performs a predetermined process for displaying on the display device 210, and outputs the display data to the display device 210.

  At this time, the image displayed on the display device 210 is equivalent to 8 bits with respect to 12 bits, which is the bit depth of one pixel of the imaging data input from the imaging element 201, but is used for composition confirmation during continuous shooting. The bit depth is sufficient for the quality of the framing image. The CPU 211 determines whether display data output to the display device 210 has been completed (step S406). Whether the display data output has been completed may be detected by the display control unit 209 generating an interrupt to the CPU 211 indicating that the display data output has been completed. If the determination in step S406 is NO, display data output has not been completed, so step S406 is repeated. If the determination in step S406 is YES, the display data output has been completed. In this case, the CPU 211 performs a setting to combine the data (recording data) read from the DRAM 206-1 with the data (recording data) read from the DRAM 206-2 (step S407).

  Based on the above setting, in the period T606, the output unit 221 reads the higher-order bit data already stored in the DRAM 206-1 via the data path 101-3. Similarly, in the period T607, the output unit 221 reads the lower bit data already stored in the DRAM 206-2 via the data path 102-3. Data from the data path 101-3 is input to the output unit 221 via the bus 205 and the data path 101-4. Data from the data path 102-3 is input to the output unit 221 via the bus 205 and the data path 102-4. In the period T608, the output unit 221 combines the upper bit data input from the DRAM 206-1 and the lower bit data input from the DRAM 206-2 to generate 12-bit data (combined data).

  Accordingly, as shown in FIG. 7, the output unit 221 reads out the higher-order bit data in the period T604 and outputs it to the display control unit 209, and then combines the combined data with the recording control unit 207 in the periods T606 and T607. Output. As a result, image data (image data composed of higher-order bit data) can be displayed on the display device 210, and image data (image data composed of combined data) can be recorded on the recording medium 208. The output unit 221 reads the higher-order bit data from the DRAM 206-1 in the periods T604 and T606, so that the number of times of reading out the upper-order bit data in one frame period is two. On the other hand, the output unit 221 reads the lower bit data from the DRAM-2 in the period T607, so that the number of times of reading the upper bits during one frame period is one, which is smaller than the number of times of reading the upper bit data. The upper bit data is used for both display and recording. The lower bit data is not used for display, but is used for recording. Therefore, the number of times of reading the lower bit data during one frame period is smaller than the number of times of reading the upper bit. For example, when the upper bit data is used for another purpose, the upper bit data may be read three or more predetermined times during one frame period.

  The output unit 221 performs a correction process or the like on the generated 12-bit data in the same manner as the display process, and then outputs the data to the data path 105. The data (recording data) output to the bus 205 is stored in the DRAM 206 and output to the recording control unit 207. The recording control unit 207 performs processing according to the recording medium 208 on the recording data, and outputs the data to the recording medium 208. As a result, image data composed of 12-bit pixel data is generated.

  The CPU 211 determines whether the output of the recording data has been completed, that is, whether the writing of the recording data to the recording medium 208 has been completed (step S408). The recording control unit 207 detects the writing status of the recording data on the recording medium 208, and when detecting the completion of the writing, causes the CPU 211 to generate an interrupt. Accordingly, the CPU 211 can make the determination in step S408. If the determination in step S408 is NO, the writing of the recording data has not been completed, so step S408 is repeated. If the determination in step S408 is YES, the writing of the recording data has been completed. In this case, the CPU 211 determines whether or not to record the next photographed frame (determines whether or not continuous shooting has been completed) (step S409). If the continuous shooting is not completed, the determination in step S409 is NO. In this case, the flow moves to step S404. If the continuous shooting has ended, the determination in step S409 is YES. In this case, the flow moves to step S401, and the imaging state changes to the LV mode (waiting) again. In the timing chart of FIG. 7, this corresponds to the period of T3.

  As described above, in the present embodiment, the dividing unit 220 divides the image data into upper bits and lower bits according to the bit depth of the pixel data in the image data input from the image sensor 201. Upper bit data having a larger number of bits is stored in a higher bandwidth DRAM 206-1 having a wider transmission band, and lower bit data having a smaller number of bits is stored in a lower bandwidth DRAM 206-2 having a narrower transmission band than the DRAM 206-1. You. Then, the output unit 221 reads out the higher-order bit data stored in the high-bandwidth DRAM 206-1 and outputs it to the display control unit 209. As a result, the display device 210 displays the image data composed of the upper bit data. On the other hand, the output unit 221 reads and combines the upper bit data stored in the high-bandwidth DRAM 206-1 and the lower-order bit data stored in the low-bandwidth DRAM 206-2. The combined data is output to the recording control unit 207, and the recording control unit 207 records the combined data on the recording medium 208.

  The bit depth of each pixel data of the image data displayed on the display device 210 is a partial bit data obtained by dividing the bit data of the image data input from the image sensor 201. Therefore, the bit depth of each pixel data of the image data displayed on the display device 210 is lower than the bit depth of each pixel data of the image data recorded on the recording medium 208. Therefore, the image quality of the image data displayed on the display device 210 is lower than the image quality of the image data recorded on the recording medium 208. However, the framing image for confirming the composition during continuous shooting is not required to be as high as the image data recorded on the recording medium 208. For this reason, even the image data composed of a part of the divided bit data is sufficient as the framing image for confirming the composition during the continuous shooting.

  Then, the output unit 221 reads out the high-order bit data stored in the high-bandwidth DRAM 206-1 and outputs it to the display control unit 209. The display control unit 209 converts the image data composed of the high-order bit data into a display device. Displayed at 210. Instead of all the bits of the pixel data of the image data input from the image sensor 201, the display device 210 displays image data composed of a part of higher-order bit data divided. The image data displayed on the display device 210 is image data composed of higher-order bit data. Therefore, the data amount of the image data (image data composed of the upper bit data) read for display is smaller than the data amount of the combined data obtained by combining the upper bit data and the lower bit data. Therefore, when displaying and recording the image data, the combined data having a large data amount is not read out a plurality of times. Therefore, even when the imaging element 201 outputs imaging data having a large number of pixels at high speed, it is possible to speed up the display of image data. In particular, the output unit 221 stores the high-order bit data in the high-bandwidth DRAM 206-1 having a wide transmission band and, when performing display, reads out the high-order bit data from the DRAM 206-1. Can be further accelerated.

  After the display control described above, the output unit 221 reads and combines the upper bit data stored in the high band DRAM 206-1 and the lower bit data stored in the low band DRAM 206-2, and combines the combined data. The data is output to the recording control unit 207. Since the speed of the display control can be increased, the timing at which the output unit 221 starts reading the upper bit data and the lower bit data is also advanced. Therefore, the timing of completing the writing of the data to the recording medium 208 is also advanced. Therefore, it is possible to suppress a delay between display and recording based on captured image data.

  Here, the imaging control unit 204 generates image data obtained by performing predetermined processing on the imaging data output by the imaging element 201, and the imaging control unit 204 performs display control without storing the image data in the DRAM 206. Output to the unit 209 is conceivable. In this case, the display processing of the image data is performed on the fly. In this case, when the imaging element 201 outputs the imaging data at high speed, if the operation speed of the circuit that performs the display processing of the image data on the fly is low, the delay of the display and recording based on the image data increases. On the other hand, the above-described delay can be reduced by using a circuit that displays image data on-the-fly at a high speed, but the circuit that displays image data on-the-fly must operate at high speed. As a result, it is necessary to apply advanced hardware to the circuit, and hardware costs increase. In the first embodiment, since image data is not processed on the fly, it is possible to reduce delays between display and recording based on captured image data while reducing hardware costs.

  In the first embodiment, an example in which a DRAM is used as the first memory and the second memory has been described. However, as the first memory and the second memory, an SRAM (static RAM) or another recording medium may be used. May be applied. Also, an example in which a high-bandwidth DRAM is applied to the DRAM 206-1 and a low-bandwidth DRAM is applied to the DRAM 206-2 has been described, but the transmission bands of the DRAM 206-1 and the DRAM 206-2 may be the same. However, the higher-order bit data divided by the dividing unit 220 is stored in the high-bandwidth DRAM 206-1, so that the speed of display control can be further increased. For this reason, it is preferable that the upper bit data divided by the dividing unit 220 be stored in the high-bandwidth DRAM 206-1 and the lower-order bit data be stored in the low-bandwidth DRAM 206-2.

<Second embodiment>
Next, a second embodiment will be described. 1 to 4 are the same as those in the first embodiment, and a description thereof will be omitted. FIG. 8 is a timing chart in a case where reading of recording data and writing to the recording medium 208 are not completed during one frame period. In the second embodiment, the same control as in the first embodiment is performed. However, when the number of pixels of the image data output from the image sensor 201 is large, or when the output speed of the image data is high, reading of the recording data and writing to the recording medium 208 are performed during one frame period. Might not complete.

  If the reading of the upper 8 bits of data in the period T706 and the reading of the lower 4 bits of the data in the period T707 are not completed during one frame period, the periods T706 and T707 start in the next frame period. In this case, the output unit 221 cannot read the upper bit data of the next frame from the DRAM 206-1. For this reason, the display control unit 209 performs control for displaying the previous frame on the display device 210 or blackout control for a frame from which display cannot be read. This makes it impossible to display an image on the display device 210 in the periods T704 and T705.

  FIG. 9 is a timing chart showing the control timing of the display data and the recording data when the second embodiment is applied. In the second embodiment, the output unit 221 completes the reading of the recording data and the writing to the recording medium 208 during one frame period (during a predetermined period or less). Therefore, in the periods T802 and T803, the division unit 220 performs a cropping process of deleting a part of the imaging data input from the imaging element 201 in the period T801 (deleting from the reading target). In this case, the dividing unit 220 performs a cropping process of cutting the upper, lower, left, and right images of the imaged data within the allowable range. FIG. 10 illustrates an example of image data that has been cropped (image data based on imaging data of the image sensor 201 at all angles of view). The allowable range is the sum of a period T805 in which the output unit 221 outputs the upper bit data to the display control unit 209 and a period T808 in which the upper bit data and the lower bit data are combined and output to the recording control unit 207. The range falls within one frame period. As a result, the angle of view of the captured data is reduced, but the amount of data to be captured is reduced. Therefore, the upper bit data whose data amount is reduced is stored in the DRAM 1206-1, and the lower bit data whose data amount is also reduced is stored in the DRAM 206-2.

  The data reduction is performed by dividing the imaging data into high-order bit data and low-order bit data, and then executing a process of reducing each data so that the sum of the period T805 and the period T808 falls within one frame period. May be.

  By reducing the data amount of the imaging data, the time for outputting the display data and the time for outputting the recording data can be reduced, and the reading of the recording data and the writing to the recording medium 208 can be performed in one frame period. It is possible to fit. Thus, the display of the next frame is not hindered. In the above description, the division unit 220 has performed the cropping process. However, the imaging element 201 deletes a part of the imaging data, adjusts the data size of the imaging data, and sends the adjusted imaging data to the division unit 220. May be output. The image sensor 201 determines that the sum of the period T805 during which the upper bit data is output to the display control unit 209 and the period T808 during which the upper bit data and the lower bit data are combined and output to the recording control unit 207 is one frame period. Adjust the data size to fit in the range.

  Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and changes can be made within the scope of the gist. The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or an apparatus via a network or a storage medium, and one or more processors of a computer of the system or the apparatus execute the program. The processing can be implemented by reading and executing. Further, the present invention can also be realized by a circuit (for example, an ASIC) that realizes one or more functions.

200 imaging device 201 imaging element 204 imaging control unit 206 DRAM
207 Recording control unit 208 Recording medium 209 Display control unit 210 Display device 211 CPU
220 Dividing unit 221 Output unit

Claims (18)

Division means for dividing imaging data acquired from the imaging device into first data and second data according to a bit depth;
The first data read from the first memory storing the first data is output to display control means for displaying an image on a display unit, and the first data and the second data read from the first memory are output. Output means for outputting data obtained by combining the second data read from the second memory to be stored to a recording control means for recording the data on a recording medium;
An image processing apparatus comprising: The first memory has a larger transmission band than the second memory,
2. The image processing apparatus according to claim 1, wherein the first data is data corresponding to an upper bit of the imaging data, and the second data is data corresponding to a lower bit of the imaging data. 3. apparatus.   The image processing apparatus according to claim 2, wherein the number of bits of the upper bits is larger than the number of bits of the lower bits. The dividing means acquires imaging data from the imaging device at predetermined intervals,
4. The apparatus according to claim 1, wherein the output unit reads the first data at a predetermined number of times of two or more in the predetermined period, and reads the second data a number of times smaller than the predetermined number. The image processing apparatus according to claim 1.   A period during which the output unit outputs the first data read from the first memory to a display control unit that displays an image on a display unit, a period during which the output unit reads the first data from the first memory, and 2. The output unit outputs the first data and the second data so that a sum of a period in which data obtained by combining the second data read from the memory and a period in which the data is output to the recording control unit is equal to or shorter than the predetermined period. The image processing apparatus according to claim 4, wherein a part of the data is deleted from a reading target. The dividing means stores the first data in the first memory, and stores the second data in the second memory;
A period during which the output unit outputs the first data read from the first memory to a display control unit that displays an image on a display unit, a period during which the output unit reads the first data from the first memory, and 2. The dividing means is configured to set the first data and the second data so that the sum of a period in which data obtained by combining the second data read from the memory and the period in which the data is output to the recording control unit is equal to or shorter than the predetermined period. 5. The image processing apparatus according to claim 4, wherein a part of the data is deleted from a storage target. After the display of the image on the display unit by the display control unit is completed, the recording control unit performs control to start recording the combined data on the recording medium,
The image processing apparatus according to claim 1, wherein: An image processing apparatus according to any one of claims 1 to 7,
The imaging device;
The display control means,
The display unit;
The recording control means,
An imaging device comprising:   The image pickup device includes a period in which the output unit outputs the first data read from the first memory to a display control unit that displays an image on a display unit, and a period in which the output unit reads out the first data from the first memory. The data size of the imaging data is adjusted so that the sum of a period in which data obtained by combining one data and the second data read from the second memory and outputting the data to the recording control unit is equal to or less than a predetermined period. The imaging device according to claim 8, wherein: A method for controlling an image processing apparatus, comprising:
Dividing imaging data acquired from the imaging device into first data and second data according to a bit depth;
The first data read from the first memory storing the first data is output to display control means for displaying an image on a display unit, and the first data and the second data read from the first memory are output. Outputting data obtained by combining the second data read from the second memory to be stored to recording control means for recording the data on a recording medium;
A method for controlling an image processing apparatus, comprising: The first memory has a larger transmission band than the second memory,
The image processing apparatus according to claim 10, wherein the first data is data corresponding to upper bits of the imaging data, and the second data is data corresponding to lower bits of the imaging data. How to control the device.   12. The method according to claim 11, wherein the number of bits of the upper bits is larger than the number of bits of the lower bits. Acquiring imaging data from the imaging device at predetermined intervals,
13. The method according to claim 10, wherein in the predetermined cycle, the first data is read out at a predetermined number of times equal to or more than two, and the second data is read out less than the predetermined number of times. The method for controlling an image processing apparatus according to the present invention.   A period for displaying the first data read from the first memory on an image on a display unit, the first data read from the first memory, and the second data read from the second memory; 14. A method according to claim 13, wherein a part of the first data and the second data is deleted from a reading target so that a sum of a period required for recording data obtained by combining the first data and the second data is equal to or shorter than the predetermined period. The control method of the image processing apparatus described in the above. Storing the first data in the first memory, and storing the second data in the second memory;
A period in which the first data read from the first memory is output to display control means for displaying an image on a display unit, and a period in which the first data read from the first memory and the second data read from the second memory are read. A part of the first data and the second data is deleted from the storage target so that the sum of a period in which data combined with data is output to the recording control unit is equal to or shorter than the predetermined period. The method for controlling an image processing apparatus according to claim 13, wherein: After the display of the image on the display unit by the display control unit is completed, control is performed to start recording the combined data on the recording medium.
14. The control method for an image processing apparatus according to claim 10, wherein:   A program for causing a computer to execute the method for controlling an image processing device according to claim 10.   A computer-readable storage medium storing a program for causing a computer to execute the control method for an image processing apparatus according to claim 10.

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