CN112510037B - 3D logic chip capacitor circuit, logic chip and electronic equipment - Google Patents
3D logic chip capacitor circuit, logic chip and electronic equipment Download PDFInfo
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- CN112510037B CN112510037B CN202011389073.6A CN202011389073A CN112510037B CN 112510037 B CN112510037 B CN 112510037B CN 202011389073 A CN202011389073 A CN 202011389073A CN 112510037 B CN112510037 B CN 112510037B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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Abstract
The embodiment of the application solves the problems of limited capacitance value of a unit area of a capacitor on a logic chip, high off-chip capacitance cost and complex structure by providing a 3D logic chip capacitance circuit, a logic chip and electronic equipment. The logic chip capacitor circuit may include: logic chip functional circuit and memory chip borrow electric capacity. The memory chip is arranged on the logic chip by a capacitor and is used for providing charges for power consumption elements of the functional circuit of the logic chip.
Description
Technical Field
The embodiment of the invention relates to the technical field of chips, in particular to a 3D logic chip capacitor circuit, a logic chip and electronic equipment.
Background
With the application of ASIC chips in the technical fields of AI artificial intelligence, big data centers, automatic driving and the like. The market demands and functions for chips are also increasing significantly. The integrated capacitor on the chip is a common device of each functional circuit of the chip, and CMOS (Complementary Metal Oxide Semiconductor ) gate capacitors, or MOM (Metal Oxide Metal) metal-oxide-metal capacitors and MIM (Metal Insulator Metal) metal-insulator-metal capacitors are commonly used for logic chips. The capacitance of the MOM capacitance and the capacitance of the MIM capacitance in unit area are smaller than the capacitance of the CMOS grid electrode, and are generally about 1/3 of the capacitance of the CMOS grid electrode. The CMOS grid capacitance is the capacitance between the grid gate, the source drain and the substrate of the CMOS device, and the capacitance value of the CMOS grid capacitance is about 11ff/um 2 in unit area, and the capacitance value is obviously influenced by voltage.
Therefore, the capacitance values of the CMOS gate, MOM capacitor and MIM capacitor, which are widely used in the logic chip, are limited, and unlike the memory chip, the implementation process of the logic chip limits the on-chip capacitor with a high capacitance value, so that when the large-capacity on-chip capacitor is required to be used in the logic chip design, only a large area of the logic chip can be occupied, and the practically achievable capacitance value in the logic chip design is difficult to exceed the order of nano-farads.
At present, the required high capacitance value capacitor is realized through the off-chip capacitor, so that the cost is increased, and the chip design is greatly limited due to the need of external pin wiring.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the embodiments of the present application is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.
The embodiment of the application solves the problems of limited capacitance value of a unit area of a capacitor on a logic chip, high off-chip capacitance cost and complex structure by providing a 3D logic chip capacitance circuit, a logic chip and electronic equipment.
To at least partially solve the above problems, in a first aspect, an embodiment of the present application provides a logic chip capacitor circuit, which may include: logic chip functional circuits and memory chips borrow capacitors,
The memory chip is arranged on the logic chip by a capacitor and is used for providing charges for power consumption elements of the logic chip functional circuit.
In a first possible implementation manner of the first aspect, the memory chip borrows a capacitor to be a high-density capacitor provided with a high-dielectric constant dielectric layer.
In a second possible implementation manner of the first aspect, the memory chip is disposed close to the power consumption element of the logic chip functional circuit by a 3D-IC three-dimensional integrated circuit technology by means of a capacitor.
In a third possible implementation manner of the first aspect, the memory chip borrows one or more capacitors.
In a fourth possible implementation manner of the first aspect, the logic chip functional circuit includes a switched capacitor circuit, and the memory chip borrows a capacitor for the switched capacitor circuit.
In a fifth possible implementation manner of the first aspect, the logic chip functional circuit includes a linear voltage stabilizing circuit, and the memory chip is disposed at a voltage output terminal of the linear voltage stabilizing circuit by using a capacitor.
In a sixth possible implementation manner of the first aspect, the logic chip functional circuit includes a charge pump circuit, and the memory chip borrows a capacitor as a bootstrap capacitor of the charge pump circuit.
In a second aspect, an embodiment of the present application provides a logic chip, which may include:
The logic chip capacitor circuit.
In a third aspect, an embodiment of the present application provides an electronic device, which may include:
The logic chip is connected with the memory chip, and the memory chip is provided with the memory chip borrowing capacitor.
In a first possible implementation manner of the third aspect, the logic chip and the memory chip are connected by a 3D-IC three-dimensional integrated circuit technology, wherein a memory chip for providing the power consumption element with electric charge is arranged at a corresponding position of the logic chip and the power consumption element by means of a capacitor.
Compared with the prior art, the logic chip capacitor circuit provided by the embodiment of the invention at least has the following beneficial effects:
the logic chip capacitor circuit provided by the embodiment of the invention comprises: the logic chip functional circuit and the memory chip borrowing capacitor are arranged on the logic chip and used for providing charges for power consumption elements of the logic chip functional circuit. Since the logic chip uses the capacitance in the memory chip, the capacitor is used as a borrowing capacitor to provide charge for the power consumption element of the logic chip itself. The problem that the capacitance value of the unit area of the on-chip capacitor is limited is well solved, meanwhile, the original cost is saved, and the response of a power supply signal and the function realization of other functional circuits are improved. In addition, the on-chip capacitor corresponding to the functional circuit of the logic chip to be provided with charges in the memory chip is used, so that the problems of high cost and complex structure caused by the need of adding an off-chip capacitor for improving the capacitance value of the on-chip capacitor of the logic chip are avoided.
Correspondingly, the logic chip and the electronic device provided by the embodiment of the invention also have the technical effects.
Drawings
For a clearer description of the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art:
FIG. 1 is a schematic block diagram of a logic chip capacitor circuit according to an embodiment of the present invention;
Fig. 2 is a circuit topology diagram of a logic chip capacitor circuit according to an embodiment of the present invention;
FIG. 3 is a circuit topology of a logic chip capacitor circuit according to an embodiment of the present invention;
FIG. 4 is a circuit topology diagram of another logic chip capacitor circuit according to an embodiment of the present invention;
FIG. 5 is a schematic block diagram of a logic chip according to an embodiment of the present invention;
FIG. 6 is a schematic block diagram of an electronic device according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The present invention is described in further detail below with reference to the drawings and examples to enable those skilled in the art to practice the invention by referring to the description.
It will be understood that terms, such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
In addition, it should be noted that the terms "disposed," "connected," and "connected" are to be construed broadly, unless otherwise specifically indicated and defined. For example, the connection can be fixed connection or detachable connection; can be directly connected or indirectly connected through an intermediate medium; may be integrally connected, or may be communication between two members. Or the two elements can be in signal transmission and data communication. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
Currently, CMOS gates, MOM capacitors, and MIM capacitors, which are widely used in logic chips, have relatively limited capacitance values per unit area. The capacitance of the MOM capacitance and the capacitance of the MIM capacitance in unit area are smaller than the capacitance of the CMOS grid electrode, and are generally about 1/3 of the capacitance of the CMOS. The CMOS grid capacitance is the capacitance between the grid gate, the source drain and the substrate of the CMOS device, and the capacitance value of the CMOS grid capacitance is about 11ff/um 2 in unit area, and the capacitance value is obviously influenced by voltage. Therefore, unlike the memory chip, the implementation process of the logic chip limits the on-chip capacitor with a high capacitance value which is difficult to integrate on the logic chip, and based on the existing capacitor solution, when the on-chip capacitor with a large capacity needs to be used in the logic chip design, a large area of the logic chip needs to be occupied, and the actually achievable capacitance value in the logic chip design is difficult to exceed the nano-scale.
Aiming at the problems, the embodiment of the application provides a 3D logic chip capacitor circuit, which solves the problems of limited capacitance value of a unit area of a capacitor on a logic chip, high off-chip capacitance cost and complex structure.
Fig. 1 is a schematic block diagram of a logic chip capacitor circuit according to an embodiment of the present invention, and as shown in fig. 1, the logic chip capacitor circuit 100 may include: logic chip functional circuit 110 and memory chip borrowing capacitor 120.
The memory chip borrowing capacitor 120 is disposed on the logic chip and is used for providing charges to the power consumption components of the logic chip functional circuit 110.
The memory chip borrowing capacitor 120 may be, for example, an on-chip capacitor of a memory chip, for example, an on-chip capacitor of a DRAM. When a certain condition is satisfied, the on-chip capacitor in the DRAM may be provided in the logic chip, and used as the capacitor of the logic chip. That is, in this embodiment, the chip borrowing capacitor 120 is provided to the logic chip by the memory chip when the logic chip and the memory chip satisfy a certain position and connection condition. In addition, for example, the chip borrowing capacitor 120 may be shared by the memory chip and the logic chip in a case where the logic chip and the memory chip satisfy a certain position and connection condition in order to achieve high utilization of the capacitor.
For example, the memory chip borrowing capacitor 120 may be disposed near the power consumption element of the logic chip functional circuit 110, and the pins of the memory chip borrowing capacitor 120 may be disposed around the power consumption element of the logic chip functional circuit 110, that is, the power consumption element in the functional circuit module or module physically close to the surface of the logic chip. The connection between the pins of the elements may also be that is, the pins of the capacitor 120 are connected to the corresponding circuits of the logic chip functional circuit 110, so as to provide charges for the power consumption elements in the logic chip functional circuit 110 to enable the logic chip functional circuit 110 to work normally.
In addition, whether the power consumption element in the functional circuit module or the module physically close to the surface of the logic chip is connected to the pin of the memory chip borrowing capacitor 120 in the circuit of the corresponding logic chip functional circuit 110, the memory chip is provided to the logic chip for use when the logic chip and the memory chip satisfy certain positions and connection conditions. In order to increase the utilization efficiency of the borrowed capacitor having a high capacitance value, the chip borrowing capacitor 120 may be shared by the memory chip and the logic chip when the logic chip and the memory chip satisfy a predetermined position and connection condition. Specifically, the above scheme needs to be satisfied, and the chip borrows the pins of the capacitor 120, and needs to be connected to the logic chip and the memory chip at the same time.
Therefore, the logic chip capacitor circuit provided by the embodiment of the invention comprises: the memory chip borrowing capacitor is arranged on the logic chip and is used for providing charges for power consumption elements of the logic chip functional circuit. Since the logic chip uses the capacitance in the memory chip, the capacitor is used as a borrowing capacitor to provide charge for the power consumption element of the logic chip itself. The problem that the capacitance value of the unit area of the on-chip capacitor is limited is well solved, meanwhile, the original cost is saved, and the response of a power supply signal and the function realization of other functional circuits are improved. In addition, the on-chip capacitor corresponding to the functional circuit of the logic chip to be provided with charges in the memory chip is adopted, so that the problems of high cost and complex structure caused by the need of adding an off-chip capacitor for improving the capacitance value of the on-chip capacitor of the logic chip are avoided.
According to some embodiments, the memory chip utilizes a capacitor as a high-density capacitor provided with a high-permittivity dielectric layer. When the medium is applied with an electric field, induced charges are generated to weaken the electric field, and the ratio of the original applied electric field (in vacuum) to the electric field in the final medium is the dielectric constant (PERMITTIVITY), also called dielectric constant, and is related to frequency. The dielectric constant is the product of the relative dielectric constant and the absolute dielectric constant in vacuum. If a material with a high dielectric constant is placed in an electric field, the strength of the electric field will drop considerably within the dielectric. The polarity of the polymer material can be determined according to the dielectric constant of the substance. In general, a substance having a relative dielectric constant of more than 3.6 is a polar substance; the substance with the relative dielectric constant in the range of 2.8-3.6 is a weak polar substance; a nonpolar substance having a relative dielectric constant of less than 2.8.
In some examples, a dielectric layer configuration of high density capacitance having a dielectric constant much greater than 3.6 may be selected, for example, a zirconium dioxide high density capacitance. The unit capacitance density can reach 1.8pf/um 2 by using the high-density capacitance realized by the dielectric layer with high dielectric constant. By adopting the high-density capacitor, the scheme has the advantage of high capacitance per unit area, saves space and can meet the capacitance requirement of a chip. Moreover, it should be noted that the high-density capacitor may be integrated into the memory chip during the manufacturing process of the memory chip by the stereo folding technology, and at present, no implementation condition is provided so that the high-density capacitor is integrated into the logic chip in the manufacturing process of the logic chip and provided to the memory chip through the logic chip.
It should be noted that, since the memory chip borrows the capacitor to provide for the logic chip, the memory chip and the logic chip need to meet certain positions and connection conditions to ensure that an excessively high resistance value cannot be generated between the memory chip borrowing capacitor and the logic chip, that is, the connection between the borrowing capacitor and the functional circuit requires a small resistance between them, based on the above problems, the embodiment of the present application further provides the following scheme:
The memory chip is illustratively arranged close to the power consuming elements of the logic chip functional circuit by 3D-IC three-dimensional integrated circuit technology with the aid of capacitors. It should be noted that 3D-IC technology is a technology that does not require chip punch-through, i.e., a technology that can connect pins of a capacitor of a certain metal layer in a memory chip with functional circuits in a logic chip, such as the Hyper-bonding technology. Through using 3D-IC technique, can make the perpendicular connection of memory chip borrow electric capacity and logic chip functional circuit, furthest reduced the resistance value between memory chip borrow electric capacity and the logic chip functional circuit to make the memory chip borrow electric capacity of above-mentioned memory chip can directly provide any logic chip inside functional circuit and use.
According to some embodiments, the number of the memory chip borrowing capacitors is one or more than two, and the on-chip capacitors in several existing chips can be selected to be used as the memory chip borrowing capacitors according to the sufficient positional relationship between the memory chip and the logic chip and the requirements of the functional circuits of the logic chip. For example, the memory chip and the logic chip are connected through the 3D-IC technology, and two on-chip capacitors corresponding to the logic chip functional circuit positions in the on-chip capacitors of the memory chip are provided, so that the two on-chip capacitors can be used as borrowed capacitors of the memory chip and connected with the logic chip functional circuit to be provided for the logic chip functional circuit. Or the storage chip and the logic chip are connected through the 3D-IC technology, and two on-chip capacitors corresponding to the positions of the logic chip functional circuits are arranged in the on-chip capacitors of the storage chip, but the logic chip functional circuits can meet the functional requirements only by the capacitance value of one of the on-chip capacitors, so that the capacitor, which is close to the power consumption element of the logic chip functional circuit, of the two on-chip capacitors can be selected as the borrowed capacitor of the storage chip, and is connected with the logic chip functional circuit so as to be provided for the logic chip functional circuit.
The logic chip capacitor circuit according to the embodiment of the present application is described below in some specific functional circuit scenarios by means of fig. 2 to 4.
As shown in fig. 2, the logic chip functional circuit unit may be a high-power consumption functional module in a logic chip, and the capacitors C1 and C2 on the memory chip may be respectively connected to the vicinity of the logic chip functional circuit unit on the surface of the logic chip through a 3D-IC technology, so as to provide the logic chip functional circuit unit with a required capacitor, thereby improving the power signal response of the logic chip functional circuit unit and improving the instantaneous voltage drop of the circuit. The original connection relation between the pins of the capacitors C1 and C2 in the memory chip is unchanged, and the corresponding capacitor function can be provided for the memory chip.
In some examples, the logic chip functional circuit may be a linear voltage stabilizing circuit, and the memory chip is disposed at a voltage output end of the linear voltage stabilizing circuit by using a capacitor. As shown in fig. 3, the logic chip functional circuit is a linear voltage stabilizing circuit, and the current linear voltage stabilizing circuit adopts a CMOS gate capacitor to provide a capacitance function, but because the capacitance per unit area of the CMOS gate capacitor is lower, the memory chip provided by the embodiment can be replaced by a capacitor to satisfy the function of the linear voltage stabilizing circuit. In the linear voltage stabilizing circuit, when the load current on the output voltage side changes, the gate voltage vgtate is regulated by comparing the output voltage with the output voltage fed back to the input terminal of the operational amplifier, so that the output voltage is kept stable at the level on the input voltage side. Wherein a Bleeder nmos is used to maintain the quiescent current of the branch. The linear voltage stabilizing circuit forms a negative feedback circuit loop, and the condition of the negative feedback circuit stability is that when the gain is reduced to 1 (unit gain), the phase shift is smaller than 180 degrees, the stability of the circuit loop is related to the position of a pole P1 (main pole point), and the pole P2, and the design of the linear voltage stabilizing circuit is usually that the pole P1 is positioned at an output end, so that the ripple wave of the input voltage can be reduced while the loop stability is maintained, and the power supply inhibition characteristic of the system is improved. As shown in the formula p1=1/(r1×c11), the larger the C11 is, the smaller the P1 is, and the better the voltage stabilizing effect of the linear voltage stabilizing circuit is, wherein R1 and C11 are respectively a small signal resistor and a small signal capacitor on the output voltage side, and referring to fig. 3, the voltage stabilizing effect of the linear voltage stabilizing circuit can be improved by replacing the capacitor C11 in the original linear voltage stabilizing circuit with the capacitor C3 by the memory chip.
In some examples, the logic chip functional circuit may be a charge pump circuit, and the storage chip uses a capacitor as a bootstrap capacitor of the charge pump circuit, where the bootstrap capacitor in the charge pump circuit can achieve the purpose of boosting by using the characteristic that voltages at two ends of the capacitor cannot be suddenly changed and the level of a switch-switched capacitor end formed by cmos. As shown in fig. 4, the logic chip functional circuit is a charge pump circuit, and has a structure that is symmetric about the left and right, and charges are transferred to vpp node and vdd1 node respectively along with the change of clock, and the charge transfer process is repeated for 2 times in each clock period T. The output current of the charge pump circuit can be found to be i=2×c× (2×vdd 1-vpp)/T. It can thus be seen that if a higher current output capability is required, the capacitance value needs to be increased. Referring to fig. 4, the current output capability of the above-described charge pump circuit can be improved by replacing the bootstrap capacitor in the original linear voltage stabilizing circuit with the memory chip borrowing capacitors C4 and C5.
According to some embodiments, the logic chip functional circuit may include a switched capacitor circuit, and the memory chip borrows a capacitor for the switched capacitor circuit. The switched capacitor circuit may be, for example, a switched capacitor filter circuit or a switched capacitor analog to digital conversion circuit, and is not limited herein. The storage chip can be used as the capacitor of the switch capacitor circuit by using the capacitor, so that the circuit function requirement is met.
It should be noted that the above logic chip functional circuit is merely an example of a specific functional circuit to illustrate that the logic chip according to the embodiments of the present invention provides charges. The logic chip capacitor circuit can be used to improve the functions of the circuit and the chip as in other functional circuits requiring a capacitor function, and is not limited herein.
The logic chip capacitor circuit according to the embodiment of the present invention is described in detail above with reference to fig. 1 to 4, and the logic chip according to the embodiment of the present invention will be described in detail below with reference to fig. 5.
Fig. 5 is a schematic block diagram of a logic chip according to an embodiment of the present invention. As shown in fig. 5, the logic chip 500 may include:
The logic chip capacitance circuit 510 described above.
The memory chip borrowing capacitor can be arranged close to a power consumption element of the logic chip functional circuit and used for providing charges for the power consumption element, wherein the memory chip borrowing capacitor is also used for providing charges for the memory chip.
In some examples, the memory chip borrowing capacitance may be an on-chip capacitance of the memory chip. When a certain condition is satisfied, the on-chip capacitor in the memory chip can be borrowed from the logic chip and used as the capacitor of the logic chip. That is, in this embodiment, the chip borrowing capacitor is provided to the logic chip by the memory chip when the logic chip and the memory chip satisfy a certain position and connection condition, and of course, in some examples, the memory chip itself may use the borrowing capacitor thereon, that is, the borrowing capacitor is commonly used by the memory chip and the logic chip.
In some examples, the memory chip borrowing capacitor may be disposed near a power consumption element of the logic chip functional circuit, and the pin of the memory chip borrowing capacitor may be disposed around the power consumption element of the logic chip functional circuit, that is, a power consumption element in the functional circuit module or module physically close to the surface of the logic chip. The connection between the pins of the elements can also be realized, namely, the pins of the memory chip borrowed capacitors are connected into the corresponding circuits of the logic chip functional circuits, so that the function of providing charges for the power consumption elements in the logic chip functional circuits can be realized, and the logic chip functional circuits can work normally.
Accordingly, the logic chip according to the embodiment of the present invention includes the logic chip capacitor circuit, where the logic chip capacitor circuit further includes: the logic chip functional circuit and the memory chip borrowing capacitor are arranged on the logic chip and used for providing charges for power consumption elements of the logic chip functional circuit. Since the logic chip uses the capacitance in the memory chip, the capacitor is used as a borrowing capacitor to provide charge for the power consumption element of the logic chip itself. The problem that the capacitance value of the unit area of the on-chip capacitor is limited is well solved, meanwhile, the original cost is saved, and the response of a power supply signal and the function realization of other functional circuits are improved. In addition, the on-chip capacitor corresponding to the functional circuit of the logic chip to be provided with charges in the memory chip is adopted, so that the problems of high cost and complex structure caused by the need of adding an off-chip capacitor for improving the capacitance value of the on-chip capacitor of the logic chip are avoided.
According to some embodiments, as shown in fig. 6, an electronic device 700 may further include:
The logic chip 710 and the memory chip 720 provided with the memory chip borrowing capacitor, and the logic chip 710 is connected to the memory chip 720.
Accordingly, the electronic device according to the embodiment of the present invention includes the logic chip, and the capacitance circuit of the logic chip further includes: the memory chip borrowing capacitor is arranged on the logic chip and is used for providing charges for power consumption elements of the logic chip functional circuit. Since the logic chip uses the capacitance in the memory chip, the capacitor is used as a borrowing capacitor to provide charge for the power consumption element of the logic chip itself. The problem that the capacitance value of the unit area of the on-chip capacitor is limited is well solved, meanwhile, the original cost is saved, and the response of a power supply signal and the function realization of other functional circuits are improved. In addition, the on-chip capacitor corresponding to the functional circuit of the logic chip to be provided with charges in the memory chip is adopted, so that the problems of high cost and complex structure caused by the need of adding an off-chip capacitor for improving the capacitance value of the on-chip capacitor of the logic chip are avoided.
According to some embodiments, as shown in fig. 7, an electronic device may further include a logic chip 610 and a memory chip 620.
The logic chip 610 and the memory chip 620 may be connected by a 3D-IC three-dimensional integrated circuit technology, wherein a memory chip for supplying electric charges to the power consumption element is disposed at a corresponding position of the logic chip and the power consumption element by using a capacitor.
Through using 3D-IC technology, can make the vertical connection of memory chip borrow electric capacity and logic chip functional circuit, furthest reduced the resistance value between memory chip borrow electric capacity and the logic chip functional circuit to make the memory chip borrow electric capacity of above-mentioned memory chip can directly provide any logic chip inside functional circuit and use.
The memory chip borrowing capacitor can be arranged close to a power consumption element of the logic chip functional circuit and used for providing charges for the power consumption element, wherein the memory chip borrowing capacitor is also used for providing charges for the memory chip.
In some examples, the memory chip borrowing capacitance may be an on-chip capacitance of the memory chip, for example, an on-chip capacitance in the memory chip. When a certain condition is satisfied, the on-chip capacitor in the memory chip may be provided in the logic chip, and used as the capacitor of the logic chip. That is, in this embodiment, the chip borrowing capacitor is provided to the logic chip by the memory chip under the condition that the logic chip and the memory chip satisfy a certain position and connection condition. In order to achieve the efficiency of capacitor utilization, the chip borrowing capacitor may be shared by the memory chip and the logic chip when the logic chip and the memory chip satisfy a certain position and connection condition.
In some examples, the memory chip borrowing capacitor may be disposed near a power consumption element of the logic chip functional circuit, and the pin of the memory chip borrowing capacitor may be disposed around the power consumption element of the logic chip functional circuit, that is, a power consumption element in the functional circuit module or module physically close to the surface of the logic chip. The connection between the pins of the elements can also be realized, namely, the pins of the memory chip borrowed by the capacitor are connected into the corresponding circuits of the logic chip functional circuits, so as to provide charges for the power consumption elements in the logic chip functional circuits, and the logic chip functional circuits can work normally.
In addition, whether the power consumption element in the functional circuit module or the module physically close to the surface of the logic chip is connected to the corresponding circuit of the logic chip functional circuit, or the pin of the memory chip borrowing capacitor is connected to the logic chip by the memory chip when the logic chip and the memory chip satisfy a certain position and connection condition. In order to achieve the efficiency of the capacitor utilization, the chip borrowing capacitor may be shared by the memory chip and the logic chip when the logic chip Logicarea and the memory chip Memoryarea satisfy a predetermined position and connection condition. Specifically, the above scheme needs to be satisfied, and the chip borrows pins of the capacitor and needs to be connected to the logic chip and the memory chip at the same time.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Although embodiments of the present invention have been disclosed above, it is not limited to the details and embodiments shown and described, it is well suited to various fields of use for which the invention would be readily apparent to those skilled in the art, and accordingly, the invention is not limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (10)
1. A 3D logic chip capacitive circuit, comprising: logic chip functional circuits and memory chips borrow capacitors,
The storage chip is arranged on the logic chip by a capacitor and is used for providing charges for power consumption elements of the logic chip functional circuit;
The memory chip borrowing capacitor is vertically connected with the logic chip functional circuit, the memory chip borrowing capacitor is arranged close to the power consumption element, and the memory chip borrowing capacitor is arranged at a corresponding position of the power consumption element of the logic chip;
the memory chip borrowing capacitance is an on-chip capacitance of the memory chip.
2. The logic chip capacitor circuit of claim 1, wherein the memory chip borrows a capacitor to be a high density capacitor provided with a high dielectric constant dielectric layer.
3. The logic chip capacitance circuit according to claim 1 or 2, wherein,
The memory chip is arranged close to the power consumption element of the logic chip functional circuit by a 3D-IC three-dimensional integrated circuit technology through a capacitor.
4. The logic chip capacitance circuit according to claim 3,
The memory chip borrows one or more than two capacitors.
5. The logic chip capacitance circuit according to claim 3,
The logic chip functional circuit comprises a switch capacitor circuit, and the memory chip is used for the switch capacitor circuit by a capacitor.
6. The logic chip capacitance circuit according to claim 3,
The logic chip functional circuit comprises a linear voltage stabilizing circuit, and the memory chip is arranged at the voltage output end of the linear voltage stabilizing circuit by means of a capacitor.
7. The logic chip capacitance circuit according to claim 3,
The logic chip functional circuit comprises a charge pump circuit, and the storage chip borrows a capacitor as a bootstrap capacitor of the charge pump circuit.
8. A logic chip, characterized in that: a logic chip capacitance circuit comprising any one of claims 1 to 7.
9. An electronic device, characterized in that: a memory chip comprising the logic chip of claim 8 and a borrowing capacitor provided with said memory chip, said logic chip being connected to said memory chip.
10. The electronic device of claim 9, wherein the logic chip and the memory chip are connected by 3D-IC three-dimensional integrated circuit technology.
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| CN111028872A (en) * | 2018-10-10 | 2020-04-17 | 美光科技公司 | Memory cell sensing based on precharging access lines using sense amplifiers |
| CN213958952U (en) * | 2020-12-01 | 2021-08-13 | 西安紫光国芯半导体有限公司 | Capacitive circuit, equipment and chip for 3D logic chip functional module |
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| US9299394B2 (en) * | 2012-10-04 | 2016-03-29 | Broadcom Corporation | Method and circuit for reducing current surge |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111028872A (en) * | 2018-10-10 | 2020-04-17 | 美光科技公司 | Memory cell sensing based on precharging access lines using sense amplifiers |
| CN213958952U (en) * | 2020-12-01 | 2021-08-13 | 西安紫光国芯半导体有限公司 | Capacitive circuit, equipment and chip for 3D logic chip functional module |
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