CN113571500A - Structure of silicon-based capacitor element - Google Patents
Structure of silicon-based capacitor element Download PDFInfo
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- CN113571500A CN113571500A CN202110809139.0A CN202110809139A CN113571500A CN 113571500 A CN113571500 A CN 113571500A CN 202110809139 A CN202110809139 A CN 202110809139A CN 113571500 A CN113571500 A CN 113571500A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 194
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 90
- 239000010703 silicon Substances 0.000 title claims abstract description 90
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 150000003376 silicon Chemical class 0.000 claims abstract description 7
- 239000004020 conductor Substances 0.000 claims description 18
- 238000010586 diagram Methods 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
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Abstract
The application relates to a structure of a silicon-based capacitor element, which comprises a silicon wafer and a plurality of capacitor units, wherein the silicon wafer is used as a substrate and is arranged on the surface of the silicon wafer; wherein: the capacitance unit comprises one or more capacitors, the capacitors comprise a plurality of electrodes, and at least one first electrode and one second electrode are arranged in the plurality of electrodes; the second electrode of each of the capacitors is not connected to the silicon wafer substrate or the second electrode of at least one of the capacitors is connected to the silicon wafer substrate. According to the multi-terminal capacitor, the plurality of capacitor units which are insulated from each other are manufactured on the silicon chip, so that multi-potential of the multi-terminal capacitor is realized, a user can freely cut the needed capacitor units according to various application scene requirements, and the flexibility is better.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a structure of a silicon-based capacitor element.
Background
Capacitors are commonly used components in electronic products, and their basic properties include storing charge; coupling and blocking direct current, passing only signal components (alternating current); the decoupling function is used for bypassing high-frequency noise, and the characteristic is applied to circuits of electronic products in daily use in various forms.
The MLCC (Multi-layer Ceramic Capacitors) is widely used due to low cost, but the conventional MLCC has the disadvantages of large capacity error, large noise, large parasitic inductance, and large temperature coefficient and voltage coefficient, and is not suitable for being used in a special circuit.
Disclosure of Invention
In order to generate multiple potentials by a multi-terminal capacitor and enable the capacitor to be flexibly applied to various scenes according to requirements, the application provides a structure of a silicon-based capacitor element.
The application provides a structure of silica-based capacitive element adopts following technical scheme:
a structure of a silicon-based capacitor element comprises a silicon wafer and a plurality of capacitor units which are arranged on the surface of the silicon wafer by taking the silicon wafer as a substrate; wherein:
the capacitance unit comprises one or more capacitors, the capacitors comprise a plurality of electrodes, and at least one first electrode and one second electrode are arranged in the plurality of electrodes; the second electrode of each of the capacitors is not connected to the silicon wafer substrate or the second electrode of at least one of the capacitors is connected to the silicon wafer substrate.
By adopting the technical scheme, the plurality of capacitor units which are mutually insulated or connected through the silicon chip substrate are manufactured on one silicon chip, and a user can obtain one or more capacitor units from the silicon chip as required, so that multi-potential of the multi-terminal capacitor is realized, the user can freely cut the required capacitor units according to various application scene requirements, and the flexibility is better.
Optionally, each of the capacitors of the capacitance unit is the same or different.
Optionally, the capacitors of each row of the capacitor units are the same and the capacitors of each column of the capacitor units are the same;
alternatively, the first and second electrodes may be,
the capacitor of each row of the capacitor unit is the same or the capacitor of each column of the capacitor unit is the same.
Optionally, the number of the capacitors included in each of the capacitor units on the silicon chip is the same or different.
Optionally, the number of the capacitors included in each row and each column of the capacitor units on the silicon chip is the same;
alternatively, the first and second electrodes may be,
the capacitor units on the silicon chip comprise the same number of capacitors in each row or column.
Optionally, the capacitor includes one or more capacitor structures with the silicon wafer as a substrate;
the capacitor structure comprises a deep groove, a conductor layer, N first polar plates, N second polar plates, a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the deep groove is arranged on the silicon chip and extends along the surface vertical to the silicon chip;
the N first polar plates and the N second polar plates are overlapped in a staggered mode, and the second dielectric layer is arranged between the first polar plates and the second polar plates to form a polar plate structure; superposing the first dielectric layer on the first polar plate of the polar plate structure to form a first structure of the capacitor structure;
the first structure is arranged in the deep groove, and the rest space in the deep groove is filled with the conductor layer; covering the third dielectric layer on the first structure and the conductor layer of the deep trench notch and insulating the conductor layer from the first and second plates by the first and third dielectric layers;
the first plate is connected with a first electrode of the capacitor, and the second plate is connected with a second electrode of the capacitor; the second electrode is connected or not connected to the conductor layer.
Optionally, the deep trench includes a lower trench and a first sub-trench and a second sub-trench disposed on two first upper edges opposite to the lower trench; the first bottom edges of the first subslot and the second subslot are respectively opposite to the two first upper edges and have the same height, and the second upper edges of the first subslot and the second subslot which are respectively opposite to the two first bottom edges are the same height as the surface of the silicon wafer;
two opposite ends of the first structure are respectively arranged in the first subslot and the second subslot, and the surface of the first dielectric layer is opposite to the bottom surfaces formed by the bottom edges of the first subslot and the second subslot; the rest part of the first structure is arranged in the low groove in a zigzag mode, and the surface of the first dielectric layer is opposite to the surface of the first upper edge of the low groove.
Optionally, each of the first electrodes of the capacitor is connected to the first plate of one or more of the capacitive structures; and the number of the first and second groups,
one of the second electrodes of the capacitor is connected to the second plate of one or more of the capacitive structures.
Optionally, a scribing groove is arranged between each capacitor unit on the silicon wafer.
In summary, the present application includes at least one of the following beneficial technical effects:
1. according to the method, the plurality of capacitor units which are mutually insulated or connected through the silicon wafer substrate are manufactured on the silicon wafer, and a user can obtain one or more capacitor units from the silicon wafer according to needs, so that multi-potential of the multi-terminal capacitor is realized, the user can freely cut the needed capacitor units according to various application scene requirements, and the flexibility is better;
2. the capacitor of the application adopts the structure that the capacitor is arranged along the extension and the zigzag of the surface of the silicon slice and the multilayer polar plates are overlapped to improve the capacitance density, and the capacitance density of the small-size capacitor unit is ensured.
Drawings
Fig. 1 is a schematic structural diagram of a silicon-based capacitive element in which a capacitive unit includes a plurality of capacitors according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a silicon-based capacitive element of which a capacitive unit includes a capacitor according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an internal circuit of the capacitor of FIGS. 1 and 2 provided by an embodiment of the present application;
fig. 4 is a schematic structural diagram of a silicon-based capacitive element with a number of electrodes of 6 in a capacitor provided in an embodiment of the present application;
FIG. 5 is a schematic diagram of an internal circuit of the capacitor of FIG. 4 when the second plates are not connected to each other according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of an internal circuit of the capacitor of FIG. 4 when second plates are connected to each other according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a silicon-based capacitive element with 5 electrodes of a capacitor provided in an embodiment of the present application;
FIG. 8 is a schematic diagram of an internal circuit of the capacitor of FIG. 7 according to an embodiment of the present disclosure;
FIG. 9 is a schematic diagram of the internal circuit of a conventional four terminal capacitor;
FIG. 10 is a schematic diagram of a first structure of a multilayer first plate and a multilayer second plate according to an embodiment of the present disclosure;
fig. 11 is a schematic diagram of a capacitor structure provided in an embodiment of the present application, where the second electrode is not connected to the conductor layer when N =1
Fig. 12 is a schematic structural diagram of a capacitor provided in an embodiment of the present application, where the second electrode is connected to the conductor layer when N = 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to fig. 1-11 and the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The embodiment of the application discloses a structure of a silicon-based capacitor element. Referring to fig. 1 and 2, a structure of a silicon-based capacitive element is partially cut, the structure of the silicon-based capacitive element includes a silicon wafer 100 and a plurality of capacitive units 200 arranged on one side of the silicon wafer 100, and in order to maximize the use of the silicon wafer, the capacitive units 200 generally arranged on one side of the silicon wafer 100 continuously and using the silicon wafer 100 as a substrate;
the capacitance unit 200 of the present embodiment includes one or more capacitors 210, fig. 1 is a schematic structural diagram of a silicon-based capacitance element in which the capacitance unit 200 includes a plurality of capacitors 210, and fig. 2 is a schematic structural diagram of a silicon-based capacitance element in which the capacitance unit 200 includes one capacitor 210; each capacitor 210 comprises a plurality of electrodes, at least one first electrode 201 and one second electrode 202 are arranged in the plurality of electrodes, and the number of the electrodes of the capacitor unit 200 is the sum of the number of the electrodes of each capacitor; when there are two electrodes of the capacitor 210, namely the first electrode 201 and the second electrode 202, as shown in fig. 1 and fig. 2, the internal circuit of the capacitor 210 is shown in fig. 3; when the number of the electrodes of the capacitor 210 is even, it may be half of the first electrodes 201 and half of the second electrodes 202, and at this time, one first electrode 201 corresponds to one second electrode 202, as shown in the structural diagram of the silicon-based capacitive element shown in fig. 4, the number of the electrodes of the capacitor is 6, and the internal circuits are shown in fig. 5 (the second plates are not connected to each other) and fig. 6 (the second plates are connected to each other); the first electrode 201 or the second electrode 202 may be larger than half, and the second electrode 202 or the first electrode 201 may be smaller than normal, in which case, a plurality of first electrodes or second electrodes share one second electrode or first electrode, that is, a plurality of terminals have the same potential; when the number of the electrodes of the capacitor 210 is odd, there must be a case where a plurality of first electrodes 201 or second electrodes 202 share one second electrode 202 or first electrode 201, as shown in the structural diagram of the silicon-based capacitive component shown in fig. 7, the number of the electrodes is 5, the internal circuit is shown in fig. 8, four second electrode plates are connected to each other, share one second electrode, and in order to further reduce the size of a single capacitor, the shared second electrode is generally disposed at the middle position of the first electrode.
In the embodiment of the present application, the relationship between the capacitors of the capacitance unit 200 includes the following two cases:
in the first case, each second electrode 202 of each capacitor 210 is not connected to the silicon wafer 100, thereby insulating the corresponding capacitive cell 200 from other capacitive cells; at this time, each first electrode 201 of each capacitor 210 may be connected with a different voltage, and the second electrode 202 of each capacitor 210 may also be connected with a different voltage to generate a different potential;
in the second case, the second electrode 202 (at least one second electrode 202) of at least one capacitor 210 is connected to the silicon chip 100, and the capacitors 210 whose second electrodes 202 are connected to the silicon chip 100 are connected to each other through the silicon chip 100, so that the corresponding capacitive unit 200 is connected to other capacitive units 200 (the second electrode 202 of at least one capacitor 210 is connected to the silicon chip 100) through the silicon chip substrate; at this time, each first electrode 201 of each capacitor 210 may be connected to a different voltage, all second electrodes 202 connected to the substrate of the silicon chip 100 may be connected to the same voltage, and the remaining second electrodes 202 may be connected to different voltages, thereby generating different potentials. The structure of the conventional multi-terminal capacitor is fixed, for example, the capacitor is provided with two first electrodes and two second electrodes, the two first electrodes are connected internally, the two second electrodes are connected internally, and the internal circuit is shown in fig. 9.
According to the embodiment of the application, the plurality of capacitor units are manufactured on the silicon chip, a user can obtain one capacitor unit from the silicon chip as required, or the plurality of capacitor units are connected and mutually insulated or connected through the silicon chip substrate, so that multi-potential of the multi-terminal capacitor is realized, the user can freely cut the needed capacitor unit according to various application scene requirements, and the flexibility is better.
In order to further improve the application flexibility, in the embodiment of the present application, the number of the first electrodes, the number of the second electrodes, and the arrangement of the first electrodes and the second electrodes of each capacitor 210 of the capacitor unit 200 are not limited, and the number of the capacitors 210 included in each capacitor unit 200 on the same silicon wafer is also not limited, and each capacitor 210 of the capacitor unit 200 may be the same or different; the two capacitors 210 are the same, which means that the number of the first electrodes 201, the number of the second electrodes 202, and the arrangement of the first electrodes 201 and the second electrodes 202 of the two capacitors are the same. The number of capacitors 210 included in each capacitive unit 200 may be the same or different on the silicon die.
In practical production, in order to facilitate production and manufacture of a greater number of capacitor units on the same silicon wafer, each capacitor unit 200 on the same silicon wafer is not generally manufactured to include a different capacitor, and therefore, in another embodiment, the arrangement of the same capacitor 210 on the same silicon wafer is any of the following cases:
(1) each row of capacitors 210 of each row of capacitive units 200 is the same and each column of capacitors 210 of each column of capacitive units 200 is the same, at which time each capacitor of the row of capacitive units is the same;
(2) the capacitors 210 in each row of the capacitive units 200 are the same or the capacitors 210 in each column of the capacitive units 200 are the same, and in this case, the capacitors in each row of the capacitive units may be the same and the capacitors in each column may be different; it is also possible that the capacitors of each row of a single capacitive unit are different and the capacitors of each column are the same.
In another embodiment, the capacitor units with the same number of capacitors 210 on the same silicon chip are arranged in any one of the following cases:
(1) each row and each column of the capacitor units on the silicon chip comprise the same number of capacitors;
(2) the same number of capacitors is included per row or column of capacitive cells on the silicon wafer.
When the capacitor units on the same silicon chip are the same, the capacitor units in each row and each column comprise the same number of capacitors, and the capacitors are the same.
In order to facilitate shearing, in the present embodiment, a scribing groove 101 is formed between each capacitor unit 200 on the silicon wafer 100; a user may cut one or more connected capacitive units 200 along the scribe line 101 as desired.
The traditional MLCC surface-mounted capacitor is formed by overlapping ceramic dielectric diaphragms printed with electrodes (inner electrodes) in a staggered mode, forming a ceramic chip through one-time high-temperature sintering, and sealing metal layers (outer electrodes) at two ends of the chip. Different from the traditional patch capacitor MLCC, the capacitor 210 of the embodiment of the present application adopts a structure extending and zigzag-arranged perpendicular to the surface of the silicon wafer to further improve the capacitance density, and ensure the capacitance density of the small-sized capacitor unit, and the capacitor 210 structure of the embodiment of the present application can manufacture at most 20 to 30 ten thousand capacitors 210 on a 12-inch silicon wafer. The capacitor 210 of the present embodiment includes one or more capacitor structures having the silicon wafer 100 as a substrate;
as shown in fig. 10, 11 and 12, the capacitor structure includes a deep trench 211 disposed on the silicon wafer 100 and extending along a direction perpendicular to the surface of the silicon wafer 100, a conductor layer, N first plates 212, N second plates 213, a first dielectric layer 214, a second dielectric layer 215, and a third dielectric layer 216; wherein N is a positive integer.
The first plate 212 is connected to the first electrode 201 of the capacitor 210, the second plate 213 is connected to the second electrode 202 of the capacitor 210, and the second electrode 202 is connected to or disconnected from the conductor layer, i.e. the second electrode 202 is connected to the silicon chip 100 through the conductor layer, or the second electrode 202 is disconnected from the silicon chip 100.
In the present embodiment, each first electrode 201 of the capacitor 210 is connected to a first plate 212 of one or more capacitive structures; and, a second electrode 202 of the capacitor 210 is connected to a second plate 213 of one or more capacitive structures, including in particular the following cases:
(1) each first electrode 201 of the capacitor 210 is connected to a first plate 212 of a capacitive structure; each second electrode 201 of the capacitor 210 is connected to a second plate 212 of the capacitor structure; in this case, each first plate and each second plate of the capacitor structure may be connected to different voltages, each pair of first and second electrodes connected to the same capacitor structure generating a different potential.
(2) At least one first electrode 201 of the capacitor 210 is connected to a first plate 212 of the plurality of capacitive structures; each second electrode 201 of the capacitor 210 is connected to a second plate 212 of the capacitor structure; in this case, the first electrodes share the same voltage, and the second plates of the capacitor structures share the same voltage, so that different potentials can be generated between the first plates and the second plates of the capacitor structures.
(3) The capacitors 210 are connected to a first plate 212 of a capacitor structure per first electrode 201; at least one second electrode 201 of the capacitor 210 is connected to a second plate 212 of the plurality of capacitive structures; in this case, the second electrodes share the same voltage, and the first plates of the capacitor structures can be connected to a non-voltage, so that different potentials can be generated between the first plates and the second plates of the capacitor structures.
(4) At least one first electrode 201 of the capacitor 210 is connected to a first plate 212 of the plurality of capacitive structures; at least one second electrode 201 of the capacitor 210 is connected to a second plate 212 of the plurality of capacitive structures. In this case, the first electrodes and the second electrodes are shared, and the first plate voltages of the capacitor structures sharing one first electrode are the same and the second plate voltages of the capacitor structures sharing one second electrode are the same; when the first polar plates of a plurality of capacitor structures share one first electrode and the second polar plates share one second electrode, the same electric potential is generated between the first polar plates and the second polar plates of the capacitor structures; when the first electrode plates of a plurality of capacitor structures share one first electrode or one second electrode plate shares one second electrode, correspondingly, the second electrode plates are connected to different second electrodes or the first electrode plates are connected to different first electrodes, different voltages can be connected, and different potentials can be generated between the first electrode plates and the second electrode plates of the capacitor structures.
The N first polar plates 212 and the N second polar plates 213 are overlapped in a staggered mode, and a second dielectric layer 215 is arranged between the first polar plates 212 and the second polar plates 213 to form a polar plate structure; forming a first structure of a capacitor structure by superimposing a first dielectric layer 214 on the face of the first plate 212 of the plate structure; the N first electrode plates 212 of the first structure are all connected to the same first electrode 201, and the N second electrode plates 213 are connected to the same second electrode 202, as shown in fig. 10.
The first structure is arranged in the deep trench 211, and the rest space in the deep trench 211 is filled with a conductor layer; a third dielectric layer 216 overlies the first structure of deep trench notches and the conductor layer, and the conductor layer is insulated from the first and second plates 212, 213 by the first and third dielectric layers 214, 216.
In the present embodiment, the deep trench 211 includes a lower trench 2111 and a first sub-trench 2112 and a second sub-trench 2113 provided on two first upper edges opposite to the lower trench 2111; the first bottom edges of the first subslot 2112 and the second subslot 2113 are respectively opposite to the two first upper edges and have the same height, and the second upper edges of the first subslot 2112 and the second subslot 2113 which are respectively opposite to the two first bottom edges are the same height as the surface of the silicon wafer 100;
the two opposite ends of the first structure are respectively arranged in the first subslot 2112 and the second subslot 2113, and the surface where the first dielectric layer 214 is located is opposite to the bottom surface formed by the bottom edges of the first subslot 2112 and the second subslot 2114; the remainder of the first structure is meandering within the undercut 2111, with the face of the first dielectric layer 214 opposite the face of the first upper edge of the undercut 2111. In some embodiments, first electrode 201 of capacitor 210 is disposed within first subslot 2112; second electrode 202 of capacitor 210 is disposed within second subslot 2113.
The foregoing is a preferred embodiment of the present application and is not intended to limit the scope of the application in any way, and any features disclosed in this specification (including the abstract and drawings) may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.
Claims (9)
1. A structure of a silicon-based capacitor element is characterized by comprising a silicon chip and a plurality of capacitor units which are arranged on the surface of the silicon chip by taking the silicon chip as a substrate; wherein:
the capacitance unit comprises one or more capacitors, the capacitors comprise a plurality of electrodes, and at least one first electrode and one second electrode are arranged in the plurality of electrodes; the second electrode of each of the capacitors is not connected to the silicon wafer substrate or the second electrode of at least one of the capacitors is connected to the silicon wafer substrate.
2. The structure of claim 1, wherein each of the capacitors of the capacitive unit is the same or different.
3. The structure of claim 2, wherein the capacitors of each row of the capacitive units are the same and the capacitors of each column of the capacitive units are the same;
alternatively, the first and second electrodes may be,
the capacitor of each row of the capacitor unit is the same or the capacitor of each column of the capacitor unit is the same.
4. The structure of claim 1, wherein the number of capacitors included in each of the capacitive units on the silicon die is the same or different.
5. The structure of claim 4, wherein the capacitor units comprise the same number of capacitors per row and per column on the silicon die;
alternatively, the first and second electrodes may be,
the capacitor units on the silicon chip comprise the same number of capacitors in each row or column.
6. The structure of claim 1, wherein the capacitor comprises one or more capacitive structures with the silicon die as a substrate;
the capacitor structure comprises a deep groove, a conductor layer, N first polar plates, N second polar plates, a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the deep groove is arranged on the silicon chip and extends along the surface vertical to the silicon chip;
the N first polar plates and the N second polar plates are overlapped in a staggered mode, and the second dielectric layer is arranged between the first polar plates and the second polar plates to form a polar plate structure; superposing the first dielectric layer on the first polar plate of the polar plate structure to form a first structure of the capacitor structure;
the first structure is arranged in the deep groove, and the rest space in the deep groove is filled with the conductor layer; covering the third dielectric layer on the first structure and the conductor layer of the deep trench notch and insulating the conductor layer from the first and second plates by the first and third dielectric layers;
the first plate is connected with a first electrode of the capacitor, and the second plate is connected with a second electrode of the capacitor; the second electrode is connected or not connected to the conductor layer.
7. The structure of claim 6, wherein the deep trench comprises a lower trench and a first sub-trench and a second sub-trench disposed on two first upper edges of the lower trench opposite; the first bottom edges of the first subslot and the second subslot are respectively opposite to the two first upper edges and have the same height, and the second upper edges of the first subslot and the second subslot which are respectively opposite to the two first bottom edges are the same height as the surface of the silicon wafer;
two opposite ends of the first structure are respectively arranged in the first subslot and the second subslot, and the surface of the first dielectric layer is opposite to the bottom surfaces formed by the bottom edges of the first subslot and the second subslot; the rest part of the first structure is arranged in the low groove in a zigzag mode, and the surface of the first dielectric layer is opposite to the surface of the first upper edge of the low groove.
8. The structure of claim 6, wherein each of said first electrodes of said capacitor is connected to said first plate of one or more of said capacitive structures; and the number of the first and second groups,
one of the second electrodes of the capacitor is connected to the second plate of one or more of the capacitive structures.
9. The structure of any one of claims 1 to 8, wherein a scribe line is provided between each of the capacitor cells on the silicon wafer.
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| CN202110809139.0A CN113571500A (en) | 2021-07-16 | 2021-07-16 | Structure of silicon-based capacitor element |
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| CN117923416A (en) * | 2024-01-08 | 2024-04-26 | 北京中科格励微科技有限公司 | MEMS element and manufacturing method thereof |
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| CN117923416A (en) * | 2024-01-08 | 2024-04-26 | 北京中科格励微科技有限公司 | MEMS element and manufacturing method thereof |
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