CN112510037A - 3D logic chip capacitor circuit, logic chip and electronic equipment - Google Patents
3D logic chip capacitor circuit, logic chip and electronic equipment Download PDFInfo
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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Abstract
The embodiment of the application provides a 3D logic chip capacitor circuit, a logic chip and an electronic device, and solves the problems that the unit area capacitance value of a capacitor on the logic chip is limited, the cost of an off-chip capacitor is high, and the structure is complex. Wherein, the logic chip capacitance circuit may include: the logic chip functional circuit and the storage chip borrow capacitors. The memory chip is arranged on the logic chip by means of a capacitor and is used for providing electric charge for power consumption elements of the functional circuit of the logic chip.
Description
Technical Field
The embodiment of the invention relates to the technical field of chips, in particular to a 3D logic chip capacitor circuit, a logic chip and electronic equipment.
Background
With the application of ASIC chip in AI artificial intelligence, big data center, automatic driving and other scientific and technological fields. The market demand and functionality for chips is also increasing dramatically. The capacitors integrated on the chip are commonly used devices of each functional circuit of the chip, and CMOS (Complementary Metal Oxide Semiconductor) gate capacitors, or mom (Metal Oxide Metal) Metal-Oxide-Metal capacitors and mim (Metal Insulator Metal) Metal-Insulator-Metal capacitors are commonly used in logic chips. The MOM capacitor and the MIM capacitor have a unit area capacitance smaller than the CMOS gate capacitance, which is about 1/3 of the CMOS gate capacitance. The gate and source of the CMOS device are used as the gate capacitor and the gate capacitorThe capacitance between the source, the drain and the substrate is generally 11ff/um per unit area2On the left and right sides, the capacitance value is significantly affected by voltage.
Therefore, the unit area capacitance values of the CMOS gate, the MOM capacitor and the MIM capacitor, which are widely used in the logic chip, are relatively limited, and different from the memory chip, the implementation process of the logic chip limits the on-chip capacitor that is difficult to integrate with a high capacitance value on the logic chip, when the large-capacity on-chip capacitor is needed in the logic chip design, only a large area of the logic chip is occupied, and the capacitance value that can be actually realized in the logic chip design hardly exceeds the nano-farad order.
At present, the required high-capacitance value capacitors are realized through off-chip capacitors, so that the cost is increased, and the design of a chip is greatly limited due to the need of external pin connection.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. The summary of the embodiments of the present application is not intended to define key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The embodiment of the application provides a 3D logic chip capacitor circuit, a logic chip and an electronic device, and solves the problems that the unit area capacitance value of a capacitor on the logic chip is limited, the cost of an off-chip capacitor is high, and the structure is complex.
To at least partially solve the above problem, in a first aspect, an embodiment of the present application provides a logic chip capacitor circuit, which may include: the logic chip functional circuit and the memory chip borrow capacitors,
the storage chip is arranged on the logic chip by means of a capacitor and is used for providing electric charges for power consumption elements of the functional circuit of the logic chip.
In a first possible implementation manner of the first aspect, the storage chip borrowing capacitor is a high-density capacitor provided with a high-dielectric-constant dielectric layer.
In a second possible implementation manner of the first aspect, the memory chip is disposed close to the power consuming element of the logic chip functional circuit by means of a 3D-IC three-dimensional integrated circuit technology by means of a capacitor.
In a third possible implementation manner of the first aspect, the memory chip borrows one or more than two capacitors.
In a fourth possible implementation form of the first aspect, the logic chip function circuit comprises a switched capacitor circuit, and the memory chip borrows a capacitor for the switched capacitor circuit.
In a fifth possible implementation manner of the first aspect, the logic chip functional circuit includes a linear voltage regulator circuit, and the memory chip is disposed at a voltage output terminal of the linear voltage regulator circuit by using a capacitor.
In a sixth possible implementation manner of the first aspect, the logic chip functional circuit includes a charge pump circuit, and the memory chip borrows a capacitor as a bootstrap capacitor of the charge pump circuit.
In a second aspect, an embodiment of the present application provides a logic chip, which may include:
the logic chip capacitor circuit is described above.
In a third aspect, an embodiment of the present application provides an electronic device, which may include:
the logic chip and the memory chip provided with the memory chip borrowing capacitor are connected with each other.
In a first possible implementation manner of the third aspect, the logic chip and the memory chip are connected by a 3D-IC three-dimensional integrated circuit technology, wherein the memory chip that supplies the power consuming element with electric charge is disposed at a position corresponding to the logic chip and the power consuming element by means of a capacitor.
Compared with the prior art, the logic chip capacitor circuit provided by the embodiment of the invention at least has the following beneficial effects:
the logic chip capacitor circuit provided by the embodiment of the invention comprises: the storage chip borrows a capacitor, and the storage chip borrows the capacitor and is arranged on the logic chip and used for providing electric charge for power consumption elements of the logic chip functional circuit. Because the logic chip uses the capacitor in the storage chip, the capacitor is used as a power consumption element for providing charge for the logic chip. The problem that the capacitance value of the on-chip capacitor in unit area is limited is solved, original cost is saved, and the response of a power supply signal and the function realization of other functional circuits are improved. In addition, the on-chip capacitor corresponding to the functional circuit of the logic chip to be provided with the charge in the memory chip is used, so that the problems of high cost and complex structure caused by the need of additionally adding an off-chip capacitor for improving the capacitance value of the on-chip capacitor of the logic chip are solved.
Accordingly, the logic chip and the electronic device provided by the embodiment of the invention also have the technical effects.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts based on these drawings:
fig. 1 is a schematic structural block diagram of a logic chip capacitor circuit according to an embodiment of the present invention;
fig. 2 is a circuit topology diagram of a logic chip capacitor circuit according to an embodiment of the present invention;
FIG. 3 is a circuit topology diagram of a capacitor circuit of a logic chip according to another embodiment of the present invention;
FIG. 4 is a circuit topology diagram of another logic chip capacitor circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural block diagram of a logic chip according to an embodiment of the present invention;
fig. 6 is a schematic structural block diagram of an electronic device according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The present invention is further described in detail below with reference to the drawings and examples so that those skilled in the art can practice the invention with reference to the description.
It will be understood that terms such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
In addition, it should be noted that the terms "disposed" and "connected" are to be construed broadly unless otherwise explicitly stated or limited. For example, the connection can be fixed connection or detachable connection; can be directly connected or indirectly connected through an intermediate medium; either integrally connected or communicating between the interior of the two components. Or the two elements may perform signal transmission and data communication. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
Currently, the CMOS gates, MOM capacitors, and MIM capacitors, which are widely used in logic chips, have relatively limited capacitance per unit area. The MOM capacitor and the MIM capacitor have a unit area capacitance smaller than the CMOS gate capacitance, which is about 1/3 of the CMOS capacitor. The CMOS grid capacitance uses the capacitance between grid gate, source, drain and substrate of CMOS device, and the unit area capacitance value is 11ff/um2On the left and right sides, the capacitance value is significantly affected by voltage. Therefore, unlike a memory chip, the implementation process of a logic chip limits the on-chip capacitors that are difficult to integrate with high capacitance values on the logic chip, and based on the existing capacitor solution, when a large-capacity on-chip capacitor is needed in the logic chip design, the area of the logic chip needs to be occupied, and the capacitance value that can be actually realized in the logic chip design is difficult to exceed the order of magnitude of nanofarads.
In view of the above problems, embodiments of the present application provide a 3D logic chip capacitor circuit, which solves the problems of limited capacitance value per unit area of a capacitor on a logic chip, high cost of off-chip capacitors, and complex structure.
Fig. 1 is a schematic structural block diagram of a logic chip capacitor circuit according to an embodiment of the present invention, and as shown in fig. 1, the logic chip capacitor circuit 100 may include: the logic chip function circuit 110 and the memory chip borrow the capacitor 120.
The memory chip is disposed on the logic chip by means of a capacitor 120, and is used to provide electric charge to the power consuming elements of the logic chip function circuit 110.
Illustratively, the above-mentioned memory chip borrowing capacitor 120 may be an on-chip capacitor of the memory chip, for example, an on-chip capacitor in a DRAM. When a certain condition is satisfied, the on-chip capacitor in the DRAM may be provided in the logic chip to be used as the capacitor of the logic chip. That is, in this embodiment, the chip borrowing capacitor 120 is provided from the memory chip to the logic chip for use when the logic chip and the memory chip satisfy certain position and connection conditions. In addition, for example, in order to realize a high utilization rate of the capacitor, the chip borrowing capacitor 120 may be shared by the memory chip and the logic chip when the logic chip and the memory chip satisfy certain position and connection conditions.
For example, the memory chip borrowing capacitor 120 may be disposed near the power consuming element of the logic chip functional circuit 110, and the pin of the memory chip borrowing capacitor 120 may be disposed around the power consuming element of the logic chip functional circuit 110, that is, the power consuming element in the functional circuit module or the module that is physically close to the surface of the logic chip. Or, the connection between the device pins may be, that is, the memory chip is connected to the corresponding circuit of the logic chip functional circuit 110 by the pin of the capacitor 120, so as to provide the charge for the power consuming device in the logic chip functional circuit 110, so as to enable the logic chip functional circuit 110 to operate normally.
In addition, no matter the functional circuit module or the power consumption element in the module which is physically close to the surface of the logic chip, or the circuit which connects the pin of the memory chip borrowing capacitor 120 to the corresponding logic chip functional circuit 110, the chip borrowing capacitor 120 is provided for the logic chip by the memory chip when the logic chip and the memory chip satisfy certain position and connection conditions. In order to improve the utilization efficiency of the borrowing capacitor having a high capacitance value, the chip borrowing capacitor 120 may be shared by the memory chip and the logic chip when the logic chip and the memory chip satisfy a predetermined position and connection condition. Specifically, the above scheme needs to satisfy that the chip borrows the pins of the capacitor 120, and needs to be connected to the logic chip and the memory chip.
Therefore, the logic chip capacitor circuit provided by the embodiment of the present invention includes: the storage chip borrows a capacitor which is arranged on the logic chip and is used for providing electric charge for a power consumption element of the logic chip functional circuit. Because the logic chip uses the capacitor in the storage chip, the capacitor is used as a power consumption element for providing charge for the logic chip. The problem that the capacitance value of the on-chip capacitor in unit area is limited is solved, original cost is saved, and the response of a power supply signal and the function realization of other functional circuits are improved. In addition, the on-chip capacitor corresponding to the functional circuit of the logic chip to be provided with the charge in the storage chip is adopted, so that the problems of high cost and complex structure caused by the need of additionally adding an off-chip capacitor for improving the capacitance value of the on-chip capacitor of the logic chip are solved.
According to some embodiments, the storage chip borrows the capacitor into a high-density capacitor provided with a high-dielectric-constant dielectric layer. When an electric field is applied to a medium, induced charges are generated to weaken the electric field, and the ratio of the original applied electric field (in vacuum) to the electric field in the final medium is the dielectric constant (permittivity), which is also called dielectric rate, and is related to frequency. The dielectric constant is the product of the relative dielectric constant and the absolute dielectric constant in vacuum. If a material with a high dielectric constant is placed in an electric field, the strength of the electric field will drop appreciably within the dielectric. The polarity of the polymer material can be determined according to the dielectric constant of the material. Generally, substances having a relative dielectric constant greater than 3.6 are polar substances; the material with the relative dielectric constant within the range of 2.8-3.6 is a weak polar material; the dielectric constant is less than 2.8, and the material is nonpolar.
In some examples, a high density capacitor constructed with a dielectric layer having a dielectric constant much greater than 3.6 may be selected, for example, a zirconium dioxide high density capacitor. The unit capacitance density can reach 1.8pf/um through high-density capacitance realized by using a dielectric layer with high dielectric constant2. By adopting the high-density capacitor, the scheme has the advantage of high capacitance value per unit area, saves space and can meet the capacitance value requirement of a chip. In addition, the high-density capacitor may be integrated into a memory chip in a memory chip manufacturing process by a three-dimensional folding technology, and currently, no implementation condition is provided so that the high-density capacitor is integrated into a logic chip in a logic chip manufacturing process and provided to the memory chip for use by the logic chip.
It should be noted that, because the memory chip is provided for the logic chip by using the capacitor, the memory chip and the logic chip need to meet a certain position and connection condition to ensure that an excessively high resistance value is not generated between the memory chip and the logic chip by using the capacitor, that is, the connection between the capacitor and the functional circuit requires that the resistance between them is very small, and based on the above problems, the embodiments of the present application further provide the following solutions:
illustratively, the memory chip is arranged close to the power consumption element of the logic chip functional circuit by 3D-IC three-dimensional integrated circuit technology by means of a capacitor. It should be noted that the 3D-IC technology is a technology that does not need to punch through a chip, that is, a technology that can connect a pin of a capacitor of a metal layer in a memory chip and a functional circuit in a logic chip, such as a Hyper-bonding technology. By using the 3D-IC technology, the memory chip can be vertically connected with the logic chip functional circuit by virtue of the capacitor, and the resistance value between the memory chip borrowing capacitor and the logic chip functional circuit is reduced to the greatest extent, so that the memory chip borrowing capacitor of the memory chip can be directly provided for any functional circuit in the logic chip to use.
According to some embodiments, the number of the storage chip borrowing capacitors is one or more than two, and on-chip capacitors in several existing chips can be selected and used as the storage chip borrowing capacitors according to the sufficient connection position relationship between the storage chip and the logic chip and the requirements of a logic chip functional circuit. For example, after the memory chip and the logic chip are connected by the 3D-IC process technology, two on-chip capacitors corresponding to the positions of the functional circuits of the logic chip are provided in the on-chip capacitors of the memory chip, and then the two on-chip capacitors can be used as the memory chip to be connected with the functional circuits of the logic chip by using the capacitors, so as to be provided for the functional circuits of the logic chip. Or, although there are two on-chip capacitors corresponding to the position of the logic chip functional circuit in the capacitors on the memory chip through the memory chip and the logic chip after the connection by the 3D-IC process technology, the logic chip functional circuit can meet the functional requirement only by the capacitance value of one on-chip capacitor, and then the capacitor closer to the power consumption element of the logic chip functional circuit in the two on-chip capacitors can be selected as the memory chip borrowing capacitor to be connected with the logic chip functional circuit so as to be provided for the logic chip functional circuit to use.
The logic chip capacitor circuit of the embodiment of the present application is described below in some specific functional circuit scenarios through fig. 2 to 4.
As shown in fig. 2, the logic chip functional circuit unit may be a high power consumption functional module in a logic chip, and capacitors C1 and C2 on a memory chip may be respectively connected to the vicinity of the logic chip functional circuit unit on the surface of the logic chip by using a 3D-IC technology, so as to provide capacitors meeting requirements for the logic chip functional circuit unit, thereby improving the power supply signal response of the logic chip functional circuit unit and improving the instantaneous voltage drop of the circuit. The original connection relationship of the pins of the capacitors C1 and C2 in the memory chip is not changed, and the corresponding capacitor function can still be provided for the memory chip.
In some examples, the logic chip functional circuit may be a linear voltage regulator circuit, and the memory chip is disposed at a voltage output terminal of the linear voltage regulator circuit by using a capacitor. As shown in fig. 3, the logic chip functional circuit is a linear voltage regulator circuit, and the conventional linear voltage regulator circuit uses a CMOS gate capacitor to provide a capacitance function, but since the capacitance value of the CMOS gate capacitor per unit area is low, the capacitance can be replaced by a capacitor through the memory chip provided in this embodiment, so as to satisfy the function of the linear voltage regulator circuit. In the linear voltage stabilizing circuit, when the load current on the output voltage side changes, the gate voltage vgate is adjusted by comparing the output voltage with the output voltage fed back to the input end of the operational amplifier, so that the output voltage is kept stable on the level of the input voltage side. Wherein the Bleeder nmos is used to maintain the quiescent current of the branch. The linear voltage stabilizing circuit forms a circuit loop of negative feedback, the stable condition of the negative feedback circuit is that when the gain is reduced to 1 (unit gain), the phase shift is less than 180 degrees, the stability of the circuit loop and a pole P1 (dominant pole) are related to the position of P2, and the design of the linear voltage stabilizing circuit is usually that P1 is positioned at the output end, so that the loop is kept stable, meanwhile, the ripple of input voltage can be reduced, and the power supply rejection characteristic of the system is improved. As shown in fig. 3, the voltage stabilizing effect of the linear voltage regulator circuit can be improved by replacing the capacitor C11 in the original linear voltage regulator circuit with the capacitor C3 by the memory chip, wherein R1 and C11 are respectively a small signal resistor and a capacitor on the output voltage side, and the larger the C11 is, the smaller the P1 is, as shown in the formula P1/(R1 × C11).
In some examples, the logic chip functional circuit may be a charge pump circuit, and the memory chip uses a capacitor as a bootstrap capacitor of the charge pump circuit, where the bootstrap capacitor in the charge pump circuit can switch a level of a capacitor end by using a characteristic that a voltage across the capacitor cannot change suddenly and a switch formed by cmos, so as to achieve a purpose of boosting. As shown in fig. 4, the logic chip functional circuit is a charge pump circuit, and has a left-right symmetrical structure, and charges are respectively transferred to the vpp node and the vdd1 node as time changes, and the process of charge transfer is repeated for 2 times in each clock cycle T. The output current of the charge pump circuit can be determined to be I ═ 2 × C × (2 × vdd 1-vpp)/T. It can therefore be seen that if a higher current output capability is required, the capacitance needs to be increased. Referring to fig. 4, the current output capability of the charge pump circuit can be improved by replacing the bootstrap capacitor in the original linear voltage stabilizing circuit with the capacitors C4 and C5 for the memory chip.
According to some embodiments, the logic chip functional circuit may include a switched capacitor circuit, and the memory chip borrows a capacitor for the switched capacitor circuit. For example, the switched capacitor circuit may be a switched capacitor filter circuit or a switched capacitor analog-to-digital conversion circuit, which is not limited herein. The memory chip can be used as the capacitor of the switched capacitor circuit by using the capacitor, so as to meet the functional requirements of the circuit.
It should be noted that the above logic chip functional circuit is only used as a specific functional circuit example to illustrate that the logic chip of the embodiment of the present invention provides electric charge. The functions of the circuit and the chip can be improved by the logic chip capacitor circuit, which is not limited herein, like other functional circuits in the logic chip that need the capacitor function.
The logic chip capacitor circuit according to the embodiment of the present invention is described in detail above with reference to fig. 1 to 4, and the logic chip according to the embodiment of the present invention is described in detail below with reference to fig. 5.
Fig. 5 is a schematic structural block diagram of a logic chip according to an embodiment of the present invention. As shown in fig. 5, the logic chip 500 may include:
the logic chip capacitor circuit 510 described above.
The memory chip borrowing capacitor can be arranged close to a power consumption element of the logic chip functional circuit and used for providing electric charge for the power consumption element, wherein the memory chip borrowing capacitor is also used for providing electric charge for the memory chip.
In some examples, the memory chip borrowing capacitor may be an on-chip capacitor of the memory chip. When a certain condition is satisfied, the on-chip capacitor in the memory chip can be borrowed to the logic chip and used as the capacitor of the logic chip. That is, in this embodiment, the chip borrowing capacitor is provided from the memory chip to the logic chip when the logic chip and the memory chip satisfy a predetermined position and connection condition, but in some examples, the memory chip itself may use the borrowing capacitor, that is, the borrowing capacitor may be used by both the memory chip and the logic chip.
In some examples, the memory chip borrowing capacitor may be disposed near a power consuming element of the logic chip functional circuit, and the pin of the memory chip borrowing capacitor may be disposed around the power consuming element of the logic chip functional circuit, that is, a power consuming element in the functional circuit module or the module physically close to the surface of the logic chip. Or the connection between the component pins, that is, the pins of the storage chip via the capacitor are connected into the corresponding circuit of the logic chip functional circuit, so as to provide charges for the power consuming components in the logic chip functional circuit, so that the logic chip functional circuit can work normally.
Accordingly, the logic chip provided in the embodiment of the present invention includes the logic chip capacitor circuit, and the logic chip capacitor circuit further includes: the storage chip borrows a capacitor, and the storage chip borrows the capacitor and is arranged on the logic chip and used for providing electric charge for power consumption elements of the logic chip functional circuit. Because the logic chip uses the capacitor in the storage chip, the capacitor is used as a power consumption element for providing charge for the logic chip. The problem that the capacitance value of the on-chip capacitor in unit area is limited is solved, original cost is saved, and the response of a power supply signal and the function realization of other functional circuits are improved. In addition, the on-chip capacitor corresponding to the functional circuit of the logic chip to be provided with the charge in the storage chip is adopted, so that the problems of high cost and complex structure caused by the need of additionally adding an off-chip capacitor for improving the capacitance value of the on-chip capacitor of the logic chip are solved.
According to some embodiments, as shown in fig. 6, an embodiment of the present application further provides an electronic device 700, which may include:
the logic chip 710 and the memory chip 720 having the memory chip borrowing capacitance are connected, and the logic chip 710 and the memory chip 720 are connected.
Accordingly, the electronic device provided in the embodiment of the present invention includes the logic chip, and the capacitor circuit of the logic chip further includes: the storage chip borrows a capacitor which is arranged on the logic chip and is used for providing electric charge for a power consumption element of the logic chip functional circuit. Because the logic chip uses the capacitor in the storage chip, the capacitor is used as a power consumption element for providing charge for the logic chip. The problem that the capacitance value of the on-chip capacitor in unit area is limited is solved, original cost is saved, and the response of a power supply signal and the function realization of other functional circuits are improved. In addition, the on-chip capacitor corresponding to the functional circuit of the logic chip to be provided with the charge in the storage chip is adopted, so that the problems of high cost and complex structure caused by the need of additionally adding an off-chip capacitor for improving the capacitance value of the on-chip capacitor of the logic chip are solved.
According to some embodiments, as shown in fig. 7, an electronic device may include a logic chip 610 and a memory chip 620.
The logic chip 610 and the memory chip 620 may be connected by a 3D-IC three-dimensional integrated circuit technology, in which the memory chip for supplying electric charge to the power consuming element is disposed at a position corresponding to the logic chip and the power consuming element by using a capacitor.
By using the 3D-IC process technology, the memory chip can be vertically connected with the logic chip functional circuit by virtue of the capacitor, and the resistance value between the memory chip borrowed capacitor and the logic chip functional circuit is reduced to the greatest extent, so that the memory chip borrowed capacitor of the memory chip can be directly provided for any functional circuit in the logic chip to use.
The memory chip borrowing capacitor can be arranged close to a power consumption element of the logic chip functional circuit and used for providing electric charge for the power consumption element, wherein the memory chip borrowing capacitor is also used for providing electric charge for the memory chip.
In some examples, the memory chip borrowing capacitor may be an on-chip capacitor of the memory chip, for example, an on-chip capacitor in the memory chip. When a certain condition is satisfied, the on-chip capacitor in the memory chip may be provided in the logic chip to be used as the capacitor of the logic chip. That is, in this embodiment, the chip borrowing capacitor is provided from the memory chip to the logic chip for use when the logic chip and the memory chip satisfy a predetermined position and connection condition. In order to achieve the utilization efficiency of the capacitor, the chip borrowing capacitor may be shared by the memory chip and the logic chip when the logic chip and the memory chip satisfy a predetermined position and connection condition.
In some examples, the memory chip borrowing capacitor may be disposed near a power consuming element of the logic chip functional circuit, and the pin of the memory chip borrowing capacitor may be disposed around the power consuming element of the logic chip functional circuit, that is, a power consuming element in the functional circuit module or the module physically close to the surface of the logic chip. Or the connection between the component pins, that is, the pins of the storage chip via the capacitor are connected into the corresponding circuit of the logic chip functional circuit, so as to provide charges for the power consuming components in the logic chip functional circuit, so that the logic chip functional circuit can work normally.
In addition, regardless of the power consumption element in the functional circuit block or module physically close to the surface of the logic chip or the circuit in which the pin of the memory chip borrowing capacitor is connected to the corresponding logic chip functional circuit, the chip borrowing capacitor is borrowed from the memory chip for use by the logic chip when the logic chip and the memory chip satisfy certain position and connection conditions. In order to achieve the utilization efficiency of the capacitor, the chip borrowing capacitor may be shared by the Memory chip and the Logic chip when the Logic chip area and the Memory chip Memory area satisfy a predetermined position and connection condition. Specifically, the above scheme needs to satisfy that the chip borrows pins of a capacitor and needs to be connected to the logic chip and the memory chip.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; may be mechanically coupled, may be electrically coupled or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
While embodiments of the invention have been disclosed above, it is not limited to the applications set forth in the description and the embodiments, which are fully applicable in various fields of endeavor to which the invention pertains, and further modifications may readily be made by those skilled in the art, it being understood that the invention is not limited to the details shown and described herein without departing from the general concept defined by the appended claims and their equivalents.
Claims (10)
1. A3D logic chip capacitance circuit, comprising: the logic chip functional circuit and the memory chip borrow capacitors,
the storage chip is arranged on the logic chip by means of a capacitor and is used for providing electric charges for power consumption elements of the functional circuit of the logic chip.
2. The logic chip capacitor circuit as claimed in claim 1, wherein the storage chip borrowing capacitor is a high density capacitor provided with a high dielectric constant dielectric layer.
3. The logic chip capacitance circuit according to claim 1 or 2,
the storage chip is arranged close to a power consumption element of the logic chip functional circuit by a 3D-IC three-dimensional integrated circuit technology by means of a capacitor.
4. The logic chip capacitance circuit of claim 3,
the storage chip borrows one or more than two capacitors.
5. The logic chip capacitance circuit of claim 3,
the logic chip functional circuit comprises a switched capacitor circuit, and the storage chip is used for the switched capacitor circuit by virtue of a capacitor.
6. The logic chip capacitance circuit of claim 3,
the logic chip functional circuit comprises a linear voltage stabilizing circuit, and the storage chip is arranged at the voltage output end of the linear voltage stabilizing circuit by virtue of a capacitor.
7. The logic chip capacitance circuit of claim 3,
the logic chip functional circuit comprises a charge pump circuit, and the memory chip borrows a capacitor as a bootstrap capacitor of the charge pump circuit.
8. A logic chip, characterized by: comprising a logic chip capacitance circuit according to any of claims 1 to 7.
9. An electronic device, characterized in that: the logic chip comprises the logic chip as claimed in claim 8 and a memory chip provided with the memory chip borrowing capacitor, wherein the logic chip is connected with the memory chip.
10. The electronic device of claim 9, wherein the logic chip and the memory chip are connected by 3D-IC three-dimensional integrated circuit technology.
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Cited By (1)
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| CN117526705A (en) * | 2023-12-29 | 2024-02-06 | 中茵微电子(南京)有限公司 | Voltage doubling circuit based on Dickson voltage doubler |
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