CN112492373A - General type high definition display system based on FPGA for photoelectric platform - Google Patents
General type high definition display system based on FPGA for photoelectric platform Download PDFInfo
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/431—Generation of visual interfaces for content selection or interaction; Content or additional data rendering
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- H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
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- H04N21/440263—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the spatial resolution, e.g. for displaying on a connected PDA
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- H04N21/440281—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the temporal resolution, e.g. by frame skipping
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Abstract
The utility model provides a photoelectric platform is with general type high definition display system based on FPGA, including the FPGA chip, the video input sensor, peripheral power module, peripheral clock and two piece at least SSRAM memory, wherein, be provided with four at least video interfaces on the video input sensor, and its output is connected with the FPGA chip, the video input sensor is through its video interface and output with outside video transmission to the inside of FPGA chip, peripheral power module and peripheral clock all are connected with the FPGA chip, and carry out current supply and time for the FPGA chip respectively and transfer, carry out two way communication between SSRAM memory and the FPGA chip and be connected, carry out data access for the FPGA chip. The universal high-definition display system has good compatibility and strong adaptability, can conveniently and quickly upgrade and update related high-definition monitoring systems and video acquisition systems, is convenient to maintain, has good self-consistency, and is simple and easy to operate.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to a general high-definition display system based on an FPGA (field programmable gate array) for a photoelectric platform.
Background
The photoelectric platform is often hung on an aircraft for performing a detection task, and a photoelectric sensor is used for scanning and monitoring a target and serving as an eye of the aircraft. With the demand of the diversity of the aircraft tasks and the development of the technology, the SDI interface on the photoelectric platform is gradually replacing the analog video signal interface of the PAL system of the early year to become the standard video signal interface.
At present, some commercial conversion modules or conversion systems are available on the market for the conversion of SDI signals, but their products are limited in volume and structure, lack corresponding services, and cannot be applied to photoelectric platforms. Custom products are expensive and are difficult to size for compact photovoltaic platforms. The existing photoelectric products need to be obviously provided with the characteristics of upgradability, easy maintenance, extremely strong adaptability and the like due to the continuous improvement of functions of the photoelectric products. Therefore, it is necessary to develop a general high-definition display system for the optoelectronic platform.
Disclosure of Invention
In order to overcome the technical problems, the invention provides a universal high-definition display system which is suitable for a photoelectric platform, has good compatibility and strong adaptability, can conveniently and quickly upgrade and update a related high-definition monitoring system and a video acquisition system, is convenient to maintain, has good self consistency and is simple and easy to operate.
In order to solve the technical problems, the invention provides the following technical scheme: a general high-definition display system based on FPGA for a photoelectric platform comprises an FPGA chip, a video input sensor, a peripheral power supply module, a peripheral clock and at least two SSRAM memories, wherein the video input sensor is provided with at least four video interfaces, the output end of the video input sensor is connected with the FPGA chip, the video input sensor transmits external videos to the interior of the FPGA chip through the video interfaces and the output end of the video input sensor, the peripheral power supply module and the peripheral clock are both connected with the FPGA chip and respectively perform current supply and time calling for the FPGA chip, and the SSRAM memories are in bidirectional communication connection with the FPGA chip and perform data access for the FPGA chip;
the FPGA chip include NIOS treater and respectively with the receiving module that NIOS treater is connected, frame frequency conversion module and output module, wherein, NIOS treater and the host computer that can control are connected, be provided with the receipt SDI interface on the receiving module, this receipt SDI interface is connected with video input sensor's output, the receiving module is used for carrying out protocol conversion to the signal and handles, frame frequency conversion module carries out the two-way communication interaction with the SSRAM memory, be used for carrying out the conversion of frame frequency and resolution ratio to the signal that has accomplished protocol conversion, and buffer memory in the SSRAM memory, be provided with on the output module and send the SDI interface, this send SDI interface is connected with display device, output module is used for exporting and sending the signal that frame frequency conversion module handled.
Further, the video interfaces on the video input sensor comprise a visible light video interface I used for receiving 1920 × 1080 resolution and 30fps visible light video, a visible light video interface II used for receiving 1920 × 1080 resolution and 50fps visible light video, an infrared video interface III used for receiving 1920 × 1080 resolution and 25fps infrared video and an infrared video interface IV used for receiving 1920 × 1080 resolution and 60fps infrared video.
Furthermore, the FPGA chip further comprises a global clock module, a global reset module and an asynchronous processing module which are respectively connected with the NIOS processor, wherein the global clock module, the global reset module and the asynchronous processing module respectively provide different-frequency clock calling, reset signal calling and clock domain crossing signal processing for the NIOS processor, the receiving module, the frame frequency conversion module and the output module.
Furthermore, the global clock module is connected with a peripheral clock.
Furthermore, the input frame frequency is not less than the output frame frequency when the frame frequency conversion module performs frame frequency conversion on the signal.
Furthermore, the frame frequency conversion module comprises a preposed cache unit, a writing SSRAM unit, a state machine, a reading SSRAM unit and a postpositive cache unit; the output end of the preposed cache unit is connected with the input end of the write-in SSRAM unit and is used for preprocessing the signal which is converted by the protocol; the writing SSRAM unit is connected with the SSRAM memory and is interactively connected with the state machine and used for controlling the writing time sequence of the SSRAM memory and sending a writing request and executing a state machine writing command to the state machine; the state machine is in bidirectional communication connection with the SSRAM memory, the write-in SSRAM unit and the read SSRAM unit and is used for controlling the storage and reading of signals in the SSRAM memory; the reading SSRAM unit is connected with the SSRAM memory and is interactively connected with the state machine, and is used for controlling the reading time sequence of the SSRAM memory, sending a reading request to the state machine and executing a state machine reading command; the input end of the post-cache unit is connected with the output end of the reading SSRAM unit and is used for performing clock domain crossing cache processing on the signals.
The invention has the beneficial effects that:
the general high-definition display system based on the FPGA for the photoelectric platform can conveniently and quickly convert signals transmitted by different types of video interfaces so as to meet the display requirements of users on videos with different resolutions and different frame frequencies. The display system has strong universality, is suitable for various photoelectric platforms with SDI interfaces, has low overall manufacturing cost, good compatibility and strong adaptability, and can conveniently and quickly upgrade and update related high-definition monitoring systems and video acquisition systems after being installed. Meanwhile, the display system is convenient to maintain integrally, good in self-consistency and easy to operate, capacity can be saved to the maximum extent in the using process, accordingly, cost is saved, and the practical effect is good.
Drawings
FIG. 1 is a block diagram of the component structure of the present invention;
FIG. 2 is a schematic diagram of the internal structure of the FPGA chip and the SSRAM memory according to the present invention;
FIG. 3 is a block diagram of the processing flow between the FPGA chip and the SDI interface according to the present invention;
fig. 4 is a block diagram schematically illustrating the structure of the frame rate conversion module according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings:
a general high-definition display system based on FPGA for photoelectric platform comprises an FPGA chip, four video input sensor output ends connected with the FPGA chip through SDI, a peripheral power supply module, a peripheral clock and at least two SSRAM memories, wherein the video input sensor transmits external video to the interior of the FPGA chip through a video interface and an output end of the video input sensor, the peripheral power supply module and the peripheral clock are both connected with the FPGA chip and respectively supply current and adjust time for the FPGA chip, the SSRAM memory is in bidirectional communication connection with the FPGA chip to access data for the FPGA chip, the video interface on the video input sensor comprises a visible light video interface I for receiving 1920 x 1080 resolution and 30fps visible light video, and a visible light video interface II for receiving 1920 x 1080 resolution and 50fps visible light video, the infrared video interface III is used for receiving 1920 x 1080 resolution and 25fps infrared video, and the infrared video interface IV is used for receiving 1920 x 1080 resolution and 60fps infrared video;
the FPGA chip comprises an NIOS processor, a receiving module, a frame frequency conversion module, an output module, a global clock module, a global reset module and an asynchronous processing module, wherein the receiving module, the frame frequency conversion module, the output module, the global clock module, the global reset module and the asynchronous processing module are respectively connected with the NIOS processor, the NIOS processor is connected with a controllable upper computer, a receiving SDI interface is arranged on the receiving module and is connected with the output end of a video input sensor, the receiving module is used for carrying out protocol conversion processing on signals, the frame frequency conversion module is in bidirectional communication interaction with an SSRAM memory and is used for carrying out frame frequency and resolution conversion on the signals after the protocol conversion, the signals are cached in the SSRAM memory, the input frame frequency when the frame frequency conversion module carries out frame frequency conversion on the signals is not less than the output frame frequency, a sending SDI interface is arranged on the output module and is connected with a display device, and the output module is used for outputting and, the global clock module is connected with the peripheral clock, and the global clock module, the global reset module and the asynchronous processing module respectively provide clock calling with different frequencies, reset signal calling and clock domain crossing signal calling for the NIOS processor.
The frame frequency conversion module comprises a preposed cache unit, a writing SSRAM unit, a state machine, a reading SSRAM unit and a postposition cache unit; the output end of the preposed cache unit is connected with the input end of the write-in SSRAM unit and is used for preprocessing the signal which is converted by the protocol; the writing SSRAM unit is connected with the SSRAM memory and is interactively connected with the state machine and used for controlling the writing time sequence of the SSRAM memory and sending a writing request and executing a state machine writing command to the state machine; the state machine is in bidirectional communication connection with the SSRAM memory, the write-in SSRAM unit and the read SSRAM unit and is used for controlling the storage and reading of signals in the SSRAM memory; the reading SSRAM unit is connected with the SSRAM memory and is interactively connected with the state machine, and is used for controlling the reading time sequence of the SSRAM memory, sending a reading request to the state machine and executing a state machine reading command; the input end of the post-cache unit is connected with the output end of the reading SSRAM unit and is used for performing clock domain crossing processing on signals.
The general high-definition display system based on the FPGA for the photoelectric platform is used for converting frame frequency and resolution by utilizing the mode of the FPGA and the SSRAM, can input four common frame frequency structures, namely 25 frames, 30 frames, 50 frames and 60 frames, and can freely select the resolution, and the conversion and the output of two paths of videos can be realized at most in practical use, and the conversion frame frequency format which can be realized is shown in the following table:
TABLE 1 input/output frame frequency relationship Table
In the table, the capital letter "Y" indicates that output is possible, and the capital letter "N" indicates that output is not possible.
The general high-definition display system based on the FPGA for the photoelectric platform generally comprises an FPGA chip, an SSRAM memory, a peripheral power supply circuit module and a peripheral clock, and the structure of the display system is shown in figure 1.
In the general high-definition display system based on the FPGA for the photoelectric platform, the number of video interfaces on a video input sensor is mainly four, and the video interfaces comprise a visible light video interface I, a visible light video interface II, an infrared video interface III and an infrared video interface IV. The method can be used for receiving visible light video (1920 × 1080 resolution, 30 fps), visible light video (1920 × 1080 resolution, 50 fps), infrared video (1920 × 1080 resolution, 25 fps) and infrared video (1920 × 1080 resolution, 60 fps) respectively, and a data transmission flow with high efficiency, convenience and strong system compatibility is required to be designed for accurately converting the four video input signals into high-speed serial SDI signals finally for transmission. The four video signals can directly input SDI signals into the FPGA chip through the video interface, and 2 SSRAM memories are utilized under the control of an NIOS processor embedded in the FPGA chip. The input video signal is transmitted to the frame frequency conversion module, the video signal after resolution and frame frequency conversion is output to an output module in the FPGA chip for corresponding processing, the processed result is output to an interface for sending SDI, and the internal structures of the FPGA chip and the SSRAM memory of the general frame frequency conversion system are shown in figure 2.
The specific data processing flow of the FPGA-based universal high-definition display system for the photoelectric platform comprises the following steps:
the processing flow between the FPGA chip and the SDI interface is shown in the attached figure 3: the four paths of videos are input through a receiving SDI interface in the FPGA chip, input signals enter a receiving module to be processed to a certain extent, after the processing is finished, protocol conversion is carried out on the processed data for facilitating subsequent processing and calculation, and converted results enter a frame frequency conversion module to be subjected to frame frequency conversion and resolution conversion.
The frame frequency conversion module controls the data to enter on one hand and controls the data to enter the SSRAM memory to be correspondingly cached on the other hand. In order to save capacity and simultaneously consider cost saving, the display system of the invention adopts 2 pieces of SSRAM memory with 36M size to realize cache.
And outputting the result after the frame frequency conversion to an output module of the FPGA chip, processing the data by the output module, converting the data into a serial single-bit line signal, and outputting the serial single-bit line signal through a sending SDI interface. The conversion of the frame rate and the resolution of two paths of videos can be realized at most, and visible light videos (1920 × 1080 resolution, 60 fps), infrared videos (1920 × 1080 resolution, 60 fps) and visible light videos (1920 × 1080 resolution, 50 fps) can be converted into video signals with 1920 × 1080 resolution or less and 50 frames or less.
All the SDI interfaces are communication interfaces, namely serial digital interfaces, which are widely used high-definition digital input and output interfaces, the SDI interfaces are divided into HD-SDI and 3G-SDI which are SD-SDI and high-definition application according to the speed, the corresponding speed of the SD-SDI is 270Mb/s, the corresponding speed of the HD-SDI is 1.485Gb/s, and the speed of the 3G-SDI is much higher than that of the SD-SDI and the HD-SDI and reaches 2.97 Gb/s. The HD-SDI is widely applied to cameras, optical transmitters and receivers and high-definition monitoring systems, can be used for converting analog signals into the high-definition monitoring systems very conveniently by adopting the HD-SDI interface, is not influenced by a transmission network, and is very effective to scenes with high-definition requirements. The 3G-SDI is widely applied compared with the HD-SDI, and is an interface which is provided for people in modern life and has the characteristics of high speed and no compression for a high-quality and low-delay system. Meanwhile, the high-speed 3G-SDI interface can be downward compatible and can be compatible with HD-SDI and SD-SDI, so that modern high-definition monitoring systems and video acquisition systems can be conveniently upgraded and updated.
The display system is also provided with an asynchronous processing module, and because a plurality of different clocks exist in the display system, the processing of clock domain crossing is required to be carried out for many times.
The display system is also provided with a global reset module which outputs data to each module by using a global network, and because the data is processed by adopting a synchronous capture and asynchronous release mode, reset signals of all the modules are generated by the global reset module.
Because multiple paths of SDI signals need to be compatible and the clocks of each path are different, in order to ensure the normal and stable work of the clocks of each path, the invention adopts the method of the global clock, the required clocks with different frequencies are all generated by the global clock module, and the generated clocks are laid out and wired by utilizing the wiring mode of the global clock in the FPGA, so that the SKEW (SKEW) and JITTER (JITTER) of the clocks in each module meet the requirements.
The FPGA chip is internally provided with the embedded NIOS processor which is used for controlling the whole display system by the upper computer, and the switching among various conversions can be realized through the control of the upper computer.
The frame frequency conversion module is a key and difficult module of the display system, is used for converting frame frequency and resolution in each channel, and comprises five sub-modules, the relationship among the sub-modules is shown in figure 4, and the state machine plays a role in core control. The five major submodules are respectively: the device comprises a front cache unit, a write-in SSRAM unit, a state machine, a read SSRAM unit and a rear cache unit.
The prepositive cache unit is a module used for converting video data into an SSRAM memory clock domain for preprocessing by the display system, an input data stream is converted into a 32-bit signal with 230M frequency and is output to the SSRAM memory by the prepositive cache unit, meanwhile, the prepositive cache unit module adopts an automatic reading and writing function, namely, whether the output is at the end of a line of an image can be automatically judged, proper processing is carried out at the end, and after the processing is finished, the processing result is sent to the writing SSRAM unit.
The main function of the write-in SSRAM unit is to control the write-in time sequence of the SSRAM memory, and to provide a write-in Request to the state machine when the data comes, if the result after the processing by the state machine is a Request which is allowed to be written in the SSRAM unit, the corresponding channel can be selected at this time, the write-in operation is carried out according to the priority sequence, if the Request which is allowed to be written in the SSRAM unit is not allowed, the write-in unit carries out corresponding processing according to the logic, and the cache or discard is selected according to the result after the processing.
The state machine in the frame frequency conversion module is the core of the whole frame frequency conversion module, and the state machine module is mainly used for overall flow control and data flow control, and comprises data resolution conversion processing, channel selection, priority selection, state processing, abnormal condition processing and the like. When a write-in SSRAM unit submits a write-in request, the state machine processes the request, determines whether to output a result to the write-in SSRAM unit according to the processed result, outputs corresponding SSRAM address information and channel information at the same time of outputting the result, and outputs the current state to the write-in SSRAM unit. When the state machine reads the SSRAM unit and puts forward a reading request, the state machine needs to process the reading request, outputs a result to the reading SSRAM unit according to the processed result, simultaneously outputs a corresponding SSRAM address and channel information, outputs the state at the moment to the reading SSRAM unit, and carries out corresponding processing in the reading SSRAM unit.
The main function of reading the SSRAM unit is to control the read-out time sequence of the SSRAM memory, and when data needs to be read, a read request is provided for the state machine, if the result processed by the state machine is that the SSRAM unit is approved to be read, a corresponding channel needs to be selected according to the result processed by the state machine, the read operation is carried out according to the priority and the time sequence, if the state machine is not approved to be read, the read module carries out a series of processing, and the cache result is output according to the processed result.
The post-buffer unit is used for cross-clock domain processing, 32-bit signals input into the SSRAM with the speed of 230M are converted into multi-bit parallel signals required by a subsequent device after passing through the post-buffer unit module, meanwhile, the post-buffer unit module adopts automatic reading and writing functions, namely whether the ending of one frame of an output image is judged by self, proper processing is carried out at the ending part of the image, and after the processing is finished, the processed result is sent to the internal FIFO.
Claims (6)
1. The utility model provides a photoelectric platform is with general type high definition display system based on FPGA which characterized in that: the display system comprises an FPGA chip, a video input sensor, a peripheral power supply module, a peripheral clock and at least two SSRAM memories, wherein the video input sensor is provided with at least four video interfaces, the output end of the video input sensor is connected with the FPGA chip, the video input sensor transmits external videos to the interior of the FPGA chip through the video interfaces and the output end of the video input sensor, the peripheral power supply module and the peripheral clock are both connected with the FPGA chip and respectively supply current and transfer time for the FPGA chip, and the SSRAM memories are in bidirectional communication connection with the FPGA chip and access data for the FPGA chip;
the FPGA chip include NIOS treater and respectively with the receiving module that NIOS treater is connected, frame frequency conversion module and output module, wherein, NIOS treater and the host computer that can control are connected, be provided with the receipt SDI interface on the receiving module, this receipt SDI interface is connected with video input sensor's output, the receiving module is used for carrying out protocol conversion to the signal and handles, frame frequency conversion module carries out the two-way communication interaction with the SSRAM memory, be used for carrying out the conversion of frame frequency and resolution ratio to the signal that has accomplished protocol conversion, and buffer memory in the SSRAM memory, be provided with on the output module and send the SDI interface, this send SDI interface is connected with display device, output module is used for exporting and sending the signal that frame frequency conversion module handled.
2. The FPGA-based universal high-definition display system for the photoelectric platform as claimed in claim 1, wherein: the video interfaces on the video input sensor comprise a visible light video interface I used for receiving a 1920 × 1080 resolution and 30fps visible light video, a visible light video interface II used for receiving a 1920 × 1080 resolution and 50fps visible light video, an infrared video interface III used for receiving a 1920 × 1080 resolution and 25fps infrared video and an infrared video interface IV used for receiving a 1920 × 1080 resolution and 60fps infrared video.
3. The FPGA-based universal high-definition display system for the photoelectric platform as claimed in claim 1, wherein: the FPGA chip further comprises a global clock module, a global reset module and an asynchronous processing module which are respectively connected with the NIOS processor, wherein the global clock module, the global reset module and the asynchronous processing module respectively provide different-frequency clock calling, reset signal calling and clock domain crossing signal processing for the NIOS processor, the receiving module, the frame frequency conversion module and the output module.
4. The FPGA-based universal high-definition display system for the photoelectric platform as claimed in claim 3, wherein: the global clock module is connected with a peripheral clock.
5. The FPGA-based universal high-definition display system for the photoelectric platform as claimed in claim 1, wherein: the input frame frequency is not less than the output frame frequency when the frame frequency conversion module performs frame frequency conversion on the signals.
6. The FPGA-based universal high-definition display system for the photoelectric platform as claimed in claim 1, wherein: the frame frequency conversion module comprises a preposed cache unit, a writing SSRAM unit, a state machine, a reading SSRAM unit and a postposition cache unit; the output end of the preposed cache unit is connected with the input end of the write-in SSRAM unit and is used for preprocessing the signal which is converted by the protocol; the writing SSRAM unit is connected with the SSRAM memory and is interactively connected with the state machine and used for controlling the writing time sequence of the SSRAM memory and sending a writing request and executing a state machine writing command to the state machine; the state machine is in bidirectional communication connection with the SSRAM memory, the write-in SSRAM unit and the read SSRAM unit and is used for controlling the storage and reading of signals in the SSRAM memory; the reading SSRAM unit is connected with the SSRAM memory and is interactively connected with the state machine, and is used for controlling the reading time sequence of the SSRAM memory, sending a reading request to the state machine and executing a state machine reading command; the input end of the post-cache unit is connected with the output end of the reading SSRAM unit and is used for performing clock domain crossing processing on signals.
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