CN112486739B - BIOS switching method, architecture and control switching method - Google Patents
BIOS switching method, architecture and control switching method Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
Abstract
The application discloses a BIOS switching method, a BIOS switching architecture and a BIOS switching control method, which are applied to a controller and comprise the following steps: detecting the running state of the BIOS currently running in the main memory or the standby memory; if the running state is the starting state, sending a corresponding timing adjusting signal to the CPLD according to the current running task of the BIOS; and if the running state is the starting completion state, sending a BIOS verification signal and a watchdog ending signal to the CPLD. According to the method and the device, the watchdog timing time of the CPLD is dynamically adjusted by the controller according to the running state and the running task of the BIOS, once the BIOS has a problem, the watchdog of the CPLD can be triggered as soon as possible and switched to the standby BIOS for restarting as soon as possible without waiting according to the preset fixed timing time, so that the starting progress is accelerated, and after the main BIOS fails, the CPLD can be redirected to the failed main BIOS through the BIOS verification signal, so that a user can maintain the CPLD, the maintenance difficulty is reduced, and the maintenance efficiency is improved.
Description
Technical Field
The present invention relates to the field of computers, and in particular, to a BIOS switching method, architecture, and control switching method.
Background
BIOS, whether an important ring in INTEL or AMD system platforms, has the main functions of initializing and testing hardware, and loading a boot program for storage and loading an operating system from the boot program. Today, either INTEL or AMD published platforms are designed using a BIOS. However, the BIOS needs to be updated frequently, but if the update fails or half of the update is powered off, the entire machine cannot be booted.
The current Dual Bios architecture utilizes a watchdog inside the CPLD to determine whether the Bios has run out, as shown in fig. 1. The Bios will use a signal to tell the CPLD Bios whether it has run out, so the watchdog time needs to be set long to avoid switching to the second Bios if it has not run out. In the hardware circuit, a Switch IC is also required to Switch the SPI signal.
In the prior art, if the system architecture is large, the watchdog needs to be designed for a long time, sometimes ten minutes and several minutes later, but if the Bios is hang up or broken after the beginning, the user needs to wait for the ten minutes and several minutes before switching to the second Bios.
Therefore, a more flexible and efficient BIOS switching method is needed.
Disclosure of Invention
In view of this, the present invention provides a BIOS switching method, architecture and control switching method, which are more flexible and more efficient. The specific scheme is as follows:
a BIOS switching control method is applied to a controller and comprises the following steps:
detecting the running state of the BIOS currently running in the main memory or the standby memory;
if the running state is the starting state, sending a corresponding timing adjusting signal to the CPLD according to the current running task of the BIOS so as to dynamically adjust the timing time of the watchdog in the CPLD according to the current running task of the BIOS;
if the running state is the starting completion state, sending a BIOS verification signal and a watchdog completion signal to the CPLD, so that the CPLD judges whether the BIOS is a main BIOS or not by using the BIOS verification signal, and closing the timing of the watchdog by using the watchdog completion signal.
Optionally, the process of sending a corresponding timing adjustment signal to the CPLD according to the current running task of the BIOS to dynamically adjust the timing time of the watchdog in the CPLD according to the current running task of the BIOS includes:
determining target timing time corresponding to the current running task according to the current running task of the BIOS and a preset mapping relation;
generating the timing adjustment signal by using the target timing time;
sending the timing adjusting signal to the CPLD to dynamically adjust the timing time of the watchdog in the CPLD;
the mapping relation is a pre-established corresponding relation between the current running task of the BIOS and the timing time.
Optionally, the method further includes:
and if the running state is a normal running state, sending a watchdog timing clearing signal to the CPLD so that the CPLD clears the timing of the watchdog by using the watchdog timing clearing signal.
Optionally, the method further includes:
and if the running state is a preset timing pause state, sending the watchdog stop signal to the CPLD so that the CPLD closes the timing of the watchdog by using the watchdog stop signal.
The invention also discloses a BIOS switching method, which is applied to the CPLD and comprises the following steps:
receiving a starting signal and starting a watchdog;
adjusting the timing time of the watchdog according to the timing adjusting signal sent by the controller;
receiving a watchdog ending signal sent by the controller, and closing the watchdog by using the watchdog ending signal;
when the watchdog is overtime, switching the BIOS and restarting;
receiving a BIOS verification signal sent by the controller, judging whether the current BIOS is a main BIOS by using the BIOS verification signal, if not, pointing to the main BIOS again so that a user can control the main BIOS;
the watchdog ending signal is a signal sent by the controller to close the watchdog when the controller detects that the running state of the currently running BIOS is the completion of starting.
Optionally, the method further includes:
and receiving a watchdog timing clearing signal sent by the controller, and clearing the watchdog timing.
Optionally, the method further includes:
receiving a watchdog stop signal sent by the controller, and closing the watchdog by using the watchdog stop signal;
the watchdog stop signal is a signal sent by the controller to close the watchdog when the controller detects that the running state of the currently running BIOS is a timing pause state.
The invention also discloses a BIOS switching architecture, comprising: a controller for executing the method as described above, a CPLD for executing the method as described above, a main memory, and a spare memory;
the controller is respectively connected with the CPLD, the main memory and the spare memory, and the CPLD is respectively connected with the main memory and the spare memory.
Optionally, the controller is a PCH or SOC.
Optionally, the controller is connected to the CPLD through a CS signal line and an LPC BUS, respectively;
the controller sends a timing adjustment signal, a watchdog timing clearing signal, a watchdog ending signal, a watchdog stopping signal and a BIOS verification signal through the LPC BUS.
Optionally, the CPLD is connected to the main memory and the spare memory through a first CS signal line and a second CS signal line, respectively.
Optionally, the controller is connected to the main memory and the standby memory through a clock and a data line, respectively, and is configured to obtain the operating state of the BIOS.
The invention discloses a BIOS switching control method applied to a controller, which comprises the following steps: detecting the running state of the BIOS currently running in the main memory or the standby memory; if the running state is the starting state, sending a corresponding timing adjusting signal to the CPLD according to the current running task of the BIOS so as to dynamically adjust the timing time of the watchdog in the CPLD according to the current running task of the BIOS; if the running state is the starting completion state, a BIOS verification signal and a watchdog ending signal are sent to the CPLD, so that the CPLD judges whether the BIOS is the main BIOS or not by using the BIOS verification signal, and the watchdog ending signal is used for closing the timing of the watchdog.
According to the invention, the watchdog timing time of the CPLD is dynamically adjusted by the controller according to the running state and the running task of the BIOS, once the BIOS has a problem, the watchdog of the CPLD can be triggered as soon as possible, and switched to the standby BIOS for restarting as soon as possible without waiting according to the preset fixed timing time, so that the starting progress is greatly accelerated, and after the main BIOS fails, the CPLD can be redirected to the failed main BIOS through the BIOS verification signal, so that a user can maintain the main BIOS, the maintenance difficulty is reduced, and the maintenance efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a diagram of the Dual Bios architecture of the prior art;
FIG. 2 is a flow chart illustrating a BIOS switching control method according to an embodiment of the present invention;
FIG. 3 is a flow chart illustrating another BIOS switching control method according to an embodiment of the present invention;
FIG. 4 is a flow chart illustrating a BIOS control method according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a BIOS switching architecture according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a BIOS switching control method, which is shown in figure 2 and is applied to a controller, and the method comprises the following steps:
s11: the running state of the BIOS currently running in the main memory or the standby memory is detected.
Specifically, a main BIOS is stored in a main memory, a standby BIOS is stored in a standby memory, and in a default state, after the computer is started, the main BIOS in the main memory runs to execute a boot program.
Specifically, after the BIOS is started, the controller may obtain an operating state of the currently operating BIOS, where the operating state of the BIOS may be divided into a plurality of operating states including a start state, a start completion state, a normal operating state after the start completion state, a timing pause state, and the like; different running tasks can be included in different states, and the running tasks are different in time consumption, so that the running state of the BIOS is detected, and the work group state and the timing time of the watchdog can be adjusted later.
S12: if the running state is the starting state, a corresponding timing adjusting signal is sent to the CPLD according to the current running task of the BIOS, so that the timing time of the watchdog in the CPLD is dynamically adjusted according to the current running task of the BIOS.
Specifically, the starting state in the running state of the BIOS includes multiple running tasks, the time required by each running task is different, in order to save time and quickly determine whether the BIOS needs to be switched when the BIOS is running normally, the controller obtains the running state of the current running BIOS and further knows the running task being executed by the current BIOS, and sends a corresponding timing adjustment signal to the CPLD according to the task executed by the current BIOS by using a correspondence relationship between the pre-designed timing time and the running task, so as to dynamically adjust the timing time of the watchdog in the CPLD.
For example, if the current BIOS is executing a detection hardware task that consumes a relatively short time, the corresponding timing time may be 6 seconds, and the controller sends a corresponding timing adjustment signal to the CPLD to adjust the timing time of the watchdog of the CPLD to 6 seconds; when the current running task executed by the BIOS is changed into the checking RAM which consumes longer time, the corresponding timing time can be 20 seconds, the controller sends a corresponding timing adjusting signal to the CPLD, and the timing time of the watchdog of the CPLD is adjusted to be 20 seconds, so that the timing time of the watchdog in the CPLD is dynamically adjusted.
It is understood that before the CPLD watchdog is dynamically adjusted, the watchdog timer in the CPLD is set to a default value, for example, the default value may be 10 seconds.
S13: if the running state is the starting completion state, a BIOS verification signal and a watchdog ending signal are sent to the CPLD, so that the CPLD judges whether the current BIOS is the main BIOS or not by using the BIOS verification signal, and the watchdog ending signal is used for closing the timing of the watchdog.
Specifically, if the BIOS is started up and indicates that the BIOS is successfully operated, a watchdog end signal is sent to the CPLD without continuously monitoring the BIOS. Because the current BIOS may be the main BIOS, or the CPLD switches to the standby BIOS after the main BIOS fails, the BIOS verification signal is sent to the CPLD, so that the CPLD judges whether the current BIOS is the main BIOS by using the BIOS verification signal, if the current BIOS is the main BIOS, no action is needed, and if the standby BIOS indicates that the main BIOS fails, for this reason, the CPLD needs to point to the main memory again, so that a user can maintain the main BIOS in the main memory after the boot is completed.
Therefore, in the embodiment of the invention, the watchdog timing time of the CPLD is dynamically adjusted by the controller according to the running state and the running task of the BIOS, once the BIOS has a problem, the watchdog of the CPLD can be triggered as soon as possible and switched to the standby BIOS for rebooting as soon as possible without waiting according to the preset fixed timing time, so that the booting progress is greatly accelerated, and after the main BIOS fails, the CPLD can be redirected to the failed main BIOS through the BIOS verification signal, so that a user can maintain the main BIOS, the maintenance difficulty is reduced, and the maintenance efficiency is improved.
The embodiment of the invention discloses a specific method, and compared with the previous embodiment, the embodiment further explains and optimizes the technical scheme. Referring to fig. 3, specifically:
s21: the running state of the BIOS currently running in the main memory or the standby memory is detected.
S22: and if the running state is the starting state, determining the target timing time corresponding to the current running task according to the current running task of the BIOS and a preset mapping relation.
Specifically, the corresponding relationship between various running tasks of the BIOS and the timing time is pre-established, for example, the target timing time corresponding to the hardware task is detected to be 6 seconds, and the target timing time corresponding to the RAM task is detected to be 20 seconds, so that the mapping relationship between the two running tasks and the respective target timing times can be obtained. Therefore, when the running task of the currently running BIOS is determined, the target timing time corresponding to the corresponding running task can be quickly determined according to the pre-established mapping relation.
S23: generating a timing adjustment signal by using the target timing time;
s24: and sending a timing adjustment signal to the CPLD to dynamically adjust the timing time of the watchdog in the CPLD.
Specifically, the CPLD receives the timing adjustment signal, and can adjust the timing time of the watchdog running by itself according to the target timing time recorded in the timing adjustment signal.
S25: if the running state is starting completion, sending a BIOS verification signal and a watchdog ending signal to the CPLD, so that the CPLD judges whether the current BIOS is the main BIOS or not by using the BIOS verification signal and closes the timing of the watchdog by using the watchdog ending signal;
s26: and if the running state is the normal running state, sending a watchdog timing clearing signal to the CPLD so that the CPLD clears the timing of the watchdog by using the watchdog timing clearing signal.
It can be understood that, if the current BIOS is in a normal operation state, the controller sends the watchdog timing clearing signal to the CPLD at regular time, so that the CPLD clears the timing of the watchdog by using the watchdog timing clearing signal, and the CPLD is prevented from triggering the watchdog program to switch the BIOS and restart the computer.
S27: and if the running state is a preset timing pause state, sending a watchdog stop signal to the CPLD so that the CPLD closes the timing of the watchdog by using the watchdog stop signal.
Specifically, in the boot process, the BIOS needs to be manually set sometimes, for example, a user enters a BIOS Setup Menu interface to set the BIOS or a certain task executed by the BIOS consumes a long time, for example, a Check Ram task, such a situation may be set to a timing pause state in advance, and in such a state, the BIOS runs normally, but a large amount of time is needed before the completion of the start-up, so that a watchdog stop signal may be sent to the CPLD, so that the CPLD uses the watchdog stop signal to close the timing of the watchdog, and the watchdog in the CPLD is prevented from being started by mistake.
The embodiment of the invention also discloses a BIOS switching method, which is applied to a CPLD and shown in fig. 4, and includes:
s31: and receiving a starting signal and starting the watchdog.
Specifically, the CPLD may detect whether the S3 signal is at a high level, and if so, prove that the computer is powered on, and at this time, start the watchdog to time for switching to the BIOS to restart when the BIOS fails.
S32: adjusting the timing time of the watchdog according to a timing adjusting signal sent by the controller;
s33: and receiving a watchdog ending signal sent by the controller, and closing the watchdog by using the watchdog ending signal.
The watchdog ending signal is a signal sent by the controller to close the watchdog when the controller detects that the running state of the currently running BIOS is the completion of starting.
S34: when the watchdog is overtime, the BIOS is switched and the computer is restarted.
Specifically, if the controller does not send the watchdog timing clearing signal, the timing time of the watchdog is overtime, which indicates that the currently running BIOS fails, the BIOS is switched, and the computer is restarted, and another BIOS is used to execute the startup program.
It can be understood that the CPLD is turned on for the first time by default to point to the main BIOS, and if the main BIOS is turned on using the standby BIOS after a failure, the user will maintain the main BIOS as soon as possible, and will also point to the main BIOS for the next time of turning on, and turn on using the main BIOS.
S35: and receiving a BIOS verification signal sent by the controller, judging whether the current BIOS is the main BIOS by using the BIOS verification signal, and if not, pointing to the main BIOS again so that a user can control the main BIOS.
Specifically, if the current BIOS is the main BIOS, the operation is not performed, and the monitoring of the BIOS is finished.
S36: and receiving a watchdog timing clearing signal sent by the controller, and clearing the watchdog timing.
S37: and receiving the watchdog stop signal sent by the controller, and closing the watchdog by using the watchdog stop signal.
The watchdog stop signal is a signal sent by the controller to close the watchdog when the controller detects that the running state of the currently running BIOS is a timing pause state.
It should be noted that there is no execution sequence between S33 and S37, and the execution sequence is a parallel execution sequence, and the corresponding step is executed under a condition that is satisfied, for example, a corresponding control signal is received or a corresponding trigger condition is satisfied, and the step is not executed if the condition is not satisfied.
Therefore, in the embodiment of the invention, the watchdog timing time of the CPLD is dynamically adjusted by the controller according to the running state of the BIOS, once the BIOS has a problem, the watchdog of the CPLD can be triggered as soon as possible and switched to the standby BIOS for restarting as soon as possible without waiting according to the preset fixed timing time, so that the starting progress is greatly accelerated, and after the main BIOS fails, the CPLD can be redirected to the failed main BIOS through the BIOS verification signal, so that a user can maintain the main BIOS, the maintenance difficulty is reduced, and the maintenance efficiency is improved.
Correspondingly, an embodiment of the present invention further discloses a BIOS switching architecture, and referring to fig. 5, the interpersonal device includes: a controller 1 for executing the method as described above, a CPLD 2 for executing the method as described above, a main memory 3 and a spare memory 4;
the controller 1 is connected to the CPLD 2, the main memory 3, and the reserve memory 4, respectively, and the CPLD 2 is connected to the main memory 3 and the reserve memory 4, respectively.
Wherein, the controller 1 is a PCH or SOC.
Specifically, the controller 1 is connected with the CPLD 2 through a CS signal line CS and an LPC BUS, respectively;
the controller 1 sends a timing adjustment signal, a watchdog timing clear signal, a watchdog end signal, a watchdog stop signal and a BIOS verification signal through the LPC BUS.
Specifically, the CPLD 2 is connected to the main memory 3 and the spare memory 4 through a first CS signal line CS1 and a second CS signal line CS2, respectively.
Specifically, the controller 1 is connected to the main memory 3 and the spare memory 4 via a clock and Data line Clk & Data, respectively, for acquiring the operating status of the BIOS.
Finally, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the components and steps of the various examples have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The technical content provided by the present invention is described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the above description of the examples is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (12)
1. A BIOS switching control method is applied to a controller and comprises the following steps:
detecting the running state of the BIOS currently running in the main memory or the standby memory;
if the running state is the starting state, sending a corresponding timing adjusting signal to the CPLD according to the current running task of the BIOS so as to dynamically adjust the timing time of the watchdog in the CPLD according to the current running task of the BIOS;
if the running state is the starting completion state, sending a BIOS verification signal and a watchdog completion signal to the CPLD, so that the CPLD judges whether the BIOS is a main BIOS or not by using the BIOS verification signal, and closing the timing of the watchdog by using the watchdog completion signal.
2. The method for controlling switching of BIOS according to claim 1, wherein said process of sending a corresponding timing adjustment signal to a CPLD according to the current running task of said BIOS to dynamically adjust the timing time of a watchdog in said CPLD according to the current running task of said BIOS comprises:
determining target timing time corresponding to the current running task according to the current running task of the BIOS and a preset mapping relation;
generating the timing adjustment signal by using the target timing time;
sending the timing adjusting signal to the CPLD to dynamically adjust the timing time of the watchdog in the CPLD;
the mapping relation is a pre-established corresponding relation between the current running task of the BIOS and the timing time.
3. The BIOS switching control method of claim 1 or 2, further comprising:
and if the running state is a normal running state, sending a watchdog timing clearing signal to the CPLD so that the CPLD clears the timing of the watchdog by using the watchdog timing clearing signal.
4. The BIOS switching control method of claim 1 or 2, further comprising:
and if the running state is a preset timing pause state, sending the watchdog stop signal to the CPLD so that the CPLD closes the timing of the watchdog by using the watchdog stop signal.
5. A BIOS switching method is applied to a CPLD and comprises the following steps:
receiving a starting signal and starting a watchdog;
adjusting the timing time of the watchdog according to a timing adjusting signal sent by a controller;
receiving a watchdog ending signal sent by the controller, and closing the watchdog by using the watchdog ending signal;
when the watchdog is overtime, switching the BIOS and restarting;
receiving a BIOS verification signal sent by the controller, judging whether the current BIOS is a main BIOS by using the BIOS verification signal, if not, pointing to the main BIOS again so that a user can control the main BIOS;
the watchdog ending signal is a signal sent by the controller to close the watchdog when the controller detects that the running state of the currently running BIOS is the completion of starting.
6. The BIOS switching method of claim 5, further comprising:
and receiving a watchdog timing clearing signal sent by the controller, and clearing the watchdog timing.
7. The BIOS switching method of claim 5, further comprising:
receiving a watchdog stop signal sent by the controller, and closing the watchdog by using the watchdog stop signal;
the watchdog stop signal is a signal sent by the controller to close the watchdog when the controller detects that the running state of the currently running BIOS is a timing pause state.
8. A BIOS switching architecture, comprising: a controller for performing the method of any one of claims 1 to 4, a CPLD for performing the method of any one of claims 5 to 7, a main memory and a spare memory;
the controller is respectively connected with the CPLD, the main memory and the spare memory, and the CPLD is respectively connected with the main memory and the spare memory.
9. The BIOS switching architecture of claim 8 wherein the controller is a PCH or SOC.
10. The BIOS switching architecture of claim 9 wherein the controller is connected to the CPLD via CS signal lines and LPC BUS, respectively;
the controller sends a timing adjustment signal, a watchdog timing clearing signal, a watchdog ending signal, a watchdog stopping signal and a BIOS verification signal through the LPC BUS.
11. The BIOS switching architecture of claim 10, wherein the CPLD is connected to the main memory and the spare memory via first and second CS signal lines, respectively.
12. The BIOS switching architecture of claim 11, wherein the controller is coupled to the main memory and the standby memory via clock and data lines, respectively, for obtaining the operating status of the BIOS.
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