CN112783690A - Crash processing method and device - Google Patents
Crash processing method and device Download PDFInfo
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- CN112783690A CN112783690A CN201911086581.4A CN201911086581A CN112783690A CN 112783690 A CN112783690 A CN 112783690A CN 201911086581 A CN201911086581 A CN 201911086581A CN 112783690 A CN112783690 A CN 112783690A
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- 238000001514 detection method Methods 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims description 13
- 238000004891 communication Methods 0.000 claims description 7
- 230000006870 function Effects 0.000 description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1438—Restarting or rejuvenating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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Abstract
The invention provides a crash processing method and a device, wherein the crash processing method comprises the following steps: the single chip microcomputer sends a detection signal to the processor; and when the processor is detected to be in a dead halt state, the singlechip controls the processor to restart through the power module. According to the crash processing method and the crash processing device, when the processor is in the crash state, the processor can be manually or automatically controlled to be powered off and restarted, so that the normal working state is recovered, and the user experience is improved.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a crash handling method and apparatus.
Background
The android system can support functions of a radio, music, navigation and the like of a traditional car machine, can be networked, has bright and colorful interfaces, is open in platform and rich in application, and is optimized in a series of ways according to the requirement of having a car, so that the android system is popular with more and more people, and more car machines using the android operating system as a main operating system are used at present.
However, the android system also has a big problem that the android system is easy to crash, and the restarting is a common operation for solving the crash problem, but the terminal in the prior art does not have the function of automatic restarting in the processor crash state, and only depends on manual operation, so that the operation is inconvenient, and if the terminal is not found in time, the terminal is always in the state of stopping running, so that the working efficiency of the terminal is influenced.
Therefore, a crash handling method and apparatus are needed to solve the above-mentioned problems.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a crash processing method and a crash processing device, which can control a power module to power off a processor through a single chip microcomputer when the processor is in a crash state, so that the processor is restarted.
The technical problem to be solved by the invention is realized by adopting the following technical scheme:
a crash handling method comprising: the single chip microcomputer sends a detection signal to the processor; and when the processor is detected to be in a dead halt state, the singlechip controls the processor to restart through the power module.
In a preferred embodiment of the present invention, the step of sending the detection signal to the processor by the single chip microcomputer includes: if the processor is in a working state, sending feedback information to the single chip microcomputer after receiving the detection signal; and if the single chip microcomputer does not receive the feedback information sent by the processor within the preset time, determining that the processor is in a dead halt state.
In a preferred embodiment of the present invention, the single chip sends the detection signal to the processor according to a preset time interval.
In a preferred embodiment of the present invention, the step of the single chip controlling the processor to restart through the power module when the processor is detected to be in the dead halt state includes: the single chip microcomputer sends a processor power-off restarting instruction to the power module according to a processor restarting instruction input by a user; and after the power module receives a processor power-off restarting instruction, the power module executes a restarting operation of powering off and then powering on the processor.
In a preferred embodiment of the present invention, the step of the single chip controlling the processor to restart through the power module when the processor is detected to be in the dead halt state includes: and if the singlechip does not receive the processor restart instruction input by the user within the preset time, automatically sending a processor power-off restart instruction to the power module.
In a preferred embodiment of the present invention, the step of the single chip controlling the processor to restart through the power module when the processor is detected to be in the dead halt state includes: and when the processor is detected to be in a dead halt state, storing the data information in the memory of the processor into a memory of the single chip microcomputer.
In a preferred embodiment of the present invention, after the step of controlling the processor to restart by the single chip via the power module when the processor is detected to be in the dead halt state, the method includes: and if the restart completion of the processor is detected, sending the data information stored in the memory of the single chip microcomputer to the processor.
In a preferred embodiment of the present invention, the single chip is connected to the processor and the power module through a communication bus.
A crash handling device comprising: the system comprises a singlechip, a processor and a power module; the single chip microcomputer is used for sending a detection signal to the processor and sending a processor power-off restarting instruction to the power module when detecting that the processor is in a dead halt state; the processor is used for receiving the detection signal sent by the singlechip and sending feedback information to the singlechip; and the power supply module is used for receiving the processor power-off restarting instruction and executing the processor restarting operation of powering off and powering on the processor according to the processor power-off restarting instruction.
The technical effect achieved by adopting the technical scheme is as follows: the single chip microcomputer sends a detection signal to the processor, and confirms that the processor is in a dead halt state when feedback information sent by the processor is not received; the singlechip can be according to user's instruction or automatic control power module to cut off the power supply to the treater to make the treater restart in order to resume normal operating condition, promoted user experience.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are specifically described in detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a flowchart of a crash handling method according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a crash processing apparatus according to a second embodiment of the present invention.
Detailed Description
To further illustrate the technical measures and effects taken by the present invention to achieve the intended objects, embodiments of the present invention will be described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. While the present invention has been described in connection with the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications, equivalent arrangements, and specific embodiments thereof.
The appearances of the phrases "first," "second," and "third," or the like, in the specification, claims, and figures are not necessarily all referring to the particular order in which they are presented. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
In order to solve the problem of abnormal halt of a processor in the prior art, the invention provides a method and a device for handling the halt, and the invention is further described in detail below with reference to the accompanying drawings and the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating a crash handling method according to a first embodiment of the invention.
As shown in fig. 1, the crash processing method according to the first embodiment of the present invention includes the following steps:
step S11: the single chip microcomputer sends a detection signal to the processor.
Specifically, in one embodiment, the MCU: a Microcontroller Unit, also called a single chip microcomputer, generally operates a real-time operating system in a vehicle machine, and is mainly responsible for tasks with strong real-time performance such as power management, CAN communication, key processing and the like; MPU: the Main Processing Unit is a processor of a vehicle machine, most of control work in the vehicle machine is completed by an MPU, and the Main Processing Unit can be used for operating an android operating system.
In one embodiment, step S11: the step of sending the detection signal to the processor by the singlechip comprises the following steps: if the processor is in a working state, sending feedback information to the single chip microcomputer after receiving the detection signal; and if the single chip microcomputer does not receive the feedback information sent by the processor within the preset time, determining that the processor is in a dead halt state.
Specifically, the single chip microcomputer is in data communication with the processor through a communication bus; the processor sends a feedback message to the singlechip after receiving a detection signal sent by the singlechip in a normal working state so that the singlechip confirms that the processor is in the normal working state; and when the processor is in a dead halt state, the feedback information cannot be sent to the single chip microcomputer, so that the single chip microcomputer determines that the processor is dead halt when the single chip microcomputer does not receive the feedback information sent by the processor within the preset time.
In one embodiment, the single chip sends a detection signal to the processor according to a preset time interval. Specifically, during the process of executing the program to execute the task by the processor, the single chip sends a detection signal to the processor according to a preset time interval to judge whether the processor is halted. When the single chip microcomputer does not receive the feedback signal of the processor within a period of time, the single chip microcomputer sends the detection signal to the processor again, and when the feedback signal of the processor is not received continuously for multiple times, the single chip microcomputer confirms that the processor is in a dead halt state. The preset time interval may be 10 seconds, 30 seconds, 1 minute, 2 minutes, or other time units. The preset time interval may be changed according to the user's needs.
Step S12: and when the processor is detected to be in a dead halt state, the singlechip controls the processor to restart through the power module.
Specifically, in an embodiment, the single chip microcomputer and the processor are independent of each other, the single chip microcomputer and the processor are both connected with the power module, and the single chip microcomputer can control power supply of the processor by sending a power-off or power-on signal to the power module, so that power-off restart of the processor is realized.
In one embodiment, step S12: when detecting that the treater is in the dead halt state, the singlechip restarts through power module control treater, includes: the single chip microcomputer sends a processor power-off restarting instruction to the power module according to a processor restarting instruction input by a user; and after the power module receives a processor power-off restarting instruction, the power module executes a restarting operation of powering off and then powering on the processor.
Specifically, the connection between the power module and the processor is interrupted by the single chip microcomputer, the switch between the power module and the processor is mainly controlled by the single chip microcomputer, and when the switch between the power module and the processor is turned off by the single chip microcomputer, the processor is powered off. Wherein, can understand that, the power supply line of singlechip and the power supply line of treater are independent each other.
In another embodiment, after the single chip microcomputer receives a processor restart instruction input by a user, the single chip microcomputer sends a detection signal to the processor to judge whether the processor is in a dead halt state. When the processor is in a dead halt state, the single chip sends a processor power-off instruction to the power module; when the processor is in a normal working state, the working state information of the processor is displayed, and the restarting operation of the processor is stopped, so that the restarting of the processor caused by the fact that a user touches a restarting operation button on the terminal by mistake is avoided.
In one embodiment, step S12: when detecting that the treater is in the dead halt state, the singlechip restarts through power module control treater, includes: and if the singlechip does not receive the processor restart instruction input by the user within the preset time, automatically sending a processor power-off restart instruction to the power module.
It can be understood that, the preset time may be a time that the user modifies according to his or her own needs. For example, the preset time may be 1 minute, 2 minutes, 3 minutes, 4 minutes, 5 minutes, or other time units.
Specifically, after the single chip microcomputer detects that the processor is in a dead halt state, if a processor restart instruction input by a user is not received after a preset time, an automatic restart mechanism is entered. After entering an automatic restart mechanism, the single chip sends a processor power-off restart instruction to the power module to perform power-off restart on the processor.
In one embodiment, step S12: when detecting that the treater is in the dead halt state, the singlechip restarts through power module control treater, includes: and when the processor is detected to be in a dead halt state, storing the data information in the memory of the processor into a memory of the single chip microcomputer.
In one embodiment, step S12: when detecting that the treater is in the dead halt state, the singlechip restarts through power module control treater, later includes: and if the restart completion of the processor is detected, sending the data information stored in the memory of the single chip microcomputer to the processor.
Specifically, after the processor is restarted, the single chip sends a detection signal to the processor again to judge whether the processor is restarted successfully or not, and when the single chip detects a feedback signal sent by the processor, the processor is confirmed to be restarted successfully and is already in a normal working state. Therefore, the singlechip sends the data information stored in the memory to the processor, so that the processor recovers the working state before the halt, the operation steps of a user are reduced, and the data loss is avoided.
In one embodiment, the single chip is connected with the processor and the power supply module through a communication bus, so that the single chip, the processor and the power supply module can communicate with each other.
In the crash processing method provided by this embodiment, the single chip sends a detection signal to the processor, and when the feedback information of the processor is not received within a preset time, the single chip determines that the processor is in a crash state; the single chip microcomputer is connected with the power module through the terminal processor, so that the processor is restarted. Through the scheme, the processor can be automatically or manually controlled to restart when the processor crashes so as to recover the normal working state, and the user experience is improved.
Fig. 2 is a schematic structural diagram of a crash processing apparatus according to a second embodiment of the present invention.
As shown in fig. 2, a crash processing apparatus according to a second embodiment of the present invention includes: singlechip 10, processor 20 and power module 30.
Specifically, the single chip microcomputer 10 is configured to send a detection signal to the processor 20, and send a processor power-off and restart instruction to the power module 30 when detecting that the processor 20 is in a dead halt state. And the processor 20 is configured to receive the detection signal sent by the single chip microcomputer 10 and send feedback information to the single chip microcomputer 10. And the power module 30 is configured to receive a processor power-off restart instruction, and execute a processor restart operation of powering off and powering on the processor 20 according to the processor power-off restart instruction.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in fig. 1 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, in different orders, and may be performed alternately or at least partially with respect to other steps or other steps.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the specific details of the above embodiments, the above embodiments are exemplary, and are not to be construed as limiting the present invention, and various simple modifications can be made to the technical solution of the present invention within the scope of the technical idea of the present invention, and these simple modifications all belong to the protection scope of the present invention.
Claims (9)
1. A crash processing method is characterized by comprising the following steps:
the single chip microcomputer sends a detection signal to the processor;
and when the processor is detected to be in a dead halt state, the single chip microcomputer controls the processor to restart through the power module.
2. The crash processing method as claimed in claim 1, wherein the step of sending the detection signal to the processor by the single chip microcomputer comprises the steps of:
if the processor is in a working state, sending feedback information to the single chip microcomputer after receiving the detection signal;
and if the single chip microcomputer does not receive the feedback information sent by the processor within the preset time, confirming that the processor is in a halt state.
3. The crash processing method according to claim 1, wherein the single chip microcomputer sends the detection signal to the processor at preset time intervals.
4. The crash processing method according to claim 1, wherein the step of controlling the processor to restart through the power module by the single chip microcomputer when detecting that the processor is in the crash state comprises:
the single chip microcomputer sends a processor power-off restarting instruction to the power module according to a processor restarting instruction input by a user;
and after receiving the processor power-off restarting instruction, the power supply module executes the restarting operation of powering off and powering on the processor.
5. The crash processing method according to claim 1, wherein the step of controlling the processor to restart through the power module by the single chip microcomputer when detecting that the processor is in the crash state comprises:
and if the single chip microcomputer does not receive a processor restart instruction input by a user within the preset time, automatically sending the processor power-off restart instruction to the power supply module.
6. The crash processing method according to claim 1, wherein the step of controlling the processor to restart through the power module by the single chip microcomputer when detecting that the processor is in the crash state comprises:
and when the processor is detected to be in a dead halt state, storing the data information in the memory of the processor into the memory of the single chip microcomputer.
7. The crash processing method according to claim 6, wherein after the step of controlling the processor to restart by the single chip via the power module when the processor is detected to be in the crash state, the method comprises:
and if the processor is detected to be restarted, sending the data information stored in the memory of the single chip microcomputer to the processor.
8. The crash processing method according to claim 1, wherein the single chip microcomputer is connected with the processor and the power module through a communication bus.
9. A crash processing apparatus, comprising: the system comprises a singlechip, a processor and a power module;
the single chip microcomputer is used for sending a detection signal to the processor and sending a processor power-off restarting instruction to the power module when detecting that the processor is in a dead halt state;
the processor is used for receiving the detection signal sent by the singlechip and sending feedback information to the singlechip;
and the power supply module is used for receiving the processor power-off restarting instruction and executing the processor restarting operation of power-off and power-on to the processor according to the processor power-off restarting instruction.
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| CN201911086581.4A CN112783690A (en) | 2019-11-08 | 2019-11-08 | Crash processing method and device |
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| CN201911086581.4A CN112783690A (en) | 2019-11-08 | 2019-11-08 | Crash processing method and device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113608914A (en) * | 2021-08-10 | 2021-11-05 | 安谋科技（中国）有限公司 | Chip, chip function safety detection method, medium and electronic equipment |
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| CN203366017U (en) * | 2013-05-24 | 2013-12-25 | 海尔集团公司 | Building talk-back intelligent terminal and crash restart system for same |
| CN104331339A (en) * | 2014-11-20 | 2015-02-04 | 惠州Tcl移动通信有限公司 | Mobile terminal crash detecting method and system, and mobile terminal |
| CN105353692A (en) * | 2015-12-08 | 2016-02-24 | 天津七一二通信广播有限公司 | Intelligent monitor for industrial control computer crash processing and realization method |
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2019
- 2019-11-08 CN CN201911086581.4A patent/CN112783690A/en active Pending
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| US20070094487A1 (en) * | 2005-10-21 | 2007-04-26 | Inventec Corporation | Automatic resetting system and method |
| CN203366017U (en) * | 2013-05-24 | 2013-12-25 | 海尔集团公司 | Building talk-back intelligent terminal and crash restart system for same |
| CN104331339A (en) * | 2014-11-20 | 2015-02-04 | 惠州Tcl移动通信有限公司 | Mobile terminal crash detecting method and system, and mobile terminal |
| CN105353692A (en) * | 2015-12-08 | 2016-02-24 | 天津七一二通信广播有限公司 | Intelligent monitor for industrial control computer crash processing and realization method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113608914A (en) * | 2021-08-10 | 2021-11-05 | 安谋科技（中国）有限公司 | Chip, chip function safety detection method, medium and electronic equipment |
| CN113608914B (en) * | 2021-08-10 | 2024-04-26 | 安谋科技（中国）有限公司 | Chip, functional safety detection method of chip, medium and electronic equipment |
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Address after: Room 208, building 4, 1411 Yecheng Road, Jiading District, Shanghai, 201821 Applicant after: Botai vehicle networking technology (Shanghai) Co.,Ltd. Address before: Room 208, building 4, 1411 Yecheng Road, Jiading District, Shanghai, 201821 Applicant before: SHANGHAI PATEO ELECTRONIC EQUIPMENT MANUFACTURING Co.,Ltd. |
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