CN112468137A - Voltage controlled oscillator, phase-locked loop circuit and clock chip - Google Patents
Voltage controlled oscillator, phase-locked loop circuit and clock chip Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
The invention discloses a voltage-controlled oscillator, a phase-locked loop circuit and a clock chip, wherein the voltage-controlled oscillator comprises a plurality of delay units which are connected end to end, the differential input end of each delay unit is connected with the differential output end of the previous delay unit, and the differential output end of one delay unit outputs a differential output signal; the delay unit comprises a differential inversion unit and a positive feedback unit, the differential inversion unit changes the current of the first current source by adjusting the voltage-controlled control signal input by the adjusting field effect transistor, and the differential inversion unit outputs a differential output signal. The voltage-controlled control signal of field effect transistor is adjusted in the adjustment to the on-resistance of field effect transistor is adjusted in the change, and then influences the size of first current source and adjusts the frequency, has reduced voltage controlled oscillator's output frequency and has received the influence of power, and anti power noise interference's ability is strong, when being used for phase-locked loop circuit, has faster locking time.
Description
Technical Field
The present invention relates to a voltage controlled oscillator, and more particularly, to a phase locked loop circuit and a clock chip having the same.
Background
The voltage-controlled oscillator adjusts the oscillation signal of the output frequency according to the external voltage control signal, and the frequency of the oscillation signal can be changed by changing the external control voltage.
As shown in fig. 1, a conventional voltage-controlled oscillator has a plurality of inverter units connected in series, wherein M1x and M2x are configured asAn oscillation signal (with a period of T) is delayed by D through a single inverter, a PMOS transistor (M31, M32, M33) is connected between the source of each inverter P transistor and the power supply, the gate of the PMOS transistor is controlled by a voltage-controlled voltage Vc, and the drain current I satisfies: i ═ β (VDD-Vc)2. Where β is a constant related to process and PMOS transistor dimensions. The inverter signal delay D depends on the magnitude of I, when I is large, the inverter inter-electrode node can be charged and discharged more rapidly, and the smaller the signal delay D, D can be approximately considered to be in inverse proportion to I, i.e., D is K/I (K is a constant). The output frequency Fo of the oscillator satisfies:
it can be seen that the output frequency Fo is significantly affected by the voltage VDD. In a practical integrated circuit working environment, when VDD changes, there is an interfering ripple, and the ripple directly changes the Fo size, so that the frequency of the oscillator deviates from an expected output frequency point.
Disclosure of Invention
To solve the problems in the prior art, an object of the present invention is to provide a voltage controlled oscillator, and a phase locked loop circuit and a clock chip having the voltage controlled oscillator.
In order to achieve the above object, an embodiment of the present invention provides a voltage-controlled oscillator, which includes a plurality of delay units connected end to end, a differential input terminal of each delay unit is connected to a differential output terminal of a previous delay unit, and a differential output terminal of one delay unit simultaneously outputs a differential output signal to the outside;
the delay unit comprises a differential inversion unit, the differential inversion unit comprises an input differential pair, an adjusting field effect transistor M3 and a first current source M4 which are sequentially connected in series, the input differential pair comprises field effect transistors M1 and M2 which are connected in parallel, the gates of M1 and M2 respectively acquire differential input signals, the current inflow directions of M1 and M2 are respectively connected with the differential output end, the equivalent resistance value of the differential input signal is changed by adjusting a voltage control signal input by the gate of the adjusting field effect transistor M3, and the current magnitude of the first current source M4 and the frequency of the differential output signal are changed.
As a further improvement of the present invention, the positive feedback unit includes a pair of positive feedback adjustment M5 and M6, which shortens the delay time of the differential output signal by M5 and M6.
As a further improvement of the present invention, the positive feedback unit further includes a comparison fet M7, a second current source M8, and a comparison branch, wherein a comparison signal is input to a gate of the comparison fet M7, one end of the comparison branch is electrically connected between the adjustment fet M3 and the first current source M4, and the other end of the comparison branch is electrically connected between the comparison fet M7 and the second current source M8, when a voltage of the voltage-controlled control signal is smaller than the comparison signal, a speed of shortening a delay time of the differential output signal is increased, and when the voltage of the voltage-controlled control signal is greater than the comparison signal, a frequency overshoot of the voltage-controlled oscillator output signal is decreased.
As a further improvement of the present invention, the fets M3, M4, M7 and M8 are all configured as NMOS transistors, the drain of the adjusting fet M3 is connected to the input differential pair M1 and M2, the first current source M4 is connected between the source of the adjusting fet M3 and ground, the drain of the comparing fet M7 is connected to the positive feedback adjusting pair M5 and M6, and the second current source M8 is connected between the source of the comparing fet M7 and ground.
As a further improvement of the invention, M3 and M7 are the same size, M4 and M8 are the same size, the gates of M4 and M8 are input with the same DC bias voltage, and the comparison branch comprises a load R1.
As a further improvement of the present invention, the input differential pair M1 and M2 are configured as NMOS transistors, the differential inverting unit further includes a first load pair electrically connected to the drains of M1 and M2 and a voltage source, the regulating fet M3 is connected to the sources of M1 and M2;
the gates of the input differential pairs M1 and M2 are the differential inputs of the differential input signal, respectively;
the drains of the input differential pairs M1 and M2 are the differential output terminals of the differential output signal, respectively.
As a further improvement of the invention, the positive feedback regulation pairs M5 and M6 are set to be NMOS tubes, the gate of M5 and the drain of M6 are both connected with the output branch of the same differential output signal, the drain of M5 and the gate of M6 are both connected with the output branch of the other differential output signal, and the sources of M5 and M6 are both connected with the comparison field effect tube M7.
As a further improvement of the present invention, each of the delay units is connected to the same voltage control signal.
As a further improvement of the present invention, the number of the delay units is set to 2n +1, where n is a positive integer.
To achieve one of the above objects, an embodiment of the present invention provides a phase-locked loop circuit, including the voltage-controlled oscillator.
To achieve one of the above objects, an embodiment of the present invention provides a clock chip, which includes the voltage controlled oscillator.
Compared with the prior art, the invention has the following beneficial effects: the voltage-controlled control signal of the adjusting field-effect transistor M3 is adjusted to change the on-resistance of the adjusting field-effect transistor M3, so that the size of the first current source M4 is influenced to adjust the frequency, the influence of a power supply on the output frequency of the voltage-controlled oscillator is reduced, the power supply noise interference resistance is high, meanwhile, a positive feedback unit is introduced, the delay time of the output signal is shortened, the response speed is higher, and when the voltage-controlled control signal is used for a phase-locked loop circuit, the phase-locked loop circuit has higher locking time.
Drawings
Fig. 1 is a circuit diagram of a conventional voltage controlled oscillator;
fig. 2 is a block diagram of a voltage controlled oscillator circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a delay unit according to an embodiment of the present invention;
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
An embodiment of the present invention provides a voltage-controlled oscillator, and a phase-locked loop circuit and a clock chip having the voltage-controlled oscillator, where the circuit structure can reduce the influence of a power supply on the output frequency of the voltage-controlled oscillator, and has a strong power supply noise interference resistance.
Specifically, the voltage-controlled oscillator of this embodiment includes a plurality of delay units connected end to end, and the end to end manner of the delay units is as shown in fig. 2, a differential input end of each delay unit is connected to a differential output end of a previous delay unit, and a differential output end of one of the delay units simultaneously outputs a differential output signal to the outside; each delay unit receives differential input signals INP and INN through two differential input ports and outputs differential output signals OUTN and OUTP through two differential output ports, a port of a previous delay unit for receiving OUTN is connected with a port of a next delay unit for receiving INP, a port of the previous delay unit for receiving OUTP is connected with a port of the next delay unit for receiving INN, and one of the delay units outputs differential output signals Fo _ p and Fo _ n with a specific frequency to the outside.
The delay unit comprises a differential inversion unit, the differential inversion unit comprises an input differential pair M1 and M2, an adjusting field-effect tube M3 and a first current source M4 which are sequentially connected in series and used for inputting differential input signals, the input differential pair comprises field-effect tubes M1 and M2 which are connected in parallel, the gates of the M1 and the M2 respectively obtain the differential input signals, the current inflow directions of the M1 and the M2 are respectively connected with the differential output end, the gate of the adjusting field-effect tube M3 receives a voltage-controlled control signal Vc through an input signal port, the gate of the first current source M4 inputs a direct-current bias voltage Vbn through the input signal port, the direct-current bias voltage Vbn is larger than the threshold voltage of the M4, and the current magnitude of the first current source M4 is changed by adjusting the voltage-controlled control signal input by the gate of the adjusting field-effect tube M3.
In this embodiment, the input differential pairs M1, M2, M3 and M4 are illustrated as NMOS transistors, the differential inverting unit further includes a first load pair electrically connected to the drains of M1 and M2 and the voltage source, and the first load pair may be configured as resistors RL1 and RL2, as shown in fig. 3, or may be configured as equivalent MOS transistors. The regulating field effect transistor M3 is connected to the sources of M1 and M2;
the gates of the input differential pairs M1 and M2 are the differential inputs of the differential input signal, respectively;
the drains of the input differential pairs M1 and M2 are the differential output terminals of the differential output signal, respectively.
The first current source M4 generates a drain current I4 under the action of the external voltage Vbn, and the drain current I4 is influenced by the drain voltage V4 of M4 based on the channel length modulation effect of the MOS transistor M4. The differential inverting unit outputs a differential output signal, the frequency is recorded as Fo, and the differential output signal has stronger common-mode noise interference resistance.
Further, the delay units are set to be 2n +1, wherein n is a positive integer. That is to say, the number of the delay units can be set to 3, 5, 7, etc., each of the delay units is connected to the same voltage-controlled control signal, in this embodiment, as shown in fig. 2, the number of the delay units is set to 3, the voltage-controlled control signal Vc acts on the input signal ports of the three delay units, the signal delay of each delay unit is set to D, the signal delay is set to 3D after passing through the three inverters, and since the signal passes through the three inverters and then returns to the initial node, the phase of the signal at this time is the same as that at the beginning. Since three inverters invert the signal, the delay 3D of the signal needs to be equal to T/2 to return the signal to the in-phase state, and the frequency Fo of the oscillating signal is known as 1/6D. The frequency Fo of the vco output signal is 1/6D, which is determined by D of the delay unit.
The input differential pair M1, M2 is alternately turned on or off by the differential signals INP, INN, and I4 flows through the regulating fet M3 and then alternately flows through the input differential pair M1, M2. When INP is a rising edge, INN is a falling edge, M1 is turned on, M2 is turned off, I4 flows through M1, drain node OUTN of M1 discharges under the action of I4, the discharge current is approximately equal to I4, and signal delay D is approximately equal to Vo C/I4, where Vo is the swing of the output signal and C is the node parasitic capacitance of OUTN, it is known that the magnitude of I4 is approximately inversely proportional to delay D.
Therefore, adjusting the voltage control signal inputted to the gate of the fet M3 changes the equivalent resistance of M3, i.e., changes the Vds value at M3, and then changes the voltage at V4, and due to the channel length modulation effect, the change in V4 changes the magnitude of the current I4 of the first current source M4, and further changes the delay D, thereby changing the output frequency. That is, by changing the voltage control signal inputted to the gate of the fet M3, the current I4 of the first current source M4 can be changed, and the output frequency of the vco can be changed.
When INP is a rising edge, node OUTN starts discharging, and the discharge current is I, where V4 satisfies: V4-Vo-I RL1-Vds1-Vds3, where Vds1 is the drain-source voltage of M1, in this embodiment, the width-to-length ratio of the input differential pair M1 and M2 is a large value (> 100), the channel resistance is negligible, that is, Vds1 is approximately 0, and V4-Vo-I RL1-Vds3 is obtained. M3 operates in a linear region, which can be equivalent to a resistor R3, the magnitude of which is affected by a voltage control signal Vc, the larger Vc is the smaller R3, and the smaller Vc is the larger R3, so the magnitude of V4 is directly affected by Vc, and as can be seen from the channel length modulation effect, the larger V4 is the larger current I4 flowing through M4 is, the smaller V4 is the smaller current I4 flowing through M4 is, and the magnitude of I4 is approximately in inverse proportion to the delay D, so it can be deduced that the output frequency Fo of the oscillator approximately satisfies: fo ═ K × Vc. Where K is the gain of the VCO, and is a constant in Hz/V.
The mechanism of the voltage-controlled oscillator of this embodiment to change the output frequency is to change the on-resistance of the adjusting fet M3 operating in the linear region by the voltage-controlled control signal Vc, then change V4, change I4 by using the channel length modulation effect of M4, thereby changing the delay D of the delay cell, and finally controlling the output frequency. By the circuit structure design of the present embodiment, compared with the prior art in the background art, the influence of VDD on Fo is reduced.
The delay unit further comprises a positive feedback unit, the positive feedback unit comprises a positive feedback regulation pair M5 and M6, and the positive feedback regulation pair M5 and M6 shortens the delay time of the differential output signal.
In this embodiment, the positive feedback adjustment pairs M5 and M6 are illustrated by taking NMOS transistors as examples. The gate of M5 and the drain of M6 are both connected with the output branch of the same differential output signal, the drain of M5 and the gate of M6 are both connected with the output branch of another differential output signal, and the sources of M5 and M6 are both connected with the comparison field effect transistor M7, as shown in FIG. 3. The positive feedback adjustment has a positive feedback effect on M5 and M6, and for a distance, when OUTN is changed from low to high and OUTP is changed from high to low, the gate voltage of M6 is changed from low to high and the gate voltage of M5 is changed from high to low, at this time, the conduction capability of M6 is enhanced, so that OUTP is changed from high to low more quickly, and M5 is further turned off, so that OUTN is changed from low to high more quickly, and therefore, the i-delay D of the delay unit is reduced, namely, the constant K in the above formula Fo-Vc is increased. Conversely, when OUTN changes from high to low and OUTP changes from low to high, the conduction capability of M5 increases, making OUTN change from high to low faster, the conduction capability of M6 decreases, making OUTP change from low to high faster, also increasing the constant K, and the delay time decreases. When the circuit structure is applied to a phase-locked loop circuit, the circuit structure can have faster locking time. When the circuit is applied to a driving circuit, the driving capability of the circuit can be stronger.
Further, the positive feedback unit further includes a comparison fet M7, a second current source M8, and a comparison branch, wherein a gate of the comparison fet M7 inputs a comparison signal Vref, and the Vref is used to specify an ideal locking voltage when the voltage-controlled oscillator is used in a phase-locked loop system, one end of the comparison branch is electrically connected between the adjustment fet M3 and the first current source M4, and the other end of the comparison branch is electrically connected between the comparison fet M7 and the second current source M8, when the voltage of the voltage-controlled control signal is smaller than the comparison signal, the speed of shortening the delay time of the differential output signal is faster, and when the voltage of the voltage-controlled control signal is greater than the comparison signal, the frequency of overshoot of the voltage-controlled oscillator output signal is reduced.
Further, the fets M7 and M8 are both configured as NMOS transistors, the drain of the adjusting fet M3 is connected to the input differential pair M1 and M2, the first current source M4 is connected between the source of the adjusting fet M3 and ground, the drain of the comparing fet M7 is connected to the positive feedback adjusting pair M5 and M6, and the second current source M8 is connected between the source of the comparing fet M7 and ground.
And M3 and M7 are the same size, M4 and M8 are the same size, the gates of M4 and M8 input the same dc bias voltage, the comparison branch includes a load R1, as shown in fig. 3, M3 and M4 are symmetrically arranged with M7 and M8, and voltage drop Vds of M1, M2, M5 and M6 is close to 0, which can be seen as that when Vc equals Vref, V4 equals V8, current on R1 is 0, and K in the above equation is denoted as K0.
When Vc is less than Vref, V4 is less than V8, and a current flowing from V8 to V4 exists in the resistor R1, and the current increases the charging and discharging current flowing through the positive feedback unit of M7, so that the increase of K by the positive feedback unit is correspondingly increased, K at this time is denoted as K1, and K1 is greater than K0, so that the delay D at this time is more reduced relative to the stage of K0.
When Vc is greater than Vref, V4 is greater than V8, and a current flowing from V4 to V8 exists in the resistor R1, and this current suppresses the charging and discharging current flowing through the positive feedback unit of M7, so that the increasing effect of the positive feedback unit on K is reduced, where K is denoted as K2, and K2 is less than K0, so that the delay D at this time is reduced relative to the reduction amount at the K0 stage.
When the voltage-controlled oscillator is applied to a phase-locked loop system, Vref can be set as the control voltage for final locking of the phase-locked loop, and the locking process of the phase-locked loop is that Vc rises from 0 to Vref, then exceeds Vref to a peak value Vp, and then continues to fall back to Vref to reach the final locking state. In the process, when Vc is smaller than Vref, K is 1, K1 is more than K0, namely the locking time of the phase-locked loop is reduced, and when Vc exceeds Vref, K is 2, K2 is less than K0, the frequency overshoot of the phase-locked loop can be reduced, and the risk of timing errors of a system which is provided with a clock by the phase-locked loop is reduced. The voltage controlled oscillator has a faster lock time and less frequency overshoot when applied to a phase locked loop system, relative to the prior art.
The MOS transistors in this embodiment all use NMOS transistors as an example to perform the discussion of the connection relationship, and when the MOS transistors are replaced by PMOS transistors, those skilled in the art can reasonably replace the NMOS transistors.
Compared with the prior art, the embodiment has the following beneficial effects:
(1) the voltage-controlled control signal of the adjusting field-effect transistor M3 is adjusted to change the on-resistance of the adjusting field-effect transistor M3, so that the size of the first current source M4 is influenced to adjust the frequency, the influence of a power supply on the output frequency of the voltage-controlled oscillator is reduced, the power supply noise interference resistance is high, meanwhile, a positive feedback unit is introduced, the delay time of the output signal is shortened, the response speed is higher, and when the voltage-controlled control signal is used for a phase-locked loop circuit, the phase-locked loop circuit has higher locking time.
(2) When the voltage-controlled oscillator is applied to a phase-locked loop circuit, when the frequency is low and the phase-locked loop circuit is not locked, the voltage-controlled oscillator has larger gain and reduces the locking speed; when the frequency is higher and is not locked, the gain is smaller, the frequency overshoot is reduced, and the system transition is smoother when the Vc changes in the locking process of the phase-locked loop.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. A voltage-controlled oscillator is characterized by comprising a plurality of delay units which are connected end to end, wherein the differential input end of each delay unit is connected with the differential output end of the previous delay unit, and the differential output end of one delay unit simultaneously outputs differential output signals to the outside;
the delay unit comprises a differential inversion unit, the differential inversion unit comprises an input differential pair, an adjusting field effect transistor M3 and a first current source M4 which are sequentially connected in series, the input differential pair comprises field effect transistors M1 and M2 which are connected in parallel, the gates of M1 and M2 respectively acquire differential input signals, the current inflow directions of M1 and M2 are respectively connected with the differential output end, the equivalent resistance value of the differential input signal is changed by adjusting a voltage control signal input by the gate of the adjusting field effect transistor M3, and the current magnitude of the first current source M4 and the frequency of the differential output signal are changed.
2. The voltage controlled oscillator of claim 1, wherein the delay unit further comprises a positive feedback unit comprising a positive feedback regulation pair of M5 and M6, the positive feedback regulation pair of M5 and M6 shortening a delay time of the differential output signal.
3. The vco of claim 2, wherein the positive feedback unit further comprises a comparison fet M7, a second current source M8, and a comparison branch, a gate of the comparison fet M7 inputs a comparison signal, one end of the comparison branch is electrically connected between the adjustment fet M3 and the first current source M4, and the other end of the comparison branch is electrically connected between the comparison fet M7 and the second current source M8, the speed of the delay time of the differential output signal is faster when the voltage of the voltage-controlled control signal is smaller than the comparison signal, and the frequency overshoot of the output signal of the vco is reduced when the voltage of the voltage-controlled control signal is greater than the comparison signal.
4. The voltage-controlled oscillator of claim 3, wherein the FETs M3, M4, M7 and M8 are all configured as NMOS transistors, the drain of the regulator FET M3 is connected to the input differential pair M1 and M2, the first current source M4 is connected between the source of the regulator FET M3 and ground, the drain of the comparator FET M7 is connected to the positive feedback regulator pair M5 and M6, and the second current source M8 is connected between the source of the comparator FET M7 and ground.
5. The voltage-controlled oscillator of claim 4, wherein M3 and M7 are the same size, M4 and M8 are the same size, the gates of M4 and M8 are input with the same DC bias voltage, and the comparison branch comprises a load R1.
6. The voltage-controlled oscillator of claim 3, wherein the input differential pair M1 and M2 are configured as NMOS transistors, the differential inverting unit further comprises a first load pair electrically connected to the drains of M1 and M2 and a voltage source, the regulating FET M3 is connected to the sources of M1 and M2;
the gates of the input differential pairs M1 and M2 are the differential inputs of the differential input signal, respectively;
the drains of the input differential pairs M1 and M2 are the differential output terminals of the differential output signal, respectively.
7. The voltage-controlled oscillator of claim 6, wherein the positive feedback regulation pairs M5 and M6 are configured as NMOS transistors, the gate of M5 and the drain of M6 are both connected to the output branch of the same differential output signal, the drain of M5 and the gate of M6 are both connected to the output branch of another differential output signal, and the sources of M5 and M6 are both connected to the comparison FET M7.
8. The voltage controlled oscillator of claim 1, wherein the delay cells are set to 2n +1, where n is a positive integer.
9. A phase locked loop circuit comprising a voltage controlled oscillator as claimed in any one of claims 1 to 8.
10. A clock chip comprising a voltage controlled oscillator as claimed in any one of claims 1 to 8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011413180.8A CN112468137A (en) | 2020-12-04 | 2020-12-04 | Voltage controlled oscillator, phase-locked loop circuit and clock chip |
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| CN202011413180.8A CN112468137A (en) | 2020-12-04 | 2020-12-04 | Voltage controlled oscillator, phase-locked loop circuit and clock chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113054951A (en) * | 2021-03-26 | 2021-06-29 | 西安紫光国芯半导体有限公司 | Active resonant load circuit and clock tree driving circuit |
| CN113517887A (en) * | 2021-03-26 | 2021-10-19 | 西安紫光国芯半导体有限公司 | Resonant load circuit and driving circuit in application chip |
| WO2024011705A1 (en) * | 2022-07-14 | 2024-01-18 | 中国科学技术大学 | Voltage-controlled oscillator and clock generator based on voltage-controlled oscillator |
-
2020
- 2020-12-04 CN CN202011413180.8A patent/CN112468137A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113054951A (en) * | 2021-03-26 | 2021-06-29 | 西安紫光国芯半导体有限公司 | Active resonant load circuit and clock tree driving circuit |
| CN113517887A (en) * | 2021-03-26 | 2021-10-19 | 西安紫光国芯半导体有限公司 | Resonant load circuit and driving circuit in application chip |
| WO2024011705A1 (en) * | 2022-07-14 | 2024-01-18 | 中国科学技术大学 | Voltage-controlled oscillator and clock generator based on voltage-controlled oscillator |
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Application publication date: 20210309 |