CN113054951A - Active resonant load circuit and clock tree driving circuit - Google Patents
Active resonant load circuit and clock tree driving circuit Download PDFInfo
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- CN113054951A CN113054951A CN202110324636.1A CN202110324636A CN113054951A CN 113054951 A CN113054951 A CN 113054951A CN 202110324636 A CN202110324636 A CN 202110324636A CN 113054951 A CN113054951 A CN 113054951A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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Abstract
The embodiment of the application discloses active resonant load circuit and clock tree drive circuit, active resonant load circuit includes: at least one differential ring oscillator circuit; each differential ring-shaped oscillation circuit comprises three or more than three odd number of delay units which are electrically connected end to end, wherein the delay units are used for adjusting the oscillation frequency of the differential ring-shaped oscillation circuit to the frequency of a clock signal input into the differential ring-shaped oscillation circuit and amplifying the amplitude of the clock signal; and a second load adjusting unit is arranged between the negative phase output end of the previous delay unit and the positive phase input end of the next delay unit, and the positive phase input end and the negative phase input end are used for receiving clock signals. The problems that disturbance, noise or amplitude attenuation and the like can be generated in the circuit along with the transmission of clock signals in the conventional clock tree network circuit can be solved.
Description
Technical Field
The present application relates to the field of integrated circuit technology, and in particular, to an active resonant load circuit and a clock tree driving circuit.
Background
Existing clock signal transmission circuits (also called clock tree network circuits) are usually composed of standing wave circuit units or traveling wave circuit units. The standing wave circuit unit is usually composed of a CMOS (Complementary Metal Oxide Semiconductor), and in a clock tree network circuit composed of the standing wave unit circuits, a reflected waveform having the same frequency and a phase difference of 180 ° as the original waveform is formed by transmitting a clock signal waveform and reflecting at the end of a transmission line, and the original waveform and the reflected waveform are superimposed to form a standing wave; the standing waves have the same phase at each node of the transmission line, but the amplitude of the clock signal is lost along with the transmission of the clock signal, so that the amplitudes of the original waveform and the reflected waveform forming the standing wave are inconsistent, additional clock disturbance (skew) is caused, and the amplitude of the clock signal is attenuated. The ripple circuit unit is usually a closed loop formed by two inverters connected end to end, the waveform amplitude of the clock signal at each point in the closed loop is equal, but as the clock signal is transmitted, the phase of each point on the transmission line changes with the position, which causes an additional clock timing asynchronization problem, and thus generates different levels of noise (jitter). In addition, no matter the clock tree network circuit is composed of standing wave circuit units or traveling wave circuit units, as the working frequency of the circuit is higher and higher, the transmitted clock signals are more and more sensitive to disturbance and noise in the circuit.
Disclosure of Invention
The invention provides an active resonant load circuit and a clock tree driving circuit, which can solve the problem that a clock signal is transmitted along the existing clock tree network circuit and is disturbed by the circuit to generate noise or the amplitude value is attenuated.
In a first aspect, an active resonant load circuit includes: at least one differential ring oscillator circuit;
each differential ring oscillator circuit comprises three or more odd number of delay units which are electrically connected end to end, wherein the delay units are used for adjusting the oscillation frequency of the differential ring oscillator circuit to the frequency of a clock signal input into the differential ring oscillator circuit and amplifying the amplitude of the clock signal, a negative phase output end of a previous delay unit is electrically connected with a positive phase input end of a next delay unit, a positive phase output end of the previous delay unit is electrically connected with a negative phase input end of the next delay unit, and the positive phase input end and the negative phase input end are used for receiving the clock signal;
the differential ring oscillator circuit includes a second load adjustment unit disposed between the negative phase output terminal of a preceding delay unit and the positive phase input terminal of a succeeding delay unit.
According to one possible embodiment, the delay unit comprises: the first amplifying frequency modulation unit and the second amplifying frequency modulation unit are symmetrically arranged, and are respectively provided with a first load adjusting unit, wherein the first load adjusting unit is used for adjusting circuit loads of the first amplifying frequency modulation unit and the second amplifying frequency modulation unit so as to adjust the oscillation frequency of the differential ring-shaped oscillation circuit;
the clock signal comprises a positive phase clock signal and a negative phase clock signal;
the first amplification frequency modulation unit is electrically connected with the positive phase input end and the negative phase output end respectively, and is used for amplifying the amplitude of the positive phase clock signal and delaying the phase of the positive phase clock signal;
the second amplification frequency modulation unit is respectively connected with the negative phase input end and the positive phase output end, and is used for amplifying the amplitude of the negative phase clock signal and delaying the phase of the negative phase clock signal.
According to a possible implementation manner, the delay unit further comprises a fixed current source, the first amplification frequency modulation unit is further provided with a first MOS transistor, and the second amplification frequency modulation unit is further provided with a second MOS transistor;
the gate electrode of the first MOS tube is electrically connected with the positive phase input end, the drain electrode of the first MOS tube is electrically connected with the negative phase output end, and the source electrode of the first MOS tube is electrically connected with the fixed current source; one end of the first load adjusting unit corresponding to the first amplifying and frequency modulating unit is electrically connected with the negative phase output end, and the other end of the first load adjusting unit is used for accessing a high level;
a gate electrode of the second MOS transistor is electrically connected to the negative phase input terminal, a drain electrode of the second MOS transistor is electrically connected to the positive phase output terminal, and a source electrode of the second MOS transistor is electrically connected to the fixed current source; one end of the first load adjusting unit corresponding to the second amplifying and frequency modulating unit is electrically connected with the positive phase output end, and the other end of the first load adjusting unit is used for accessing a high level;
the first load regulation unit includes a series load regulation unit.
According to a possible embodiment, the first amplifying frequency modulation unit and the second amplifying frequency modulation unit are further respectively provided with an adjustable current source unit, and the adjustable current source unit is connected in parallel with the fixed current source.
According to a possible embodiment, the adjustable current source unit comprises a current source and a switch connected in series with the current source, and the current source is connected in series with the switch and then connected in parallel with the fixed current source.
According to a possible embodiment, the series load regulating unit comprises: the device comprises a fixed resistor and/or an adjustable resistor and a switch connected with the fixed resistor and/or the adjustable resistor in series.
According to a possible embodiment, the series load regulating unit comprises: and (4) an adjustable resistor.
According to a possible embodiment, the first load regulation unit further comprises a parallel load regulation unit comprising the series load regulation units in parallel.
According to a possible embodiment, the first load regulation unit further comprises a series capacitance regulation unit;
one end of the series capacitor adjusting unit corresponding to the first amplifying and frequency modulating unit is electrically connected with the negative phase output end, and the other end of the series capacitor adjusting unit is grounded;
one end of the series capacitor adjusting unit corresponding to the second amplification frequency modulation unit is electrically connected with the positive phase output end, and the other end of the series capacitor adjusting unit is grounded.
According to a possible embodiment, the first load adjusting unit further comprises a parallel capacitance adjusting unit comprising the series capacitance adjusting unit in parallel.
According to one possible embodiment, the series capacitance adjustment unit comprises: the circuit comprises a fixed capacitor and/or an adjustable capacitor and a switch connected with the fixed capacitor and/or the adjustable capacitor in series.
According to one possible embodiment, the series capacitance adjustment unit comprises: an adjustable capacitance.
According to one possible embodiment, the second load regulating unit comprises a resistor.
In a second aspect, a clock tree driving circuit includes: a clock tree network circuit, a buffer amplification circuit, DQs signal lines and the active resonant load circuit of the first aspect;
the buffer amplifying circuit is used for receiving a clock signal output by the clock tree network circuit, and the active resonant load circuit is electrically connected with the buffer amplifying circuit and the DQs signal line respectively.
In the active resonant load circuit and the clock tree driving circuit provided by this embodiment, each differential ring oscillator in the active resonant load circuit amplifies the amplitude of the clock signal step by step through a plurality of cascaded delay units, so that the amplitude of the clock signal output from the clock tree network circuit can be increased, and the amplitude of the clock signal attenuated from the clock tree network circuit can be recovered. In addition, the oscillation frequency of the differential ring-shaped oscillation circuit is adjusted by adjusting the circuit parameters of each delay unit, so that the oscillation frequency of the differential ring-shaped oscillation circuit is consistent with the frequency of the input clock signal, and it is easy to understand that the consistent situation in practical application can be regarded as infinite approach; in addition, the oscillation frequency of the differential ring oscillation circuit is consistent with the frequency of the input clock signal, the rising edge and the falling edge of the clock signal waveform can be optimized, noise can be optimized to the maximum extent, the common-mode noise suppression capability is stronger, therefore, the effects of eliminating or weakening interference and noise are achieved, and the response speed of the whole differential ring oscillation circuit can be improved.
Drawings
Fig. 1 is a schematic diagram of an active resonant load circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic circuit diagram of a differential ring oscillator circuit according to an embodiment of the present application;
fig. 3 is a schematic circuit diagram of another differential ring oscillator circuit provided in an embodiment of the present application;
fig. 4 is a schematic circuit diagram of a delay unit according to an embodiment of the present application;
FIG. 5 is a schematic circuit diagram of another delay cell provided in an embodiment of the present application;
FIG. 6 is a schematic circuit diagram of another delay unit provided in an embodiment of the present application;
FIG. 7 is a schematic circuit diagram of another delay cell provided in an embodiment of the present application;
FIG. 8a is an eye diagram of an output waveform of a noise simulation clock tree network circuit without introducing a resonant load circuit according to an embodiment of the present application;
fig. 8b is an eye diagram of an output waveform of a noise simulation clock tree network circuit after the resonant load circuit is introduced according to an embodiment of the present application;
fig. 9 is a schematic circuit diagram of a delay unit according to an embodiment of the present application;
FIG. 10 is a schematic circuit diagram of another delay cell provided in an embodiment of the present application;
FIG. 11 is a schematic circuit diagram of another delay cell provided in an embodiment of the present application;
FIG. 12a is an eye diagram of an output waveform of a noise simulation clock tree network circuit without introducing a resonant load circuit according to an embodiment of the present application;
FIG. 12b is an eye diagram of an output waveform of a noise simulation clock tree network circuit after the resonant load circuit is introduced according to an embodiment of the present application;
fig. 13 is a schematic structural block diagram of a clock tree driving circuit according to an embodiment of the present application.
Detailed Description
In order to better understand the technical solutions provided by the embodiments of the present specification, the technical solutions of the embodiments of the present specification are described in detail below with reference to the drawings and specific embodiments, and it should be understood that the specific features in the embodiments and examples of the present specification are detailed descriptions of the technical solutions of the embodiments of the present specification, and are not limitations on the technical solutions of the embodiments of the present specification, and the technical features in the embodiments and examples of the present specification may be combined with each other without conflict.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. The term "two or more" includes the case of two or more.
In view of the problem that the clock signal is transmitted along the existing clock tree network circuit, and the clock signal is disturbed by the circuit to generate noise or amplitude attenuation, the embodiment of the application provides an active resonant load circuit which can comprise at least one differential ring-shaped oscillating loop.
In a possible implementation, fig. 1 is a schematic diagram of an active resonant load circuit provided in an embodiment of the present application. As shown in fig. 1, the present embodiment provides an active resonant load circuit ARL including 2 differential ring oscillators DRO. Fig. 1 is only an illustration, and the number of the active resonant load circuit ARL including the differential ring oscillator circuit DRO may also be 1, 3, or more, and the present application is not limited in particular. The active resonant load circuit ARL may be connected after the clock tree network circuit for receiving the clock signals output by the clock tree network circuit, the different differential ring oscillator circuits DRO may receive clock signals of different phases, taking fig. 1 as an example for illustration, each differential ring oscillator DRO includes two phase input/output terminals, namely a positive phase input/output terminal and a negative phase input/output terminal, the positive phase input/output terminal and the negative phase input/output terminal can be WCK0(0 ° phase clock signal input/output terminal) and WCK180(180 ° phase clock signal input/output terminal), respectively, the phases of the clock signals received by the positive phase input/output terminal and the negative phase input/output terminal corresponding to the different differential ring oscillator DROs can be different, as shown in fig. 1, the phases of the clock signals corresponding to the positive phase input/output terminal WCK90 and the negative phase input/output terminal WCK270 of the other differential ring oscillator DRO are 90 ° and 270 °, respectively. Therefore, the number of the differential ring oscillator circuits DRO in the active resonant load circuit ARL can be set according to the number of pins of the clock tree network circuit outputting the clock signal.
In a possible embodiment, each differential ring oscillator circuit may include three or more odd number of delay units electrically connected end to end, wherein the delay units are configured to adjust an oscillation frequency of the differential ring oscillator circuit to a frequency of a clock signal input to the differential ring oscillator circuit and amplify an amplitude of the clock signal, a negative phase output terminal of a previous delay unit is electrically connected to a positive phase input terminal of a subsequent delay unit, a positive phase output terminal of the previous delay unit is electrically connected to a negative phase input terminal of the subsequent delay unit, and the positive phase input terminal and the negative phase input terminal are configured to receive the clock signal. Fig. 2 is a schematic circuit diagram of a differential ring oscillator according to an embodiment of the present application. As shown in fig. 2, the differential ring oscillator DRO mentioned in the above embodiment includes 3 delay units, D1, D2 and D3, and the delay units D1, D2 and D3 are electrically connected end to end in sequence to form a ring loop.
Fig. 3 is a schematic circuit diagram of another differential ring oscillator circuit provided in an embodiment of the present application. As shown in fig. 3, the differential ring oscillator DRO mentioned in the above embodiment includes 5 delay units, which are D1, D2, D3, D4 and D5, and the delay units D1, D2, D3, D4 and D5 are electrically connected end to end in sequence to form a ring.
Fig. 2 and 3 are only schematic, and the number of delay units included in the differential ring oscillator circuit is only required to be 3 or an odd number greater than 3, and the present application is not particularly limited.
Illustratively, in conjunction with fig. 2 and 3, each delay cell is provided with a positive phase input terminal Vinp, a negative phase input terminal Vinn, a positive phase output terminal Voutp, and a negative phase output terminal Voutn. In the differential ring oscillator circuit, the negative phase output terminal Voutn of the previous delay unit is electrically connected with the positive phase input terminal Vinp of the next delay unit, and the positive phase output terminal Voutp of the previous delay unit is electrically connected with the negative phase input terminal Vinn of the next delay unit. It should be noted that the former and the latter have relativity, but must be between two adjacent delay units. Exemplarily, as shown in fig. 2, between adjacent D1 and D2, D1 belongs to the former and D2 belongs to the latter; between adjacent D2 and D3, D2 belongs to the previous one, and D3 belongs to the next one; between adjacent D3 and D1, D3 belongs to the previous one, and D1 belongs to the next one; fig. 3 is the same as fig. 2. With reference to fig. 2 and fig. 3, a positive phase input/output end WCK0 can be led out between any adjacent negative phase output end Voutn and positive phase input end Vinp, and a negative phase input/output end WCK180 can be led out between any adjacent positive phase output end Voutp and negative phase input end Vinn. Each delay unit can be regarded as an equivalent amplifier, and can amplify the amplitude of an input clock signal, and the plurality of delay units amplify the amplitude of the clock signal step by step. The differential ring oscillator circuit formed by odd number of delay units can form a ring oscillator, and each delay unit can achieve the purpose of adjusting the oscillation frequency of the differential ring oscillator circuit by adjusting circuit parameters.
The active resonant load circuit provided by this embodiment is provided with one or more differential ring oscillator circuits, each differential ring oscillator circuit is formed by a plurality of cascaded delay units, the plurality of cascaded delay units amplify the amplitude of the clock signal step by step, and each delay unit can adjust the oscillation frequency of the differential ring oscillator circuit by adjusting circuit parameters.
The differential ring oscillator circuit further comprises a second load adjusting unit, wherein the second load adjusting unit is arranged between the negative phase output end of the previous delay unit and the positive phase input end of the next delay unit, and the second load adjusting unit is arranged between the positive phase output end of the previous delay unit and the negative phase input end of the next delay unit. The second load adjusting unit is arranged between the two adjacent delay units, the circuit load of the differential ring-shaped oscillation circuit can be further adjusted, the adjustable width and the adjustment precision of the oscillation frequency of the differential ring-shaped oscillation circuit are further increased, and the applicability of the differential ring-shaped oscillation circuit can be widened. It should be noted that the second load adjusting unit also participates in the phase delay of the clock signal, and the phase delay is equivalent to Δ P mentioned in the above embodiment.
In one possible embodiment, the second load regulation unit may include a resistor. For example, as shown in fig. 2, the resistor R3 may be an adjustable resistor or a fixed resistor, and the present application is not limited in particular.
Because the clock signal is transmitted along the existing clock tree network circuit, and the noise or amplitude attenuation generated by the clock signal due to circuit disturbance is introduced into the active resonant load circuit provided by the embodiment, each differential ring-shaped oscillation loop in the active resonant load circuit amplifies the amplitude of the clock signal step by step through a plurality of cascaded delay units, so that the amplitude of the clock signal output from the clock tree network circuit can be increased, and the amplitude of the clock signal attenuated from the clock tree network circuit is recovered. In addition, the oscillation frequency of the differential ring-shaped oscillation circuit is adjusted by adjusting the circuit parameters of each delay unit, so that the oscillation frequency of the differential ring-shaped oscillation circuit is consistent with the frequency of the input clock signal, and it is easy to understand that the consistent situation in practical application can be regarded as infinite approach; in addition, the oscillation frequency of the differential ring oscillation circuit is consistent with the frequency of the input clock signal, the rising edge and the falling edge of the clock signal waveform can be optimized, noise can be optimized to the maximum extent, the common-mode noise suppression capability is stronger, therefore, the effects of eliminating or weakening interference and noise are achieved, and the response speed of the whole differential ring oscillation circuit can be improved.
In another possible embodiment, the delay unit may include: the first amplifying frequency modulation unit and the second amplifying frequency modulation unit are symmetrically arranged, and are respectively provided with a first load adjusting unit, wherein the first load adjusting unit is used for adjusting circuit loads of the first amplifying frequency modulation unit and the second amplifying frequency modulation unit so as to adjust the oscillation frequency of the differential ring-shaped oscillation circuit; the clock signal includes a positive phase clock signal and a negative phase clock signal, and a phase difference between the positive phase clock signal and the negative phase clock signal is 180 °, so that a phase difference between a positive phase input-output end and a negative phase input-output end of the same differential ring oscillator circuit is 180 °. The first amplification frequency modulation unit is respectively electrically connected with the positive phase input end and the negative phase output end and is used for amplifying the amplitude of the positive phase clock signal and delaying the phase of the positive phase clock signal; the second amplification frequency modulation unit is respectively electrically connected with the negative phase input end and the positive phase output end, and is used for amplifying the amplitude of the negative phase clock signal and delaying the phase of the negative phase clock signal. Illustratively, each delay unit has the effect of phase delay on the input clock signal, the phase delay generated by each delay unit is 180 ° + Δ P, Δ P can be regarded as the equivalent phase delay of the first load adjusting unit, the phase delay of an odd number of delay units of 3 or more than 3 can satisfy an integer multiple of 360 °, and the gain of each delay unit is more than 1, and the two conditions are satisfied at the same time, the oscillation starting condition of the differential ring oscillator circuit can be achieved (the superposition of the delay phases of all the delay units is an integer multiple of 360 °). Specifically, taking fig. 2 as an example, the phase delay of each delay cell is 180 ° +60 °, and the phase delay of 3 delay cells is 720 ° (180 ° + 3+60 ° + 3). As shown in fig. 3, the phase delay of each delay unit is 180 ° +36 °, and the phase delay of 5 delay units is 1080 ° (180 ° + 5+36 ° + 5). The first amplifying frequency modulation unit and the second amplifying frequency modulation unit are symmetrically arranged, so that the delay of the two amplifying frequency modulation units to the phase of the clock signal is the same, but the phase difference of the clock signal input by the two amplifying frequency modulation units is 180 degrees.
In the active resonant load circuit provided by this embodiment, the first amplification frequency modulation unit and the second amplification frequency modulation unit that are symmetrical to each other are disposed in the delay unit, the first amplification frequency modulation unit amplifies the amplitude of the positive phase clock signal and delays the phase of the positive phase clock signal, and the second amplification frequency modulation unit amplifies the amplitude of the negative phase clock signal and delays the phase of the negative phase clock signal. The same first load adjusting units are respectively arranged in the first amplification frequency modulation unit and the second amplification frequency modulation unit, the circuit loads of the first amplification frequency modulation unit and the second amplification frequency modulation unit can be adjusted through the first load adjusting units, circuit current can be adjusted through adjusting the circuit loads, and then the oscillation frequency of the differential ring-shaped oscillation circuit can be adjusted.
Illustratively, under the condition that other conditions are not changed, the circuit resistances of the first amplifying frequency modulation unit and the second amplifying frequency modulation unit in each delay unit are synchronously increased by adjusting parameters in the first load adjusting unit, the circuit current is reduced, and the oscillation frequency is reduced; under the condition that other conditions are not changed, the circuit capacitance is synchronously increased by adjusting parameters in the first load adjusting unit, and the oscillation frequency is reduced. When the oscillation frequency of the differential ring oscillation circuit is higher than the frequency of the input clock signal, the oscillation frequency of the differential ring oscillation circuit needs to be adjusted downwards so that the oscillation frequency and the frequency of the differential ring oscillation circuit are infinitely consistent; when the oscillation frequency of the differential ring oscillator circuit is lower than the frequency of the input clock signal, the oscillation frequency of the differential ring oscillator circuit needs to be adjusted up so that the two will be infinitely consistent. The arrangement of the first load adjusting unit can increase the oscillation frequency bandwidth of the whole differential ring oscillation circuit, and the applicability of the differential ring oscillation circuit can be widened.
In a possible implementation manner, for example, fig. 4 is a schematic circuit diagram of a delay unit provided in an embodiment of the present application. As shown in fig. 4, the delay unit further includes a fixed current source i0, the first fm unit T1 is further provided with a first MOS transistor M1, and the second fm unit T2 is further provided with a second MOS transistor M2. The gate electrode of the first MOS transistor M1 is electrically connected to the positive phase input terminal Vinp, the drain electrode of the first MOS transistor M1 is electrically connected to the negative phase output terminal Voutn, the source electrode of the first MOS transistor M1 is used for being electrically connected to the fixed current source i0, and the other end of the fixed current source i0 is grounded; one end of the first load adjusting unit L1 corresponding to the first amplifying and frequency modulating unit T1 is electrically connected to the negative phase output terminal Voutn, and the other end is used for accessing a high level. The gate electrode of the second MOS transistor M2 is electrically connected to the negative phase input terminal Vinn, the drain electrode of the second MOS transistor M2 is electrically connected to the positive phase output terminal Voutp, and the source electrode of the second MOS transistor M2 is electrically connected to the fixed current source i 0; one end of the first load adjusting unit L1 corresponding to the second amplification frequency modulation unit T2 is electrically connected to the positive phase output terminal Voutp, and the other end is used for accessing a high level. The first MOS transistor M1 and the second MOS transistor M2 are used for generating a phase delay of 180 ° for the input clock signal. The fixed current source i0 is used for providing a basic operating current for the first MOS transistor M1 and the second MOS transistor M2, and can make the first MOS transistor M1 and the second MOS transistor M2 continuously conduct. The first MOS transistor M1 and the second MOS transistor M2 are respectively combined with the first load adjusting unit L1, and can amplify the amplitude of the respective input clock signals. The equivalent resistance of the first load adjusting unit L1 may generate a phase delay Δ P for the phase of the input clock signal such that each delay unit has a phase delay of 180 ° + Δ P for the input clock signal. For example, the first load regulating unit L1 may include a series load regulating unit. The first MOS tube and the second MOS tube can adopt NMOS tubes.
The active resonant load circuit provided by the embodiment can realize the effects of phase delay and amplitude amplification by adopting a circuit structure of combining the MOS tube with the load. The first load adjusting unit adopts the series load adjusting units to realize the adjustment of the load.
In a possible implementation manner, for example, fig. 5 is a schematic circuit diagram of another delay unit provided in an embodiment of the present application. As shown in fig. 5, the first amplifying frequency modulation unit T1 and the second amplifying frequency modulation unit T2 are further respectively provided with an adjustable current source unit a, and the adjustable current source unit a and the fixed current source i0 may be connected in parallel. For example, the adjustable current source unit a may include a current source i1 and a switch Si1 connected in series with the current source i1, and the current source i1 is connected in series with the switch Si1 and then connected in parallel with the fixed current source i 0. The switch Si1 is turned on or off to control whether the current source i1 is connected to the corresponding MOS transistor, and when the switch Si1 is turned on, the current source i1 is turned on to increase the operating current in the circuit. The two switches Si1 shown in fig. 5 may be opened and closed asynchronously or synchronously, the operating current in the circuit is increased in double, and the closing current alone is increased only in double. The parameters of the two current sources i1 may be the same or different, and the present application is not limited in particular.
The active resonant load circuit provided by the embodiment is additionally provided with the adjustable current source unit, and the current of the corresponding circuit can be adjusted by controlling the on-off of the adjustable current source unit, so that the adjustment of the first load adjusting unit on the circuit load can be assisted, the oscillation frequency bandwidth of the whole differential ring oscillation circuit can be further increased, and the applicability of the differential ring oscillation circuit can be widened.
In a possible implementation, the series load adjusting unit mentioned in the above embodiment may include: a fixed resistor and/or an adjustable resistor, and a switch in series with the fixed resistor and/or the adjustable resistor. Exemplarily, fig. 6 is a schematic circuit diagram of another delay unit provided in an embodiment of the present application. As shown in fig. 6, the series load adjusting unit mentioned in the foregoing embodiment may include a resistor R1 and a switch SR1, the resistor R1 is connected in series with the switch SR1, and the resistor R1 may adopt a trimming resistor or a fixed resistor. The switch SR1 is turned on or off to realize whether the resistor R1 is connected to the first amplifying frequency modulation unit or the second amplifying frequency modulation unit. For example, when the two switches SR1 are synchronously closed, the two resistors R1 are respectively connected to the first amplifying frequency modulation unit and the second amplifying frequency modulation unit, so that the resistance value in the circuit is increased, the current value is reduced, and the oscillation frequency is reduced. In addition, when the resistor R1 is an adjustable resistor, the resistance values of the two adjustable resistors R1 can be synchronously adjusted to change the resistance value in the circuit when the two switches SR1 are synchronously closed, so that the adjustment of the oscillation frequency is realized. Fig. 6 is a schematic diagram showing a case where a fixed current source i0 is connected, and the present application is not particularly limited. When the frequency of the input clock signal is greater than the oscillation frequency of the differential ring oscillation circuit, for example, the effect of down-regulating the oscillation frequency of the differential ring oscillation circuit is achieved by regulating the switch or the resistance value of the adjustable resistor, so that the frequency of the input clock signal and the oscillation frequency of the differential ring oscillation circuit tend to be the same. Specifically, the down-regulation of the oscillation frequency requires the load in the circuit to be reduced, and the two switches SR1 can be synchronously opened or the resistance values of the two adjustable resistors R1 can be synchronously adjusted down. The adjustable resistor is combined with the switch, so that the load adjusting range of the first load adjusting unit can be enlarged, the adjustable width of the oscillation frequency of the whole differential ring-shaped oscillation circuit can be further enlarged, and the applicability of the differential ring-shaped oscillation circuit can be widened.
In a possible implementation, the series load adjusting unit mentioned in the above embodiments may include an adjustable resistor. When the adjustable resistor has a large adjusting range, the adjustable resistor can independently realize the function of adjusting the circuit load.
In one possible embodiment, the first load regulation unit may further include a parallel load regulation unit, and the parallel load regulation unit may include a series load regulation unit connected in parallel. Exemplarily, fig. 7 is a schematic circuit diagram of another delay unit provided in an embodiment of the present application. As shown in fig. 7, the resistor R1 connected in series with the switch SR1 can be regarded as a series load adjusting unit, the resistor R2 connected in series with the switch SR2 can be regarded as a series load adjusting unit, and the two series load adjusting units are connected in parallel to form a parallel load adjusting unit. Fig. 7 is only an exemplary diagram, and the parallel load adjusting unit may further include more series load adjusting units, which is not limited in this application. In addition, the resistor R1 and the resistor R2 may adopt fixed resistors or adjustable resistors, and the resistance values of the fixed resistors and the adjustable resistors may be the same or different; the adjustable resistance ranges of the adjustable resistor R1 and the adjustable resistor R2 may be the same or different, the series load adjusting unit may only include an adjustable resistor and does not include a switch, and any combination may be made between the embodiments of the present application, which is not illustrated here. The parallel connection of the plurality of series load adjusting units can further enhance the resistance adjusting range and the resistance adjusting precision of the first load adjusting unit, further increase the adjustable width and the adjusting precision of the oscillation frequency of the differential ring-shaped oscillation circuit, and can widen the applicability of the differential ring-shaped oscillation circuit.
The noise in the circuit is simulated by additionally adding an interference signal to the power supply of the clock tree network circuit, wherein the interference signal can be a sinusoidal signal with the amplitude of 50mA and the frequency of 200HZ, and the waveform of the active resonant load circuit comprising the delay unit shown in FIG. 7 is simulated. FIG. 8a is an eye diagram of an output waveform of a noise simulation clock tree network circuit without introducing a resonant load circuit according to an embodiment of the present application; fig. 8b is an eye diagram of an output waveform of a noise simulation clock tree network circuit after the resonant load circuit is introduced according to an embodiment of the present application. The eye width of fig. 8a is 202p and the eye width of fig. 8b is 225p, the eye width being increased by about 11.4%. The eye skew of FIG. 8a is 73.1p, the eye skew of FIG. 8b is 52.3p, and the eye skew is improved by 28.5%. Therefore, as can be seen from fig. 8a and 8b, the active resonant load circuit provided by the embodiment of the present application can significantly optimize the skew of the clock signal. It should be noted that the smaller the eye pattern skew, the smaller the interference of the clock signal by the noise, the stronger the suppression capability of the circuit to the noise, and the larger the eye pattern width, the less error prone during the data reading process.
In one possible embodiment, the first load regulation unit may further include a series capacitance regulation unit. One end of the series capacitor adjusting unit corresponding to the first amplifying and frequency modulating unit is electrically connected with the negative phase output end, and the other end of the series capacitor adjusting unit is grounded; one end of the series capacitor adjusting unit corresponding to the second amplification frequency modulation unit is electrically connected with the positive phase output end, and the other end of the series capacitor adjusting unit is grounded. The series capacitor adjusting unit can adjust the circuit load through the adjustment of the capacitor, can increase the adjusting range and the adjusting precision of the first load adjusting unit to the circuit load, and further increases the adjusting range and the adjusting precision of the oscillating frequency of the differential ring-shaped oscillating circuit.
In a possible implementation, the series capacitance adjusting unit shown in the above embodiment may include: a fixed capacitor and/or an adjustable capacitor, and a switch in series with the fixed capacitor and/or the adjustable capacitor. Or the series capacitance adjusting unit comprises an adjustable capacitance. Exemplarily, fig. 9 is a schematic circuit diagram of a delay unit provided in an embodiment of the present application. As shown in fig. 9, the series capacitance adjustment may include an adjustable capacitance C1. One end of an adjustable capacitor C1 corresponding to the first amplifying and frequency modulating unit is connected to an equipotential point V1 between the series load adjusting unit and the negative phase output end Voutn, and the other end of the adjustable capacitor C1 is grounded. One end of an adjustable capacitor C1 corresponding to the second amplifying and frequency modulating unit is connected to an equipotential point V2 between the series load adjusting unit and the positive phase output end Voutp, and the other end of the adjustable capacitor C1 is grounded. Shown in fig. 9 is a series load regulation unit comprising a resistor R1 and a switch SR1 connected in series. Fig. 10 is a schematic circuit diagram of another delay unit provided in an embodiment of the present application. As shown in fig. 10, the first load adjusting unit includes a parallel load adjusting unit. The adjustable capacitor C1 may also be a series switch, and the C2 may also be a fixed capacitor, which are not listed here, but may be combined arbitrarily between the embodiments of the present application. The capacitor adjusting range of the first load adjusting unit can be further enlarged by the arrangement of the series capacitor adjusting unit, the load adjusting range and the adjusting precision of the differential ring-shaped oscillating circuit are further enlarged, the adjustable width of the oscillating frequency is further increased, and the applicability of the differential ring-shaped oscillating circuit can be widened.
In one possible embodiment, the first load adjusting unit may further include a parallel capacitance adjusting unit including series capacitance adjusting units connected in parallel. Exemplarily, fig. 11 is a schematic circuit diagram of another delay unit provided in an embodiment of the present application. As shown in fig. 11, the capacitor C1 and the capacitor C2 are respectively connected in series with a switch SC1 and a switch SC2, and the capacitor C1 and the capacitor C2 may adopt adjustable capacitors or fixed capacitors. The on-off of the switch SC1 and the switch SC2 can respectively control the on-off of the capacitor C1 and the capacitor C2, a plurality of series capacitor adjusting units are arranged to be connected in parallel, the capacitance value adjusting range and the capacitance value adjusting precision of the capacitor adjusting units can be further enlarged, the adjustable width and the adjusting precision of the oscillation frequency of the differential ring-shaped oscillation circuit can be further enlarged, and the applicability of the differential ring-shaped oscillation circuit can be widened.
Noise in the circuit is simulated by adding an interference signal to the power supply of the clock tree network circuit, wherein the interference signal can be a sinusoidal signal with the amplitude of 50mA and the frequency of 200HZ, and the waveform of the active resonant load circuit comprising the delay unit shown in FIG. 11 is simulated. FIG. 12a is an eye diagram of an output waveform of a noise simulation clock tree network circuit without introducing a resonant load circuit according to an embodiment of the present application; fig. 12b is an eye diagram of an output waveform of a noise simulation clock tree network circuit after the resonant load circuit is introduced according to an embodiment of the present application. The eye width of fig. 12a is 202p and the eye width of fig. 12b is 231p, the eye width being increased by about 14.4%. The eye skew of FIG. 12a is 73.2p, the eye skew of FIG. 12b is 44.3p, and the eye skew is improved by 39.4%. Therefore, as can be seen from fig. 12a and 12b, the active resonant load circuit provided by the embodiment of the present application can obviously optimize the skew of the clock signal. It should be noted that the smaller the eye pattern skew, the smaller the interference of the clock signal by the noise, the stronger the suppression capability of the circuit to the noise, and the larger the eye pattern width, the less error prone during the data reading process.
In a second aspect, an embodiment of the present application provides a clock tree driving circuit, including: a clock tree network circuit, a buffer amplifier circuit, DQs (Bi-d i rect i Data strobe bidirectional Data control pin) signal lines and an active resonant load circuit in any of the above embodiments; the buffer amplifying circuit is used for receiving clock signals output by the clock tree network circuit, and the active resonant load circuit is electrically connected with the buffer amplifying circuit and the DQs signal wires respectively. Exemplarily, fig. 13 is a schematic structural block diagram of a clock tree driving circuit provided in an embodiment of the present application. As shown in fig. 13, a clock tree driving circuit of the present embodiment includes: a clock tree network circuit WCKM, a signal line Q of a buffer amplifying circuit B, DQs and an active resonant load circuit ARL of any of the above embodiments; the clock tree network circuit WCKM is electrically connected with the buffer amplifying circuit B, the active resonant load circuit ARL comprises two differential ring-shaped oscillation circuits DRO, and the active resonant load circuit ARL is respectively electrically connected with the buffer amplifying circuit B and the DQs signal line Q. The clock signal WCK is transmitted to the Buffer amplifying circuit B from the clock tree network circuit WCKM, the Buffer amplifying circuit B can transmit the clock signal WCK to the active resonant load circuit ARL through the clock channel WCK Lane, and the Buffer amplifying circuit B can adopt a CML Buffer circuit.
The clock tree driving circuit provided in this embodiment is provided with an active resonant load circuit, where the active resonant load circuit includes at least one differential ring oscillator circuit, and the differential ring oscillator circuit amplifies the amplitude of a clock signal step by step through a plurality of cascaded delay units, so as to increase the amplitude of the clock signal output from the clock tree network circuit, recover the amplitude of the clock signal attenuated by the clock tree network circuit to a certain extent, and optimize the edges (rising edge and falling edge) of the clock signal. In addition, the oscillation frequency of the differential ring-shaped oscillation circuit is adjusted by adjusting the circuit parameters of each delay unit, so that the oscillation frequency of the differential ring-shaped oscillation circuit is consistent with the frequency of the input clock signal, and it is easy to understand that the consistent situation in practical application can be regarded as infinite approach; in addition, the oscillation frequency of the differential ring oscillation circuit is consistent with the frequency of the input clock signal, the rising edge and the falling edge of the clock signal waveform can be optimized, interference and noise can be eliminated or weakened, and the response speed of the whole differential ring oscillation circuit can be improved.
Additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the specification. Various modifications and alterations to this description may be made by those skilled in the art without departing from the spirit and scope of this description. It is intended that the present specification also cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (10)
1. An active resonant load circuit, comprising: at least one differential ring oscillator circuit;
each differential ring oscillator circuit comprises three or more odd number of delay units which are electrically connected end to end, wherein the delay units are used for adjusting the oscillation frequency of the differential ring oscillator circuit to the frequency of a clock signal input into the differential ring oscillator circuit and amplifying the amplitude of the clock signal, a negative phase output end of a previous delay unit is electrically connected with a positive phase input end of a next delay unit, a positive phase output end of the previous delay unit is electrically connected with a negative phase input end of the next delay unit, and the positive phase input end and the negative phase input end are used for receiving the clock signal;
the differential ring oscillator circuit includes a second load adjustment unit disposed between the negative phase output terminal of a preceding delay unit and the positive phase input terminal of a succeeding delay unit.
2. The active resonant load circuit of claim 1,
the delay unit includes: the first amplifying frequency modulation unit and the second amplifying frequency modulation unit are symmetrically arranged, and are respectively provided with a first load adjusting unit, wherein the first load adjusting unit is used for adjusting circuit loads of the first amplifying frequency modulation unit and the second amplifying frequency modulation unit so as to adjust the oscillation frequency of the differential ring-shaped oscillation circuit;
the clock signal comprises a positive phase clock signal and a negative phase clock signal;
the first amplification frequency modulation unit is electrically connected with the positive phase input end and the negative phase output end respectively, and is used for amplifying the amplitude of the positive phase clock signal and delaying the phase of the positive phase clock signal;
the second amplification frequency modulation unit is respectively connected with the negative phase input end and the positive phase output end, and is used for amplifying the amplitude of the negative phase clock signal and delaying the phase of the negative phase clock signal.
3. The active resonant load circuit of claim 2, wherein the delay unit further comprises a fixed current source, the first amplifying frequency modulation unit is further provided with a first MOS transistor, and the second amplifying frequency modulation unit is further provided with a second MOS transistor;
the gate electrode of the first MOS tube is electrically connected with the positive phase input end, the drain electrode of the first MOS tube is electrically connected with the negative phase output end, and the source electrode of the first MOS tube is electrically connected with the fixed current source; one end of the first load adjusting unit corresponding to the first amplifying and frequency modulating unit is electrically connected with the negative phase output end, and the other end of the first load adjusting unit is used for accessing a high level;
a gate electrode of the second MOS transistor is electrically connected to the negative phase input terminal, a drain electrode of the second MOS transistor is electrically connected to the positive phase output terminal, and a source electrode of the second MOS transistor is electrically connected to the fixed current source; one end of the first load adjusting unit corresponding to the second amplifying and frequency modulating unit is electrically connected with the positive phase output end, and the other end of the first load adjusting unit is used for accessing a high level;
the first load regulation unit includes a series load regulation unit.
4. The active resonant load circuit of claim 3, wherein the first amplifying frequency modulation unit and the second amplifying frequency modulation unit are further respectively provided with an adjustable current source unit, and the adjustable current source unit is connected in parallel with the fixed current source.
5. The active resonant load circuit of claim 4, wherein the adjustable current source unit comprises a current source and a switch connected in series with the current source, and the current source is connected in series with the switch and then connected in parallel with the fixed current source.
6. The active resonant load circuit of claim 3, wherein the series load adjustment unit comprises: the device comprises a fixed resistor and/or an adjustable resistor and a switch connected with the fixed resistor and/or the adjustable resistor in series.
7. The active resonant load circuit of claim 3, wherein the series load adjustment unit comprises: and (4) an adjustable resistor.
8. The active resonant load circuit of claim 6 or 7, wherein the first load regulation unit further comprises a parallel load regulation unit comprising the series load regulation units in parallel.
9. The active resonant load circuit of claim 8, wherein the first load regulation unit further comprises a series capacitance regulation unit;
one end of the series capacitor adjusting unit corresponding to the first amplifying and frequency modulating unit is electrically connected with the negative phase output end, and the other end of the series capacitor adjusting unit is grounded;
one end of the series capacitor adjusting unit corresponding to the second amplification frequency modulation unit is electrically connected with the positive phase output end, and the other end of the series capacitor adjusting unit is grounded.
10. A clock tree driving circuit, comprising: a clock tree network circuit, a buffer amplification circuit, DQs signal lines and an active resonant load circuit as claimed in any one of claims 1 to 9;
the buffer amplifying circuit is used for receiving a clock signal output by the clock tree network circuit, and the active resonant load circuit is electrically connected with the buffer amplifying circuit and the DQs signal line respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110324636.1A CN113054951A (en) | 2021-03-26 | 2021-03-26 | Active resonant load circuit and clock tree driving circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110324636.1A CN113054951A (en) | 2021-03-26 | 2021-03-26 | Active resonant load circuit and clock tree driving circuit |
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| CN113054951A true CN113054951A (en) | 2021-06-29 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281061A (en) * | 2010-06-08 | 2011-12-14 | 香港科技大学 | Method and apparatus for tuning frequency of lc-oscillators based on phase-tuning technique |
| CN112468137A (en) * | 2020-12-04 | 2021-03-09 | 中科威发半导体（苏州）有限公司 | Voltage controlled oscillator, phase-locked loop circuit and clock chip |
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2021
- 2021-03-26 CN CN202110324636.1A patent/CN113054951A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281061A (en) * | 2010-06-08 | 2011-12-14 | 香港科技大学 | Method and apparatus for tuning frequency of lc-oscillators based on phase-tuning technique |
| CN112468137A (en) * | 2020-12-04 | 2021-03-09 | 中科威发半导体（苏州）有限公司 | Voltage controlled oscillator, phase-locked loop circuit and clock chip |
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