CN112466368A

CN112466368A - Three-dimensional memory and control method thereof

Info

Publication number: CN112466368A
Application number: CN202011345682.1A
Authority: CN
Inventors: 谢学准; 宋雅丽; 靳磊; 赵向南; 闵园园; 贾建权
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-11-26
Filing date: 2020-11-26
Publication date: 2021-03-09
Anticipated expiration: 2040-11-26
Also published as: CN113838508A; CN112466368B; WO2022111060A1; CN113838508B

Abstract

The invention relates to a three-dimensional memory and a control method thereof, wherein the three-dimensional memory comprises a plurality of memory strings, each memory string comprises a plurality of memory cells, the memory cells comprise a first part and a second part, the diameter of a channel structure corresponding to the memory cells of the first part is smaller than that of a channel structure corresponding to the memory cells of the second part, and the method comprises the following steps: and applying a conducting voltage to unselected memory cells when reading the selected memory cell, wherein a first conducting voltage is applied to a first unselected memory cell in the first part, and a second conducting voltage is applied to a second unselected memory cell in the second part, and the first conducting voltage is smaller than the second conducting voltage. The method reduces the read interference of the memory cell with smaller channel structure diameter and improves the reliability of the three-dimensional memory.

Description

Three-dimensional memory and control method thereof

Technical Field

The invention relates to the field of manufacturing of integrated circuits, in particular to a three-dimensional memory and a control method thereof.

Background

In order to overcome the limitation of the two-dimensional memory device, a memory device having a three-dimensional (3D) structure, which increases integration density by arranging memory cells three-dimensionally over a substrate, has been developed and mass-produced in the industry. The 3D NAND flash memory is a three-dimensional memory device. As the number of stacked layers increases, the trench hole will be deeper and deeper. Since the upper aperture of the channel hole is larger than the lower aperture, the difference between the upper aperture and the lower aperture of the channel hole increases as the channel hole deepens. When the three-dimensional memory is read, the same conduction voltage is applied to each memory cell on the memory string formed by the same channel hole, and if the aperture of the channel hole where the memory cell is located is smaller, the electric field intensity brought to the memory cell by the conduction voltage is larger, and the memory cell is read and interfered after being read for many times.

Disclosure of Invention

The invention aims to provide a three-dimensional memory for reducing read interference and a control method thereof.

The present invention is directed to a method for controlling a three-dimensional memory, where the three-dimensional memory includes a plurality of memory strings, each of the memory strings includes a plurality of memory cells, and the plurality of memory cells includes a first portion and a second portion, and a diameter of a channel structure corresponding to a memory cell of the first portion is smaller than a diameter of a channel structure corresponding to a memory cell of the second portion, and the method includes: and applying a conducting voltage to unselected memory cells when reading the selected memory cell, wherein a first conducting voltage is applied to a first unselected memory cell in the first part, and a second conducting voltage is applied to a second unselected memory cell in the second part, and the first conducting voltage is smaller than the second conducting voltage.

In an embodiment of the present invention, the method further includes: when the selected memory cell is subjected to programming verification operation, applying the second breakover voltage to the second unselected memory cell, and if the first unselected memory cell is in a programming state, applying the first breakover voltage to the first unselected memory cell; and if the first unselected memory cell is in an erasing state, applying the second breakover voltage to the first unselected memory cell.

In an embodiment of the invention, the memory cells in the memory string are coupled to corresponding word lines, and the turn-on voltage is applied to the memory cells through the word lines.

In one embodiment of the present invention, when a read operation is performed on a selected memory cell, a read voltage is applied to a word line of the selected memory cell.

In one embodiment of the present invention, a program verify voltage is applied to a word line of a selected memory cell when a program verify operation is performed on the selected memory cell.

In an embodiment of the present invention, each memory cell is at a corresponding cell depth in the memory string, and a program operation is performed to a page of memory cells at the same cell depth layer by layer through the word lines along an extending direction of a channel structure of the memory string.

The present invention further provides a three-dimensional memory for solving the above technical problems, comprising: a memory cell array comprising a plurality of memory strings, each of the memory strings extending vertically above a substrate and comprising a plurality of memory cells arranged vertically in series; the plurality of memory cells comprise a first part and a second part, and the diameter of the channel structure of the memory cells of the first part is smaller than that of the channel structure of the memory cells of the second part; a controller configured to: when reading operation is carried out on the selected memory cell, applying a conducting voltage to unselected memory cells, wherein a first conducting voltage is applied to a first unselected memory cell in the first part, and a second conducting voltage is applied to a second unselected memory cell in the second part, and the first conducting voltage is smaller than the second conducting voltage.

In an embodiment of the invention, the controller is further configured to: when the selected memory cell is subjected to programming verification operation, applying the second breakover voltage to the second unselected memory cell, and if the first unselected memory cell is in a programming state, applying the first breakover voltage to the first unselected memory cell; and if the first unselected memory cell is in an erasing state, applying the second breakover voltage to the first unselected memory cell.

In an embodiment of the invention, the memory further comprises a plurality of word lines, each of the word lines being coupled to a page of memory cells at a same cell depth, wherein each memory cell is at a corresponding cell depth in the memory string.

In an embodiment of the present invention, a diameter of a channel structure of the memory string gradually increases from a bottom to a top of the memory string.

In an embodiment of the invention, the memory cells of the first portion are located below the memory cells of the second portion.

In an embodiment of the present invention, the memory string includes a first memory string and a second memory string stacked along an extending direction of the channel structure, a diameter of the channel structure of the first memory string gradually increases from a bottom to a top of the first memory string, and a diameter of the channel structure of the second memory string gradually increases from the bottom to the top of the second memory string.

In an embodiment of the present invention, a diameter of a channel structure at a top of the first memory string is larger than a diameter of a channel structure at a bottom of the second memory string.

In an embodiment of the invention, the three-dimensional memory is a 3D NAND flash memory.

According to the three-dimensional memory and the control method thereof, the first conduction voltage which is smaller than the normal conduction voltage is applied to the memory cell with the smaller diameter of the channel structure, so that the read interference of the part of the memory cells can be reduced. In addition, a smaller first conduction voltage is applied to the storage unit with the smaller-aperture channel structure in the programming verification stage, so that the read interference of the storage unit is further reduced, and the reliability of the three-dimensional memory is improved.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1 is a schematic diagram of a portion of a three-dimensional memory having a plurality of stacks;

FIGS. 2A and 2B are distribution diagrams of threshold voltages of memory cells in a three-dimensional memory;

FIG. 3 is a schematic illustration of the effect of read disturb on the E0 window;

FIG. 4 is an exemplary flow chart of a method of controlling a three-dimensional memory according to an embodiment of the present invention;

FIGS. 5A-5D are schematic diagrams illustrating the implementation of a control method for a three-dimensional memory according to an embodiment of the invention;

FIG. 6 is a schematic diagram illustrating an effect of a control method of a three-dimensional memory according to an embodiment of the invention;

FIGS. 7A-7D are schematic diagrams illustrating the implementation of a control method for a three-dimensional memory according to an embodiment of the invention;

FIG. 8 is a block diagram of a three-dimensional memory according to one embodiment of the invention;

FIG. 9 is a circuit schematic of a memory block that can be used with embodiments of the invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited.

The term "three-dimensional (3D) memory device" as used herein refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," e.g., NAND strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertically" means nominally perpendicular to a lateral surface of a substrate.

As used herein, the term "substrate" refers to a material upon which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

The term "layer" as used in this application refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, which may include one or more layers therein, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.

Fig. 1 is a partial structural diagram of a three-dimensional memory having a plurality of stacks. Referring to fig. 1, the three-dimensional memory includes two stacks (deck), a first stack 110 and a second stack 120. Each stack includes a

stack structure

111, 121 formed by alternately stacking gate layers and dielectric layers, and a

channel hole structure

112, 122 formed in the

stack structure

111, 121. As shown in fig. 1, in the first stack 110, the pore diameter at the top 114 of the trench pore structure 112 is larger than the pore diameter at the bottom 113. In the second stack 120, the aperture at the top 124 of the trench hole structure 122 is larger than the aperture at the bottom 123. At the intersection of the first stack 110 and the second stack 120, the channel aperture at the bottom 113 of the first stack 110 is smaller than the channel aperture at the top 124 of the second stack 120.

In an actual three-dimensional memory structure, the channel hole diameter gradually decreases from the top to the bottom of the channel hole along the extending direction of the channel hole structure. As the number of stacked layers in the

stacked structures

111, 121 increases, the

trench hole structures

112, 122 become deeper and deeper, and the aspect ratio thereof becomes larger, resulting in a larger difference between the aperture at the top and the aperture at the bottom of the

trench hole structures

112, 122.

Fig. 2A and 2B are distribution diagrams of threshold voltages of memory cells in a three-dimensional memory. The horizontal axis represents the threshold voltage Vt, and the vertical axis represents the number of memory cells. Fig. 2A and 2B exemplify a multi-level cell (MLC) technique, according to which each memory cell stores two bits of information, namely 00, 01, 10, and 11. The threshold voltage of the memory cell can be in four different states, namely the E state, the P1 state, the P2 state and the P3 state as shown in FIGS. 2A and 2B. Wherein, the E state is an erasing state corresponding to the erasing action, and the corresponding data format is 11; the P1, P2, and P3 states are all programmed states corresponding to a program operation, and correspond to data formats 00, 01, and 10, respectively.

Fig. 2A is a threshold voltage distribution diagram in a normal state. Referring to fig. 2A, there is a window distance between the states, which is divided into a plurality of windows, such as an E0 window and an E1 window between the E state and the P1 state, wherein the E0 window is close to the E state and the E1 window is close to the P1 state. By analogy, the window distances between the P1 state, the P2 state, and the P3 state are divided into E2 windows, E3 windows, E4 windows, E5 windows.

In a read operation of a memory cell, a read voltage (Vread) is applied to a gate of a read memory cell, and a pass voltage (Vpass) is applied to other memory cells in the same memory String (String) as the read memory cell, thereby turning on the memory cells. The turn-on voltage is also referred to as the transmission voltage, the turn-on voltage. A memory string may be understood as a string of memory cells distributed along the trench hole structure shown in fig. 1. For a small-aperture storage unit positioned at the bottom of a channel hole structure, the electric field intensity brought by the conducting voltage is larger, the tunneling effect is stronger, and a certain programming effect is generated on the storage unit. Especially for the memory cell in the erased state, since the threshold voltage is small, it is easily affected by the programming action of the turn-on voltage, so that the distribution of the erased state E state is widened, as shown in fig. 2B.

FIG. 2B is a graph of threshold voltage distribution for distribution broadening for an erased state. Referring to fig. 2B, the voltage distribution of the E0 state broadens in the direction closer to the P1 state, resulting in a smaller E0 window. Since the window of E0 is smaller, it may cause read errors to the E-state memory cells, thereby causing read disturb and reducing the reliability of data storage.

FIG. 3 is a graphical illustration of the effect of read disturb on the E0 window. As shown in FIG. 3, the horizontal axis represents the Word Line (WL) number of the three-dimensional memory from 0 to 127, which means that the three-dimensional memory is a 128-layer 3D NAND flash memory. Also, the three-dimensional memory includes 2 stacks as shown in fig. 1. The vertical axis in fig. 3 is the width of the E0 window, which is the median of the multiple test results. Referring to FIG. 3, the left half 310 of the horizontal axis shows the original state of the memory cell when it has not been programmed (Fresh), and the right half 320 shows the state of the memory cell after 300 programming passes (300 cyc).

Referring to fig. 3, four curves are included in each of the left half 310 and the right half 320, corresponding to different read times. The number of readings corresponding to the

curves

311 and 321 is 0, the number of readings corresponding to the

curves

312 and 322 is 1000, the number of readings corresponding to the curves 313 and 323 is 3000, and the number of readings corresponding to the

curves

314 and 324 is 30000. Obviously, the E0 window gradually shrinks as the number of reads increases. Since fig. 3 corresponds to a three-dimensional memory having 2 stacks as shown in fig. 1, wherein word line numbers 0-63 belong to the first stack, the numbers increase gradually from the bottom of the trench hole structure upwards; word line numbers 64-127 belong to the second stack.

Taking the left half 310 as an example, and referring to fig. 1 and 3, word line number 0 corresponds to the memory cell at the bottom of the trench hole structure. After multiple read operations, the size of the E0 window for memory cells in the first stack increases with increasing wordline number (0-63), and the size of the E0 window for memory cells in the second stack also increases with increasing wordline number (64-127). Thus, the E0 window for the memory location at the bottom of the stack is smallest, as shown by the first region 315 and the second region 316 circled in dashed lines in fig. 3, corresponding to the memory location at the bottom of the first stack and the memory location at the bottom of the second stack, respectively.

In right half 320, the E0 window for the memory cells after 300 programs is reduced compared to the E0 window for the memory cells of the original state that were not programmed. Otherwise, similar to the left half 310, the E0 windows for the memory cells at the bottom of the first stack and the memory cells at the bottom of the second stack are both relatively small, as shown by the third area 317 and the fourth area 318 encircled by the dashed lines in fig. 3.

Fig. 4 is an exemplary flowchart of a control method of a three-dimensional memory according to an embodiment of the present invention. The three-dimensional memory comprises a plurality of memory strings, each memory string comprises a plurality of memory cells, the plurality of memory cells comprise a first part and a second part, and the diameter of a channel structure corresponding to the memory cells of the first part is smaller than that of the channel structure corresponding to the memory cells of the second part. Referring to fig. 4, the control method of this embodiment includes the steps of:

step S410: and applying a conducting voltage to unselected memory cells when reading the selected memory cell, wherein the first conducting voltage is applied to a first unselected memory cell in the first part, and the second conducting voltage is applied to a second unselected memory cell in the second part, and the first conducting voltage is smaller than the second conducting voltage.

In some embodiments, the memory cells in the memory string of the three-dimensional memory are coupled to corresponding word lines, and the application of the turn-on voltage to the memory cells is achieved by applying the turn-on voltage to the word lines.

In some embodiments, in a read operation on a selected memory cell, a read voltage is applied to a word line of the selected memory cell.

Fig. 5A-5D are schematic diagrams illustrating the implementation of a control method for a three-dimensional memory according to an embodiment of the invention. The control method shown in fig. 4 will be described below with reference to fig. 5A to 5D.

Referring to fig. 5A, a schematic diagram of a three-dimensional memory having a total of 128 layers of 2 stacks is shown. Including a first stack 510 below and a second stack 520 above. The first stack 510 includes 64 gate layers: WL0-WL63, the second stack 520 also includes 64 gate layers: WL64-WL 127. Also included between the first stack 510 and the second stack 520 are some dummy gate layers 530, which portions of dummy gate layers 530 do not function as actual gates. It is understood that in the structure of the three-dimensional memory, the word line is connected to the gate layer, and a voltage may be applied to the gate layer connected thereto through the word line. The names of gate layers connected to different word lines are denoted by wl (wordline) in fig. 5A to 5D.

In this embodiment, the diameter of the channel structure corresponding to the memory cell is the aperture of the channel hole structure shown in fig. 1.

Referring to fig. 1 and fig. 5A, the aperture of the channel structure corresponding to the memory cell associated with the bottom gate layers in the first stack 510 is smaller, assuming that the number of the gate layers is about 15-20, that is, the memory cell of the first portion is located between the gate layers WL0-WL14 and WL0-WL 19.

The invention does not limit the number of the memory units of the first part and the second part, and does not limit the layer number of the corresponding gate layers. In an actual implementation of the control method, the ranges of the gate layers where the memory cells of the first portion and the second portion are located may be set as required.

The present invention is described with 16 layers as an example. Referring to FIG. 5A, memory cells corresponding to WL0-WL15 and WL64-WL79 belong to the first part in step S410, and memory cells in the remaining gate layer belong to the second part.

To explain step S410, the number of gate layers in which the selected memory cell is located is described.

In FIG. 5A, the selected memory cell 540 is between WL0-WL23, and the memory cells on the other gate layers are all unselected memory cells, including WL24-WL 127. When the read voltage Vread is applied to the selected memory cell 540, the pass voltage Vpass is applied to all the other unselected memory cells. Of these unselected memory cells, the memory cells located at WL64-WL78 belong to a first segment, which is referred to as first unselected memory cell 550. The remainder of the second portion includes memory cells located at WL24-WL63, WL79-WL127, which are referred to as second unselected memory cells 560. According to step S410, a first pass voltage Vpass1 is applied to a first unselected memory cell 550 belonging to the first section, and a second pass voltage Vpass2 is applied to a second unselected memory cell 560 belonging to the second section, Vpass1< Vpass 2.

Note that the selected memory cell 540 being between WL0-WL23 means that the selected memory cell 540 is located in any one or more layers between WL 0-W23. The selected memory cell 540 may be located in different memory strings, but the diameters of the channel structures corresponding to the memory cells 540 of different memory strings located on the same gate layer are substantially the same. If the selected memory cell 540 is in the layer of WL15, then the pass voltages are applied to the memory cells on the gate layer except WL15 in WL0-W23, that is, the first pass voltage Vpass1 is applied to WL0-WL14 belonging to the first portion, and the second pass voltage Vpass2 is applied to WL16-WL23 belonging to the second portion, according to the principle of step S410.

In FIG. 5B, the selected memory cell 540 is between WL24-WL55, and the memory cells on the other gate layers are all unselected memory cells. When the read voltage Vread is applied to the selected memory cell 540, the pass voltage Vpass is applied to all the other unselected memory cells. Of these unselected memory cells, the first unselected memory cell 550 includes memory cells in gate layers WL0-WL15, WL64-WL79, and the second unselected memory cell 560 includes memory cells in gate layers WL16-WL23, WL56-WL63, WL80-WL 127. According to step S410, a first pass voltage Vpass1 is applied to the first unselected memory cell 550, and a second pass voltage Vpass2 is applied to the second unselected memory cell 560, Vpass1< Vpass 2.

In FIG. 5C, the selected memory cell 540 is between WL56-WL87, and the memory cells on the other gate layers are all unselected memory cells. When the read voltage Vread is applied to the selected memory cell 540, the pass voltage Vpass is applied to all the other unselected memory cells. Of these unselected memory cells, first unselected memory cell 550 comprises memory cells in the gate layers WL0-WL15, and second unselected memory cell 560 comprises memory cells in the gate layers WL16-WL55, WL88-WL 127. According to step S410, a first pass voltage Vpass1 is applied to the first unselected memory cell 550, and a second pass voltage Vpass2 is applied to the second unselected memory cell 560, Vpass1< Vpass 2.

In FIG. 5D, selected memory cell 540 is between WL88-WL127, and the memory cells in the other gate layers are all unselected memory cells. When the read voltage Vread is applied to the selected memory cell 540, the pass voltage Vpass is applied to all the other unselected memory cells. Of these unselected memory cells, the first unselected memory cell 550 includes memory cells in gate layers WL0-WL15, WL64-WL79, and the second unselected memory cell 560 includes memory cells in gate layers WL16-WL63, WL80-WL 87. According to step S410, a first pass voltage Vpass1 is applied to the first unselected memory cell 550, and a second pass voltage Vpass2 is applied to the second unselected memory cell 560, Vpass1< Vpass 2.

In the above-described embodiment, the second pass voltage may be a normal pass voltage that is generally used, for example, Vpass2 ═ 6.5-7V. The first pass voltage is less than the normal pass voltage, e.g., Vpass1 ═ 6-6.5V. The first pass voltage Vpass1 is about 0.5V less than the second pass voltage Vpass 2.

Fig. 6 is a schematic diagram illustrating an effect of a control method of a three-dimensional memory according to an embodiment of the invention. Referring to FIG. 6, the horizontal axis is the word line number of the three-dimensional memory, from 0-127; the longitudinal axis is the width of the E0 window (E0 margin). Fig. 6 shows the average value of the E0 window obtained after 30000 read operations. Curve 610 shows the case where the second pass voltage Vpass2 is applied to all unselected cells, and curve 620 shows the case where the first pass voltage Vpass1 is applied to the first unselected memory cell and the second pass voltage Vpass2 is applied to the second unselected memory cell.

In the embodiment shown in fig. 6, Vpass1 is 6.2V and Vpass2 is 6.6V. As shown in FIG. 6, the Y-axis value of curve 620 is greater than the Y-axis value of curve 610 for memory cells near WL0-WL16 located at the bottom of the channel structure, i.e., the E0 window of memory cells near WL0-WL16 is increased according to the method of the present invention.

According to the control method of the three-dimensional memory, the first conduction voltage which is smaller than the normal conduction voltage is applied to the memory cell with the smaller diameter of the channel structure, and the read interference of the part of the memory cells can be reduced.

Referring to fig. 4, in some embodiments, the method for controlling a three-dimensional memory of the present invention further includes the steps of:

step 420: applying a second conduction voltage to a second unselected memory cell when the selected memory cell is subjected to programming verification operation, and applying a first conduction voltage to a first unselected memory cell if the first unselected memory cell is in a programmed state; if the first unselected memory cell is in the erased state, a second turn-on voltage is applied to the first unselected memory cell. Step 420 is described below in conjunction with fig. 7A-7D.

In some embodiments, in performing a program verify operation on a selected memory cell, a program verify voltage is applied to a word line of the selected memory cell.

Fig. 7A-7D are schematic diagrams illustrating the implementation of a control method for a three-dimensional memory according to an embodiment of the invention. Fig. 7A-7D show four different cases of the number of gate layers in which the selected memory cell is located, respectively.

Referring to fig. 7A, similar to fig. 5A, fig. 7A shows a schematic structural diagram of a three-dimensional memory having a total of 128 layers of 2 stacks. Including a first stack 710 below and a second stack 720 above. The first stack 710 includes 64 gate layers: WL0-WL63, the second stack 720 also includes 64 gate layers: WL64-WL 127. There are also some dummy gate layers 730 between the first stack 710 and the second stack 720, and this part of the dummy gate layer 730 does not function as an actual gate layer. The memory cells in the gate layers WL0-WL15 and WL64-WL79 correspond to a first portion having a small aperture channel structure, and the memory cells in the remaining gate layers correspond to a second portion having a larger aperture channel structure.

In FIG. 7A, selected memory cell 740 is between WL0-WL23, and the memory cells on other gate layers are all unselected memory cells, including WL24-WL 127. When the program verify voltage Vverify is applied to the selected memory cell 740, the pass voltage Vpass is applied to all the other unselected memory cells.

In some embodiments, each memory cell is at a corresponding cell depth in the memory string, and a program operation is performed by the word lines layer by layer to a page of memory cells at the same cell depth along an extending direction of a channel structure of the memory string. Referring to fig. 7A, in this embodiment, word line numbers increase from layer to layer upward along a first direction D1, the first direction D1 also corresponding to an extending direction of a channel structure of a memory string. WL0 corresponds to the bottom of the channel structure and WL127 corresponds to the top of the channel structure. Further, WL0 corresponds to the bottom of the channel structure of the first stack 710, WL63 corresponds to the top of the channel structure of the first stack 710; WL64 corresponds to the bottom of the channel structure of the second stack 720 and WL127 corresponds to the top of the channel structure of the second stack 720.

The unit depth of the memory cells in the same gate layer is the same, and the memory cells in the same unit depth form one page (page) of the three-dimensional memory. In the embodiment shown in FIGS. 7A-7D, the programming operation is performed layer by layer, starting with the bottommost layer WL 0.

During a program operation (which may also be understood as writing data), memory cells are programmed according to a word line programming sequence or other programming rules. For example, programming may begin at a word line at the source side of the memory block and continue to a word line at the drain side of the memory block. In one programming rule, each word line is programmed before proceeding to the next word line (i.e., programming in units of pages). Selecting one or more layers of the three-dimensional memory as a selection layer when programming; a programming voltage is applied to the selection layer, a bit line voltage is not applied to the bit line corresponding to the selected string, namely the bit line corresponding to the selected string is grounded, so that the selected string is programmed, and the other memory strings are inhibited.

Referring to FIG. 7A, selected memory cell 740 is between and among gate layers WL0-WL23, which may be one or more layers. In this state, the other gate layers WL24-WL127 are in the erased state without undergoing the programming operation, and therefore the pass voltage Vpass applied to the unselected memory cells of WL24-WL127 is the second pass voltage Vpass 2.

In FIG. 7B, the selected memory cell 741 is between WL24-WL55, and the memory cells in the other gate layers are all unselected memory cells. When the program verify voltage Vverify is applied to the selected memory cell 741, the pass voltage Vpass is applied to all the other unselected memory cells. Among these unselected memory cells, the second pass voltage Vpass2 is applied to the second unselected memory cell 761. The first unselected memory cell 750 on the gate layer WL0-WL15 has undergone the programming operation in FIG. 7A, and is in a programmed state, so that the first pass voltage Vpass1 is applied to the first unselected memory cell 750. Unselected memory cells 762 in gate layers WL56-WL127 are all in an erased state, so a second pass voltage Vpass2 is applied to these unselected memory cells 762, Vpass1< Vpass 2. The unselected memory cells 762 include a first unselected memory cell WL64-WL79 belonging to the first portion and a second unselected memory cell WL80-127 belonging to the second portion.

In FIG. 7C, the selected memory cell 742 is between WL56-WL87, and the memory cells on the other gate layers are all unselected memory cells. When the program verify voltage Vverify is applied to the selected memory cell 742, the pass voltage Vpass is applied to all the other unselected memory cells. Among these unselected memory cells, the second pass voltage Vpass2 is applied to a second unselected memory cell 763, which includes memory cells located in the gate layers WL16-WL55, WL88-WL127, among the second unselected memory cells 763. Also included in the unselected memory cells are first unselected memory cells 750 located in gate layers WL0-WL15, which have undergone the program operation in FIG. 7A and are in a programmed state, and thus a first pass voltage Vpass1 is applied to the first unselected memory cells 750.

In FIG. 7D, selected memory cell 743 is between WL88-WL127, and the memory cells in the other gate layers are all unselected memory cells. When the program verify voltage Vverify is applied to the selected memory cell 743, the pass voltage Vpass is applied to all other unselected memory cells. Among these unselected memory cells, the second pass voltage Vpass2 is applied to a second unselected memory cell 764, which includes memory cells located in the gate layers WL16-WL63, WL80-WL87, among the second unselected memory cells 764. Also included in the unselected memory cells are a first unselected memory cell 750 in the gate layer WL0-WL15 and a first unselected memory cell 751 in the gate layer WL64-WL79, which have undergone the programming operation in FIG. 7A and are in a programmed state, so that the first pass voltage Vpass1 is applied to both unselected

memory cells

750, 751.

Applying the program verify voltage Vverify to a memory cell is equivalent to a read operation, and also causes read disturb for a memory cell having a smaller aperture. According to the control method of the above embodiment, the read disturb of the program verify voltage can be reduced at the same time.

Fig. 7A-7D illustrate an embodiment of performing a program operation to WL127 layer by layer starting from gate layer WL 0. In other embodiments, the program operation can be performed from the gate layer WL127 down to the gate layer WL0, and the above operation method is also applicable to these embodiments.

FIG. 8 is a block diagram of a three-dimensional memory according to an embodiment of the invention. The aforementioned control method of the three-dimensional memory according to the present invention can be used to control the three-dimensional memory according to this embodiment, and therefore the aforementioned drawings and descriptions can be used to describe the three-dimensional memory according to the present invention.

Referring to fig. 8, the three-dimensional memory includes a memory cell array 810 and a controller 820. The memory cell array 810 includes a plurality of memory strings, each memory string extending vertically above a substrate and including a plurality of memory cells arranged vertically in series. The plurality of memory cells includes a first portion and a second portion, and a diameter of a channel structure of the memory cells of the first portion is smaller than a diameter of a channel structure of the memory cells of the second portion. The controller 820 is configured to apply a pass voltage Vpass to unselected memory cells when performing a read operation on selected memory cells, wherein a first pass voltage Vpass1 is applied to a first unselected memory cell in the first portion and a second pass voltage Vpass2 is applied to a second unselected memory cell in the second portion, wherein the first pass voltage Vpass1 is less than the second pass voltage Vpass 2.

In some embodiments, the controller 820 is further configured to: applying a second pass voltage Vpass2 to second unselected memory cells during a program verify operation on selected memory cells, and applying a first pass voltage Vpass1 to first unselected memory cells if the first unselected memory cells are in a programmed state; if the first unselected memory cell is in the erased state, the second pass voltage Vpass2 is applied to an unselected memory cell.

The controller 820 can implement the above-mentioned functions by using the control method of the three-dimensional memory of the present invention, and therefore the above-mentioned figures and descriptions can be used to describe the specific functions of the controller 820 of the three-dimensional memory of the present invention, and the same contents will not be expanded.

In the present embodiment, each memory cell included in the memory cell array 810 may be a single-level memory cell SLC in which 1-bit data is stored, or a multi-level memory cell (MLC) in which 2-bit or more data may be stored, such as MLC, TLC, QLC, and the like, or any combination of a single-level memory cell and a multi-level memory cell.

In the present embodiment, memory cells in the memory cell array 810 may be connected to word lines WL and bit lines BL. Meanwhile, the memory cell array 810 may also be connected to other selection lines such as a string selection line SSL, a ground selection line GSL, and the like. Specifically, the memory cell array 810 may be connected to a word line decoder 850 via a word line WL or a select line (SSL and/or GSL), and further connected to a voltage generator 860. The memory cell array 810 may be connected to a bit line decoder 830 via a bit line BL and further connected to an input/output (I/O) circuit 840. Controller 820 is coupled to bit line decoder 830, I/O circuit 840, word line decoder 850, and voltage generator 860, respectively.

When one or more memory cells need to be erased, programmed, read, or verified, the controller 820 can send the address of the one or more memory cells to the bit line decoder 830 and the word line decoder 850, and then be addressed by the bit line BL via the bit line decoder 830 and by the word line WL via the word line decoder 850.

In some embodiments, the functions of the bit line decoder 830 and the word line decoder 850 may be implemented by a unified address decoder. The address decoder may also include components such as an address buffer.

The I/O circuit 840 may receive data from the controller 820 and/or the outside and store the received data in the memory cell array 810 for a write operation, on the one hand, and may read data from the memory cell array 810 and output the read data to the controller 820 and/or the outside for a read operation, on the other hand.

The voltage generator 860 may generate various voltages for performing operations of erasing, programming, reading, writing, verifying, and the like on the memory cell array 810 in response to a control signal from the controller 820. Specifically, the voltage generator 860 may generate a word line voltage, such as a program voltage (or a write voltage), a program inhibit voltage, a read voltage, a verify voltage, and the like. The voltage generator 860 may generate a bit line voltage, such as a bit line force voltage or an inhibit voltage. In an embodiment of the present invention, the voltage generator 860 may generate the pass voltages Vpass described above, including the first pass voltage Vpass1 and the second pass voltage Vpass2, as well as the read voltage Vread, the program verify voltage Vverify, and the like.

The controller 820 may output control signals to the bit line decoder 830, the I/O circuit 840, the word line decoder 850, and the voltage generator 860. For example, controller 820 may output voltage control signals to voltage generator 860, word line addresses to word line decoder 850, bit line addresses to bit line decoder 830, write data to I/O circuit 840 and read data from I/O circuit 840.

In some embodiments, the controller 820 controls the bit line decoder 830 to select some bit lines BL and controls the word line decoder 850 to select some bit lines WL, and the voltage generator 860 applies a certain voltage to these bit lines BL and word lines WL. For example, during a read operation, a read voltage may be applied to a selected word line WL, and for a memory cell inhibited from reading, a read inhibit voltage may be applied to unselected bit lines BL. During a program operation, a program voltage and a verify voltage may be applied to a selected word line WL, and a program inhibit voltage may be applied to unselected bit lines BL.

The controller 820 of the embodiment of the present invention may further include a processor, an I/O interface, and the like. The control logic of controller 820 to bit line decoder 830, I/O circuit 840, word line decoder 850, and voltage generator 860 is not limited to that described above. The controller 820 may also implement any other logic control functions for the non-volatile memory as will be appreciated by those skilled in the art.

In some embodiments, the controller 820 may instruct the memory cell array 810 to perform desired memory operations based on software.

In an embodiment of the present invention, the memory strings extend vertically above the substrate. The substrate may be a Silicon substrate (Si), a Germanium substrate (Ge), a Silicon Germanium substrate (SiGe), a Silicon On Insulator (SOI), a Germanium On Insulator (GOI), or the like. In some embodiments, the substrate may also be a substrate comprising other elemental or compound semiconductors, such as GaAs, InP, SiC, or the like. But also a stacked structure such as Si/SiGe or the like. Other epitaxial structures may also be included, such as Silicon Germanium On Insulator (SGOI) and the like. In some embodiments, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers, among others. The substrate may have undergone some necessary processing, such as having formed the common active region and having undergone necessary cleaning, etc.

A stack structure, which may be a stack of alternating layers of a first material and a second material, is included over the substrate. The first material layer and the second material layer may be selected from materials and include at least one insulating dielectric such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and the like, and combinations thereof. The first material layer and the second material layer have different etching selectivity. For example, a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, or the like may be used. The deposition method of the first material layer and the second material layer of the stack structure may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), Atomic Layer Deposition (ALD), or a physical vapor deposition method such as Molecular Beam Epitaxy (MBE), thermal oxidation, evaporation, sputtering, and the like, among various methods thereof. In an embodiment of the invention, the first material layer may be a gate layer, and the second material layer is a dielectric layer. The gate layer may be formed after removing the dummy gate layer. The material for the gate sacrificial layer may be, for example, a silicon nitride layer. The material for the gate layer may be a conductive material such as tungsten, cobalt, copper, nickel, etc., or may be polysilicon, doped silicon, or any combination thereof. The material for the dielectric layer may be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like.

In an embodiment of the invention, the material of the substrate is, for example, silicon. The first material layer and the second material layer are, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, a stacked structure may be formed by alternately depositing silicon nitride and silicon oxide on a substrate in sequence by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable deposition methods.

Although exemplary configurations of the initial semiconductor structure are described herein, it will be appreciated that one or more features may be omitted, substituted, or added to the semiconductor structure. For example, various well regions may be formed in the substrate as desired. In addition, the materials of the various layers illustrated are merely exemplary, e.g., the substrate may also be other silicon-containing substrates, such as SOI (silicon on insulator), SiGe, Si: C, etc. The gate layer may also be other conductive layers such as tungsten, cobalt, nickel, etc. The second material layer may also be other dielectric materials such as aluminum oxide, hafnium oxide, tantalum oxide, and the like.

A channel structure corresponding to the memory cell may be formed in a channel hole vertically passing through the stack structure, and thus the channel structure may be cylindrical. The channel structure may include a channel layer and a memory layer. Viewed from the whole, the memory layer and the channel layer are arranged in sequence from the outside to the inside in the radial direction of the channel structure. The memory layer may include a blocking layer, a charge trapping layer, and a tunneling layer sequentially arranged from outside to inside in a radial direction of the channel structure. A filling layer can be arranged in the channel layer. The filler layer may function as a support. The material of the fill layer may be silicon oxide. The filling layer can be solid or hollow without affecting the reliability of the device. The formation of the channel structure may be accomplished using one or more thin film deposition processes, such as ALD, CVD, PVD, the like, or any combination thereof.

In some embodiments, the three-dimensional memory of the present invention further comprises a plurality of word lines, each word line coupled to a page of memory cells at the same cell depth, wherein each memory cell is at a corresponding cell depth in a memory string.

FIG. 9 is a circuit schematic of a memory block that can be used with embodiments of the invention. The memory cell array 810 shown in fig. 8 may include several memory blocks. Referring to fig. 9, where mc (memory cell) represents a memory cell, each memory cell has a corresponding cell depth. For example, memory cell MC in fig. 9 is in the gate layer to which word line WL8 is coupled. The memory string STR connects a plurality of memory cells in series along the increasing number of layers of word lines WL1-WL 8. Memory cells at the same cell depth are in the same PAGE (PAGE). The controller 820 generates voltages to be applied to the respective word lines according to the set control voltage generator 860, thereby controlling the voltages applied to each memory cell.

Each string STR may further include a string selection transistor SST and a ground selection transistor GST respectively connected to both ends of the memory cells MC connected in series. CSL is a common source line. The number of memory strings STR, the number of word lines WL, and the number of bit lines BL may vary according to embodiments.

The illustration in fig. 9 is merely an example, and is not intended to limit the specific structure of the three-dimensional memory, the number of layers of word lines, and the like of the present invention.

In some embodiments, the diameter of the channel structure of the memory string of the present invention gradually increases from the bottom to the top of the memory string.

In some embodiments, the memory cells of the first portion are located below the memory cells of the second portion.

In some embodiments, the memory strings include a first memory string and a second memory string stacked along an extension direction of the channel structure, the channel structure of the first memory string having a diameter gradually increasing from a bottom to a top of the first memory string, and the channel structure of the second memory string having a diameter gradually increasing from the bottom to the top of the second memory string. Wherein a diameter of the channel structure at the top of the first memory string may be larger than a diameter of the channel structure at the bottom of the second memory string. The structure of the three-dimensional memory of these embodiments can be seen with reference to fig. 1, and the three-dimensional memory includes more than 2 stacks, each stack including a channel structure with a small bottom and a large top.

In some embodiments, the three-dimensional memory of the present invention is a 3D NAND flash memory.

When the three-dimensional memory is used for reading, a smaller first conduction voltage is applied to the memory unit with a smaller aperture channel structure, so that the reading interference of the memory unit can be effectively reduced; in addition, a smaller first conduction voltage is applied to the storage unit with the smaller-aperture channel structure in the programming verification stage, so that the read interference of the storage unit is further reduced, and the reliability of the three-dimensional memory is improved.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims

1. A method for controlling a three-dimensional memory, the three-dimensional memory comprising a plurality of memory strings, each of the memory strings comprising a plurality of memory cells, the plurality of memory cells comprising a first portion and a second portion, wherein a diameter of a channel structure corresponding to a memory cell of the first portion is smaller than a diameter of a channel structure corresponding to a memory cell of the second portion, the method comprising:

and applying a conducting voltage to unselected memory cells when reading the selected memory cell, wherein a first conducting voltage is applied to a first unselected memory cell in the first part, and a second conducting voltage is applied to a second unselected memory cell in the second part, and the first conducting voltage is smaller than the second conducting voltage.

2. The control method according to claim 1, further comprising: when the selected memory cell is subjected to programming verification operation, applying the second breakover voltage to the second unselected memory cell, and if the first unselected memory cell is in a programming state, applying the first breakover voltage to the first unselected memory cell; and if the first unselected memory cell is in an erasing state, applying the second breakover voltage to the first unselected memory cell.

3. The method of claim 1, wherein the memory cells in the memory string are coupled to corresponding word lines, the turn-on voltage being applied to the memory cells through the word lines.

4. The control method of claim 3, wherein in the read operation of the selected memory cell, a read voltage is applied to a word line of the selected memory cell.

5. The control method of claim 3, wherein a program verify voltage is applied to a word line of a selected memory cell when a program verify operation is performed on the selected memory cell.

6. The control method of claim 3, wherein each memory cell is at a corresponding cell depth in the memory string, and a programming operation is performed by the word lines layer by layer along an extension direction of a channel structure of the memory string to a page of memory cells at the same cell depth.

7. A three-dimensional memory, comprising:

a memory cell array comprising a plurality of memory strings, each of the memory strings extending vertically above a substrate and comprising a plurality of memory cells arranged vertically in series;

the plurality of memory cells comprise a first part and a second part, and the diameter of the channel structure of the memory cells of the first part is smaller than that of the channel structure of the memory cells of the second part;

a controller configured to: when reading operation is carried out on the selected memory cell, applying a conducting voltage to unselected memory cells, wherein a first conducting voltage is applied to a first unselected memory cell in the first part, and a second conducting voltage is applied to a second unselected memory cell in the second part, and the first conducting voltage is smaller than the second conducting voltage.

8. The three-dimensional memory of claim 7, wherein the controller is further configured to: when the selected memory cell is subjected to programming verification operation, applying the second breakover voltage to the second unselected memory cell, and if the first unselected memory cell is in a programming state, applying the first breakover voltage to the first unselected memory cell; and if the first unselected memory cell is in an erasing state, applying the second breakover voltage to the first unselected memory cell.

9. The three-dimensional memory of claim 7, further comprising a plurality of word lines, each coupled to a page of memory cells at a same cell depth, wherein each memory cell is at a corresponding cell depth in the memory string.

10. The three-dimensional memory of claim 7, wherein a diameter of the channel structure of the memory string gradually increases from a bottom to a top of the memory string.

11. The three-dimensional memory according to claim 7, wherein the memory cells of the first portion are located below the memory cells of the second portion.

12. The three-dimensional memory of claim 7, wherein the memory string comprises a first memory string and a second memory string stacked along an extension direction of the channel structure, a diameter of the channel structure of the first memory string gradually increases from a bottom to a top of the first memory string, and a diameter of the channel structure of the second memory string gradually increases from the bottom to the top of the second memory string.

13. The three-dimensional memory of claim 12, wherein a diameter of the channel structure at a top of the first memory string is larger than a diameter of the channel structure at a bottom of the second memory string.

14. The three-dimensional memory according to claim 7, wherein the three-dimensional memory is a 3D NAND flash memory.